Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	510	1			T19	7		T35	14		T36	4
all_values[1]	510	1			T19	7		T35	14		T36	4
all_values[2]	510	1			T19	7		T35	14		T36	4
all_values[3]	510	1			T19	7		T35	14		T36	4
all_values[4]	510	1			T19	7		T35	14		T36	4
all_values[5]	510	1			T19	7		T35	14		T36	4
all_values[6]	510	1			T19	7		T35	14		T36	4
all_values[7]	510	1			T19	7		T35	14		T36	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2248

1

T19

26

T35

62

T36

16

auto[1]

1832

1

T19

30

T35

50

T36

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1661

1

T19

18

T35

47

T36

18

auto[1]

2419

1

T19

38

T35

65

T36

14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2342

1

T19

31

T35

72

T36

20

auto[1]

1738

1

T19

25

T35

40

T36

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	118	1			T19	1		T35	4		T37	2
all_values[0]	auto[0]	auto[0]	auto[1]	56	1			T19	1		T35	1		T37	2
all_values[0]	auto[0]	auto[1]	auto[0]	60	1			T19	1		T35	1		T36	2
all_values[0]	auto[0]	auto[1]	auto[1]	53	1			T19	2		T35	2		T358	1
all_values[0]	auto[1]	auto[0]	auto[1]	100	1			T19	2		T37	1		T359	5
all_values[0]	auto[1]	auto[1]	auto[1]	123	1			T35	6		T36	2		T37	3
all_values[1]	auto[0]	auto[0]	auto[0]	123	1			T19	2		T35	4		T36	2
all_values[1]	auto[0]	auto[0]	auto[1]	42	1			T19	1		T37	2		T359	4
all_values[1]	auto[0]	auto[1]	auto[0]	98	1			T35	2		T36	2		T37	1
all_values[1]	auto[0]	auto[1]	auto[1]	44	1			T35	3		T359	3		T164	1
all_values[1]	auto[1]	auto[0]	auto[1]	112	1			T19	3		T35	2		T37	3
all_values[1]	auto[1]	auto[1]	auto[1]	91	1			T19	1		T35	3		T37	2
all_values[2]	auto[0]	auto[0]	auto[0]	118	1			T19	1		T35	8		T36	2
all_values[2]	auto[0]	auto[0]	auto[1]	58	1			T35	1		T37	1		T359	1
all_values[2]	auto[0]	auto[1]	auto[0]	78	1			T35	1		T37	1		T359	4
all_values[2]	auto[0]	auto[1]	auto[1]	37	1			T19	2		T359	1		T164	1
all_values[2]	auto[1]	auto[0]	auto[1]	128	1			T19	1		T35	3		T36	1
all_values[2]	auto[1]	auto[1]	auto[1]	91	1			T19	3		T35	1		T36	1
all_values[3]	auto[0]	auto[0]	auto[0]	105	1			T35	2		T36	1		T37	2
all_values[3]	auto[0]	auto[0]	auto[1]	53	1			T19	1		T35	6		T358	1
all_values[3]	auto[0]	auto[1]	auto[0]	90	1			T35	1		T36	1		T37	7
all_values[3]	auto[0]	auto[1]	auto[1]	59	1			T19	2		T359	1		T163	2
all_values[3]	auto[1]	auto[0]	auto[1]	99	1			T19	1		T35	3		T36	1
all_values[3]	auto[1]	auto[1]	auto[1]	104	1			T19	3		T35	2		T36	1
all_values[4]	auto[0]	auto[0]	auto[0]	97	1			T35	3		T36	1		T37	1
all_values[4]	auto[0]	auto[0]	auto[1]	54	1			T19	2		T35	4		T36	1
all_values[4]	auto[0]	auto[1]	auto[0]	72	1			T19	2		T35	1		T359	1
all_values[4]	auto[0]	auto[1]	auto[1]	50	1			T35	1		T37	2		T359	1
all_values[4]	auto[1]	auto[0]	auto[1]	122	1			T19	2		T35	3		T37	5
all_values[4]	auto[1]	auto[1]	auto[1]	115	1			T19	1		T35	2		T36	2
all_values[5]	auto[0]	auto[0]	auto[0]	160	1			T19	1		T35	5		T36	1
all_values[5]	auto[0]	auto[1]	auto[0]	119	1			T19	5		T35	4		T36	1
all_values[5]	auto[1]	auto[0]	auto[1]	130	1			T19	1		T35	1		T37	2
all_values[5]	auto[1]	auto[1]	auto[1]	101	1			T35	4		T36	2		T37	2
all_values[6]	auto[0]	auto[0]	auto[0]	122	1			T19	1		T35	4		T36	2
all_values[6]	auto[0]	auto[0]	auto[1]	44	1			T19	1		T35	1		T359	1
all_values[6]	auto[0]	auto[1]	auto[0]	92	1			T19	3		T35	1		T36	2
all_values[6]	auto[0]	auto[1]	auto[1]	43	1			T35	3		T37	1		T164	1
all_values[6]	auto[1]	auto[0]	auto[1]	127	1			T19	1		T35	3		T37	1
all_values[6]	auto[1]	auto[1]	auto[1]	82	1			T19	1		T35	2		T37	2
all_values[7]	auto[0]	auto[0]	auto[0]	111	1			T35	3		T36	1		T37	3
all_values[7]	auto[0]	auto[0]	auto[1]	52	1			T36	1		T37	1		T359	3
all_values[7]	auto[0]	auto[1]	auto[0]	98	1			T19	1		T35	3		T37	1
all_values[7]	auto[0]	auto[1]	auto[1]	36	1			T19	1		T35	3		T358	1
all_values[7]	auto[1]	auto[0]	auto[1]	117	1			T19	3		T35	1		T36	2
all_values[7]	auto[1]	auto[1]	auto[1]	96	1			T19	2		T35	4		T37	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal