Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.13	97.55	92.89	98.61	80.85	95.99	90.94	88.08

Total test records in report: 846

T763	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1219429216	Apr 30 03:01:35 PM PDT 24	Apr 30 03:02:01 PM PDT 24	7236328309 ps
T764	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1434256156	Apr 30 03:02:11 PM PDT 24	Apr 30 03:02:14 PM PDT 24	14366550 ps
T765	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.647937698	Apr 30 03:02:01 PM PDT 24	Apr 30 03:02:02 PM PDT 24	16254702 ps
T766	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.621994055	Apr 30 03:01:57 PM PDT 24	Apr 30 03:02:01 PM PDT 24	92489315 ps
T767	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.2865406178	Apr 30 03:02:07 PM PDT 24	Apr 30 03:02:09 PM PDT 24	12490620 ps
T139	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3032453833	Apr 30 03:01:49 PM PDT 24	Apr 30 03:01:52 PM PDT 24	307296102 ps
T768	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.2371105004	Apr 30 03:02:09 PM PDT 24	Apr 30 03:02:11 PM PDT 24	62194535 ps
T98	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.332889677	Apr 30 03:01:56 PM PDT 24	Apr 30 03:01:58 PM PDT 24	19539792 ps
T769	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2735667995	Apr 30 03:01:41 PM PDT 24	Apr 30 03:01:43 PM PDT 24	27561241 ps
T770	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.3241253380	Apr 30 03:02:04 PM PDT 24	Apr 30 03:02:06 PM PDT 24	27467161 ps
T771	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4067402698	Apr 30 03:01:36 PM PDT 24	Apr 30 03:01:37 PM PDT 24	33206074 ps
T153	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3303749835	Apr 30 03:02:00 PM PDT 24	Apr 30 03:02:03 PM PDT 24	158636383 ps
T772	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2299782251	Apr 30 03:02:01 PM PDT 24	Apr 30 03:02:05 PM PDT 24	1183442669 ps
T773	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.342218476	Apr 30 03:01:59 PM PDT 24	Apr 30 03:02:02 PM PDT 24	73138548 ps
T774	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1700333748	Apr 30 03:01:45 PM PDT 24	Apr 30 03:01:47 PM PDT 24	78616384 ps
T377	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2339907515	Apr 30 03:01:59 PM PDT 24	Apr 30 03:02:06 PM PDT 24	119071684 ps
T775	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.494189490	Apr 30 03:02:03 PM PDT 24	Apr 30 03:02:08 PM PDT 24	113840000 ps
T776	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3011579373	Apr 30 03:01:54 PM PDT 24	Apr 30 03:01:56 PM PDT 24	62728739 ps
T777	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3914371548	Apr 30 03:01:46 PM PDT 24	Apr 30 03:02:25 PM PDT 24	7538287489 ps
T137	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2433699095	Apr 30 03:02:00 PM PDT 24	Apr 30 03:02:03 PM PDT 24	39499502 ps
T778	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.218271850	Apr 30 03:02:05 PM PDT 24	Apr 30 03:02:07 PM PDT 24	44430440 ps
T779	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.796206707	Apr 30 03:01:43 PM PDT 24	Apr 30 03:02:22 PM PDT 24	7577918933 ps
T780	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3133012297	Apr 30 03:02:03 PM PDT 24	Apr 30 03:02:06 PM PDT 24	44074734 ps
T781	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2030408862	Apr 30 03:01:41 PM PDT 24	Apr 30 03:01:44 PM PDT 24	71735221 ps
T782	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.4286482337	Apr 30 03:02:09 PM PDT 24	Apr 30 03:02:10 PM PDT 24	14119740 ps
T378	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3855578047	Apr 30 03:01:57 PM PDT 24	Apr 30 03:02:04 PM PDT 24	109998141 ps
T783	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.4213305180	Apr 30 03:02:11 PM PDT 24	Apr 30 03:02:13 PM PDT 24	14636074 ps
T784	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3400409540	Apr 30 03:01:52 PM PDT 24	Apr 30 03:02:01 PM PDT 24	119004104 ps
T380	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.838662123	Apr 30 03:01:56 PM PDT 24	Apr 30 03:02:04 PM PDT 24	106126636 ps
T785	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.897861272	Apr 30 03:02:11 PM PDT 24	Apr 30 03:02:14 PM PDT 24	14858782 ps
T138	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1585243271	Apr 30 03:02:07 PM PDT 24	Apr 30 03:02:12 PM PDT 24	60741562 ps
T786	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.780513779	Apr 30 03:01:55 PM PDT 24	Apr 30 03:01:58 PM PDT 24	140886692 ps
T787	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.127962514	Apr 30 03:02:00 PM PDT 24	Apr 30 03:02:04 PM PDT 24	1044184169 ps
T788	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.3808938670	Apr 30 03:01:59 PM PDT 24	Apr 30 03:02:01 PM PDT 24	25537136 ps
T789	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3315265835	Apr 30 03:01:52 PM PDT 24	Apr 30 03:02:16 PM PDT 24	353313795 ps
T381	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.920342617	Apr 30 03:01:35 PM PDT 24	Apr 30 03:01:55 PM PDT 24	291737971 ps
T790	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2574525893	Apr 30 03:02:02 PM PDT 24	Apr 30 03:02:05 PM PDT 24	111387787 ps
T791	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.2683516320	Apr 30 03:01:54 PM PDT 24	Apr 30 03:01:55 PM PDT 24	14356974 ps
T792	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.296894898	Apr 30 03:02:06 PM PDT 24	Apr 30 03:02:11 PM PDT 24	249168703 ps
T793	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1845336022	Apr 30 03:02:11 PM PDT 24	Apr 30 03:02:16 PM PDT 24	299924810 ps
T136	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1306183604	Apr 30 03:01:57 PM PDT 24	Apr 30 03:02:02 PM PDT 24	252563573 ps
T794	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.4107740485	Apr 30 03:02:08 PM PDT 24	Apr 30 03:02:10 PM PDT 24	13241106 ps
T795	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4204683218	Apr 30 03:02:02 PM PDT 24	Apr 30 03:02:07 PM PDT 24	134915693 ps
T796	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.1322077814	Apr 30 03:02:03 PM PDT 24	Apr 30 03:02:05 PM PDT 24	13911689 ps
T99	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3786379165	Apr 30 03:01:33 PM PDT 24	Apr 30 03:01:35 PM PDT 24	32208829 ps
T797	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.608447251	Apr 30 03:02:08 PM PDT 24	Apr 30 03:02:21 PM PDT 24	207374151 ps
T798	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.922115774	Apr 30 03:01:43 PM PDT 24	Apr 30 03:01:45 PM PDT 24	28008081 ps
T799	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3828575810	Apr 30 03:01:35 PM PDT 24	Apr 30 03:01:45 PM PDT 24	781819655 ps
T800	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2185864248	Apr 30 03:01:46 PM PDT 24	Apr 30 03:01:51 PM PDT 24	58040435 ps
T801	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.10122103	Apr 30 03:02:08 PM PDT 24	Apr 30 03:02:29 PM PDT 24	306398694 ps
T802	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2317726888	Apr 30 03:01:59 PM PDT 24	Apr 30 03:02:05 PM PDT 24	208985324 ps
T803	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.2425077397	Apr 30 03:02:12 PM PDT 24	Apr 30 03:02:14 PM PDT 24	45381017 ps
T804	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2448169415	Apr 30 03:02:01 PM PDT 24	Apr 30 03:02:02 PM PDT 24	28240120 ps
T805	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3662230191	Apr 30 03:01:46 PM PDT 24	Apr 30 03:01:48 PM PDT 24	32083876 ps
T806	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1496740838	Apr 30 03:02:03 PM PDT 24	Apr 30 03:02:05 PM PDT 24	70127469 ps
T807	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.4070320355	Apr 30 03:02:06 PM PDT 24	Apr 30 03:02:08 PM PDT 24	44715977 ps
T808	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3633299798	Apr 30 03:02:02 PM PDT 24	Apr 30 03:02:18 PM PDT 24	2009288717 ps
T809	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3747387324	Apr 30 03:02:04 PM PDT 24	Apr 30 03:02:07 PM PDT 24	19746084 ps
T810	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1952295587	Apr 30 03:01:36 PM PDT 24	Apr 30 03:01:41 PM PDT 24	467275725 ps
T811	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.910929487	Apr 30 03:01:44 PM PDT 24	Apr 30 03:01:48 PM PDT 24	56828564 ps
T812	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1014335425	Apr 30 03:02:06 PM PDT 24	Apr 30 03:02:10 PM PDT 24	126185360 ps
T813	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1181476411	Apr 30 03:01:42 PM PDT 24	Apr 30 03:01:45 PM PDT 24	47449523 ps
T814	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3397557467	Apr 30 03:01:58 PM PDT 24	Apr 30 03:02:02 PM PDT 24	1210908029 ps
T815	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2397390892	Apr 30 03:02:10 PM PDT 24	Apr 30 03:02:15 PM PDT 24	1898801204 ps
T816	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.2774979372	Apr 30 03:02:01 PM PDT 24	Apr 30 03:02:02 PM PDT 24	22288221 ps
T817	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.3103155453	Apr 30 03:02:05 PM PDT 24	Apr 30 03:02:07 PM PDT 24	15312207 ps
T818	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1989980521	Apr 30 03:02:03 PM PDT 24	Apr 30 03:02:05 PM PDT 24	34112868 ps
T819	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1222368885	Apr 30 03:01:37 PM PDT 24	Apr 30 03:01:41 PM PDT 24	152538421 ps
T820	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3239228255	Apr 30 03:01:48 PM PDT 24	Apr 30 03:01:51 PM PDT 24	2171418681 ps
T821	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4051479210	Apr 30 03:01:52 PM PDT 24	Apr 30 03:01:54 PM PDT 24	109136087 ps
T822	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4039409254	Apr 30 03:01:58 PM PDT 24	Apr 30 03:02:02 PM PDT 24	684342195 ps
T823	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.260700023	Apr 30 03:01:59 PM PDT 24	Apr 30 03:02:02 PM PDT 24	243503290 ps
T824	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1204080225	Apr 30 03:02:03 PM PDT 24	Apr 30 03:02:05 PM PDT 24	110897400 ps
T825	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.846567285	Apr 30 03:02:06 PM PDT 24	Apr 30 03:02:09 PM PDT 24	737427032 ps
T826	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3857316395	Apr 30 03:02:02 PM PDT 24	Apr 30 03:02:22 PM PDT 24	328904088 ps
T827	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1961104330	Apr 30 03:01:50 PM PDT 24	Apr 30 03:02:06 PM PDT 24	1425248300 ps
T828	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3280379819	Apr 30 03:01:44 PM PDT 24	Apr 30 03:01:48 PM PDT 24	115388073 ps
T829	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2602189855	Apr 30 03:01:57 PM PDT 24	Apr 30 03:02:01 PM PDT 24	139703371 ps
T830	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3181078909	Apr 30 03:01:59 PM PDT 24	Apr 30 03:02:02 PM PDT 24	196044221 ps
T831	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3580104116	Apr 30 03:02:01 PM PDT 24	Apr 30 03:02:05 PM PDT 24	261968603 ps
T832	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.3584616486	Apr 30 03:02:04 PM PDT 24	Apr 30 03:02:06 PM PDT 24	12519651 ps
T833	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2121643301	Apr 30 03:01:45 PM PDT 24	Apr 30 03:01:46 PM PDT 24	15285777 ps
T834	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1210520352	Apr 30 03:02:07 PM PDT 24	Apr 30 03:02:09 PM PDT 24	27729677 ps
T835	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.1989462812	Apr 30 03:02:08 PM PDT 24	Apr 30 03:02:10 PM PDT 24	45136551 ps
T836	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2342881936	Apr 30 03:02:03 PM PDT 24	Apr 30 03:02:05 PM PDT 24	17147514 ps
T837	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2296567759	Apr 30 03:02:02 PM PDT 24	Apr 30 03:02:15 PM PDT 24	1214204349 ps
T838	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2676602263	Apr 30 03:02:02 PM PDT 24	Apr 30 03:02:04 PM PDT 24	103955981 ps
T839	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2309721437	Apr 30 03:01:59 PM PDT 24	Apr 30 03:02:04 PM PDT 24	300503760 ps
T840	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.1182397615	Apr 30 03:01:59 PM PDT 24	Apr 30 03:02:00 PM PDT 24	44034451 ps
T841	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.605728057	Apr 30 03:01:36 PM PDT 24	Apr 30 03:01:38 PM PDT 24	215298596 ps
T842	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2083529678	Apr 30 03:02:06 PM PDT 24	Apr 30 03:02:09 PM PDT 24	170557026 ps
T843	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3206930743	Apr 30 03:01:55 PM PDT 24	Apr 30 03:01:57 PM PDT 24	26458314 ps
T844	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.3275228333	Apr 30 03:02:06 PM PDT 24	Apr 30 03:02:08 PM PDT 24	49462870 ps
T100	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2250433257	Apr 30 03:01:36 PM PDT 24	Apr 30 03:01:38 PM PDT 24	76578195 ps
T845	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3768790089	Apr 30 03:01:40 PM PDT 24	Apr 30 03:01:55 PM PDT 24	550469088 ps
T846	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.600028945	Apr 30 03:02:09 PM PDT 24	Apr 30 03:02:11 PM PDT 24	31653805 ps

Test location	/workspace/coverage/default/48.spi_device_pass_cmd_filtering.1875822812
Short name	T4
Test name
Test status
Simulation time	3029472367 ps
CPU time	6.73 seconds
Started	Apr 30 03:22:50 PM PDT 24
Finished	Apr 30 03:22:57 PM PDT 24
Peak memory	233712 kb
Host	smart-ea35e240-b886-47dc-a3c5-8ab1102c6ee9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1875822812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1875822812
Directory	/workspace/48.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3293564951
Short name	T6
Test name
Test status
Simulation time	2609062874 ps
CPU time	35.83 seconds
Started	Apr 30 03:20:26 PM PDT 24
Finished	Apr 30 03:21:04 PM PDT 24
Peak memory	222964 kb
Host	smart-c644b7c6-e43d-4dae-a82d-3155350caa78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293564951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl e.3293564951
Directory	/workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_all.3543784832
Short name	T3
Test name
Test status
Simulation time	5654603204 ps
CPU time	26.1 seconds
Started	Apr 30 03:21:05 PM PDT 24
Finished	Apr 30 03:21:32 PM PDT 24
Peak memory	216324 kb
Host	smart-9016d789-2c98-4d66-8aa7-2e46fd709347
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3543784832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3543784832
Directory	/workspace/25.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/48.spi_device_flash_and_tpm.1585528017
Short name	T26
Test name
Test status
Simulation time	67964104375 ps
CPU time	44.53 seconds
Started	Apr 30 03:22:37 PM PDT 24
Finished	Apr 30 03:23:22 PM PDT 24
Peak memory	223636 kb
Host	smart-7d405cc3-fa9b-42d3-93e3-c33a51048dfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585528017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1585528017
Directory	/workspace/48.spi_device_flash_and_tpm/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2274268621
Short name	T115
Test name
Test status
Simulation time	4334721557 ps
CPU time	21.79 seconds
Started	Apr 30 03:02:01 PM PDT 24
Finished	Apr 30 03:02:23 PM PDT 24
Peak memory	215228 kb
Host	smart-ffccc78d-af5f-4ebb-8e98-f858be28b4a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274268621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic e_tl_intg_err.2274268621
Directory	/workspace/11.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/33.spi_device_stress_all.3320105350
Short name	T359
Test name
Test status
Simulation time	37459359 ps
CPU time	0.99 seconds
Started	Apr 30 03:21:35 PM PDT 24
Finished	Apr 30 03:21:37 PM PDT 24
Peak memory	206824 kb
Host	smart-5d34a13c-a751-41bb-bddc-cff50333498a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320105350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre ss_all.3320105350
Directory	/workspace/33.spi_device_stress_all/latest

Test location	/workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3131478139
Short name	T64
Test name
Test status
Simulation time	3069541464 ps
CPU time	8.83 seconds
Started	Apr 30 03:21:09 PM PDT 24
Finished	Apr 30 03:21:19 PM PDT 24
Peak memory	224332 kb
Host	smart-a59d0b07-fbd1-48d2-a813-6cb2671b8279
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131478139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa p.3131478139
Directory	/workspace/24.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/1.spi_device_intercept.3539489978
Short name	T12
Test name
Test status
Simulation time	2704683176 ps
CPU time	14.9 seconds
Started	Apr 30 03:19:41 PM PDT 24
Finished	Apr 30 03:19:57 PM PDT 24
Peak memory	223852 kb
Host	smart-76aba9e8-22a6-48cf-be33-40f5f1e35155
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539489978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3539489978
Directory	/workspace/1.spi_device_intercept/latest

Test location	/workspace/coverage/default/0.spi_device_ram_cfg.2657057183
Short name	T44
Test name
Test status
Simulation time	17122154 ps
CPU time	0.74 seconds
Started	Apr 30 03:19:40 PM PDT 24
Finished	Apr 30 03:19:41 PM PDT 24
Peak memory	216124 kb
Host	smart-a498c894-1804-478e-9261-64edd78db41a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657057183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2657057183
Directory	/workspace/0.spi_device_ram_cfg/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_all.3860997863
Short name	T106
Test name
Test status
Simulation time	3568521286 ps
CPU time	31.79 seconds
Started	Apr 30 03:20:50 PM PDT 24
Finished	Apr 30 03:21:23 PM PDT 24
Peak memory	221052 kb
Host	smart-6507fba5-0dd3-46cc-b1e6-0bea6a90772d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3860997863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3860997863
Directory	/workspace/19.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/16.spi_device_upload.3912699249
Short name	T10
Test name
Test status
Simulation time	4938591912 ps
CPU time	20.24 seconds
Started	Apr 30 03:20:29 PM PDT 24
Finished	Apr 30 03:20:50 PM PDT 24
Peak memory	234960 kb
Host	smart-04070177-d7f0-4ff0-ba26-2f99640defb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912699249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3912699249
Directory	/workspace/16.spi_device_upload/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2151968688
Short name	T17
Test name
Test status
Simulation time	12909534256 ps
CPU time	13.73 seconds
Started	Apr 30 03:21:16 PM PDT 24
Finished	Apr 30 03:21:31 PM PDT 24
Peak memory	216296 kb
Host	smart-c5fb268d-ddd5-4116-8be5-e6c0c1207849
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2151968688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2151968688
Directory	/workspace/28.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3088414642
Short name	T117
Test name
Test status
Simulation time	220388381 ps
CPU time	4.99 seconds
Started	Apr 30 03:01:56 PM PDT 24
Finished	Apr 30 03:02:01 PM PDT 24
Peak memory	215264 kb
Host	smart-0cdd8014-9a09-47f9-947a-4730b3115ea4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088414642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3 088414642
Directory	/workspace/7.spi_device_tl_errors/latest

Test location	/workspace/coverage/default/5.spi_device_flash_mode.502653348
Short name	T5
Test name
Test status
Simulation time	1985885101 ps
CPU time	32.51 seconds
Started	Apr 30 03:20:00 PM PDT 24
Finished	Apr 30 03:20:33 PM PDT 24
Peak memory	249052 kb
Host	smart-073b2fa5-ea91-4b53-ac9d-975038b0198e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502653348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.502653348
Directory	/workspace/5.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_all.3652713394
Short name	T395
Test name
Test status
Simulation time	2777035046 ps
CPU time	23.66 seconds
Started	Apr 30 03:21:07 PM PDT 24
Finished	Apr 30 03:21:32 PM PDT 24
Peak memory	220356 kb
Host	smart-a1cf25ac-91af-4881-bfd4-fd1a45b73c08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652713394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3652713394
Directory	/workspace/26.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/16.spi_device_alert_test.2236256230
Short name	T448
Test name
Test status
Simulation time	11566861 ps
CPU time	0.72 seconds
Started	Apr 30 03:20:36 PM PDT 24
Finished	Apr 30 03:20:37 PM PDT 24
Peak memory	205332 kb
Host	smart-2b90c832-af3d-40cb-87f4-5bd7cc7e10bf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236256230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test. 2236256230
Directory	/workspace/16.spi_device_alert_test/latest

Test location	/workspace/coverage/default/23.spi_device_pass_cmd_filtering.361719904
Short name	T61
Test name
Test status
Simulation time	19115574065 ps
CPU time	50.6 seconds
Started	Apr 30 03:21:01 PM PDT 24
Finished	Apr 30 03:21:53 PM PDT 24
Peak memory	234844 kb
Host	smart-8937ef1d-8b0b-422a-9f45-64d2fab00363
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361719904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.361719904
Directory	/workspace/23.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/27.spi_device_intercept.581492279
Short name	T285
Test name
Test status
Simulation time	21817299765 ps
CPU time	47.09 seconds
Started	Apr 30 03:21:16 PM PDT 24
Finished	Apr 30 03:22:04 PM PDT 24
Peak memory	218824 kb
Host	smart-133bd7c6-be7f-4d3c-aa9b-1aaf27f8e867
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581492279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.581492279
Directory	/workspace/27.spi_device_intercept/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.51132074
Short name	T43
Test name
Test status
Simulation time	39327641 ps
CPU time	2.63 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	215112 kb
Host	smart-3b2db03f-8b30-4594-b342-f2fb5550100d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51132074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.51132074
Directory	/workspace/13.spi_device_csr_rw/latest

Test location	/workspace/coverage/default/8.spi_device_pass_cmd_filtering.4056129106
Short name	T238
Test name
Test status
Simulation time	18957156989 ps
CPU time	45.66 seconds
Started	Apr 30 03:20:14 PM PDT 24
Finished	Apr 30 03:21:00 PM PDT 24
Peak memory	226808 kb
Host	smart-f2eeabf9-048d-4ff5-b9c4-439a2274c088
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056129106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4056129106
Directory	/workspace/8.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/0.spi_device_mailbox.1218754103
Short name	T320
Test name
Test status
Simulation time	6726545160 ps
CPU time	60.55 seconds
Started	Apr 30 03:19:42 PM PDT 24
Finished	Apr 30 03:20:44 PM PDT 24
Peak memory	223392 kb
Host	smart-33ffc1c6-1c87-4eaf-b125-7f5ea1aeda8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218754103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1218754103
Directory	/workspace/0.spi_device_mailbox/latest

Test location	/workspace/coverage/default/28.spi_device_pass_cmd_filtering.1031425277
Short name	T222
Test name
Test status
Simulation time	42440984285 ps
CPU time	24.92 seconds
Started	Apr 30 03:21:16 PM PDT 24
Finished	Apr 30 03:21:42 PM PDT 24
Peak memory	222416 kb
Host	smart-e26c4ed9-fcd5-40eb-9353-0501492f42ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031425277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1031425277
Directory	/workspace/28.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/4.spi_device_upload.1771039177
Short name	T210
Test name
Test status
Simulation time	9791972413 ps
CPU time	17.63 seconds
Started	Apr 30 03:19:53 PM PDT 24
Finished	Apr 30 03:20:12 PM PDT 24
Peak memory	222440 kb
Host	smart-e5e31ccb-de26-4286-9999-9a9ba4d43267
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771039177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1771039177
Directory	/workspace/4.spi_device_upload/latest

Test location	/workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4161739230
Short name	T62
Test name
Test status
Simulation time	1561520188 ps
CPU time	7.06 seconds
Started	Apr 30 03:19:44 PM PDT 24
Finished	Apr 30 03:19:52 PM PDT 24
Peak memory	237968 kb
Host	smart-2921a4ca-46d1-4d49-a006-7a3de906d2ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161739230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap .4161739230
Directory	/workspace/2.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/12.spi_device_upload.3746113117
Short name	T233
Test name
Test status
Simulation time	21114766613 ps
CPU time	20.69 seconds
Started	Apr 30 03:20:25 PM PDT 24
Finished	Apr 30 03:20:47 PM PDT 24
Peak memory	223992 kb
Host	smart-5da1df67-757c-4941-acda-64a4c0a22b30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746113117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3746113117
Directory	/workspace/12.spi_device_upload/latest

Test location	/workspace/coverage/default/39.spi_device_mailbox.1330417183
Short name	T284
Test name
Test status
Simulation time	6171615850 ps
CPU time	19.13 seconds
Started	Apr 30 03:22:02 PM PDT 24
Finished	Apr 30 03:22:23 PM PDT 24
Peak memory	237124 kb
Host	smart-d3433296-6f71-4907-ac30-ae8e52432d65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330417183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1330417183
Directory	/workspace/39.spi_device_mailbox/latest

Test location	/workspace/coverage/default/47.spi_device_pass_cmd_filtering.2646906634
Short name	T287
Test name
Test status
Simulation time	11410374277 ps
CPU time	32.35 seconds
Started	Apr 30 03:22:32 PM PDT 24
Finished	Apr 30 03:23:05 PM PDT 24
Peak memory	223948 kb
Host	smart-238e644e-d7df-4ae7-b530-cc5140860901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2646906634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2646906634
Directory	/workspace/47.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_all.2931011822
Short name	T404
Test name
Test status
Simulation time	15370396590 ps
CPU time	52.04 seconds
Started	Apr 30 03:21:05 PM PDT 24
Finished	Apr 30 03:21:58 PM PDT 24
Peak memory	216244 kb
Host	smart-1e2bed99-6c10-4481-8780-b5691920b455
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2931011822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2931011822
Directory	/workspace/24.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/40.spi_device_intercept.2848018379
Short name	T196
Test name
Test status
Simulation time	3880752211 ps
CPU time	32.63 seconds
Started	Apr 30 03:22:02 PM PDT 24
Finished	Apr 30 03:22:35 PM PDT 24
Peak memory	222552 kb
Host	smart-65024206-85e4-4540-9d42-5bca2813b82d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2848018379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2848018379
Directory	/workspace/40.spi_device_intercept/latest

Test location	/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.78625310
Short name	T330
Test name
Test status
Simulation time	12468708139 ps
CPU time	11.92 seconds
Started	Apr 30 03:22:35 PM PDT 24
Finished	Apr 30 03:22:47 PM PDT 24
Peak memory	219348 kb
Host	smart-327cf68f-718f-4984-b052-6bdf937b0783
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78625310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.78625310
Directory	/workspace/49.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/11.spi_device_pass_addr_payload_swap.213109611
Short name	T327
Test name
Test status
Simulation time	871133986 ps
CPU time	6.98 seconds
Started	Apr 30 03:20:19 PM PDT 24
Finished	Apr 30 03:20:27 PM PDT 24
Peak memory	232064 kb
Host	smart-c2e67645-b630-4d86-af16-c72c859faee2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213109611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap .213109611
Directory	/workspace/11.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.772917719
Short name	T74
Test name
Test status
Simulation time	160243032922 ps
CPU time	24.26 seconds
Started	Apr 30 03:22:11 PM PDT 24
Finished	Apr 30 03:22:35 PM PDT 24
Peak memory	236856 kb
Host	smart-21c2428d-02a1-4963-a453-053334b406e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772917719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap .772917719
Directory	/workspace/43.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/25.spi_device_intercept.2976040567
Short name	T45
Test name
Test status
Simulation time	129781868 ps
CPU time	3.89 seconds
Started	Apr 30 03:21:10 PM PDT 24
Finished	Apr 30 03:21:14 PM PDT 24
Peak memory	219792 kb
Host	smart-bb0669a3-45d0-49c0-9dd7-baeb796ca723
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976040567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2976040567
Directory	/workspace/25.spi_device_intercept/latest

Test location	/workspace/coverage/default/13.spi_device_intercept.3021100968
Short name	T360
Test name
Test status
Simulation time	684454535 ps
CPU time	11.26 seconds
Started	Apr 30 03:20:26 PM PDT 24
Finished	Apr 30 03:20:39 PM PDT 24
Peak memory	232360 kb
Host	smart-885bb113-2be0-419f-98cd-9eda4e68b0eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021100968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3021100968
Directory	/workspace/13.spi_device_intercept/latest

Test location	/workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1005009893
Short name	T289
Test name
Test status
Simulation time	11015944951 ps
CPU time	13.05 seconds
Started	Apr 30 03:22:34 PM PDT 24
Finished	Apr 30 03:22:48 PM PDT 24
Peak memory	218204 kb
Host	smart-70c99039-cdd2-487b-800f-e87895fe6039
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005009893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa p.1005009893
Directory	/workspace/48.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/0.spi_device_sec_cm.2029552839
Short name	T49
Test name
Test status
Simulation time	39959424 ps
CPU time	0.96 seconds
Started	Apr 30 03:19:43 PM PDT 24
Finished	Apr 30 03:19:45 PM PDT 24
Peak memory	234964 kb
Host	smart-562b7e27-9f11-456e-a46a-4008c45aaa9b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029552839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2029552839
Directory	/workspace/0.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/5.spi_device_upload.3008743395
Short name	T224
Test name
Test status
Simulation time	12776466325 ps
CPU time	21.29 seconds
Started	Apr 30 03:20:06 PM PDT 24
Finished	Apr 30 03:20:28 PM PDT 24
Peak memory	240168 kb
Host	smart-f797a785-759f-4757-904a-a8f53842ad1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008743395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3008743395
Directory	/workspace/5.spi_device_upload/latest

Test location	/workspace/coverage/default/8.spi_device_mailbox.3691943989
Short name	T180
Test name
Test status
Simulation time	4019113434 ps
CPU time	21.62 seconds
Started	Apr 30 03:20:10 PM PDT 24
Finished	Apr 30 03:20:32 PM PDT 24
Peak memory	234740 kb
Host	smart-e8f9473e-9fd4-42e3-88ef-7d9f228d43c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691943989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3691943989
Directory	/workspace/8.spi_device_mailbox/latest

Test location	/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3064868075
Short name	T334
Test name
Test status
Simulation time	5154209092 ps
CPU time	10.49 seconds
Started	Apr 30 03:20:14 PM PDT 24
Finished	Apr 30 03:20:26 PM PDT 24
Peak memory	232756 kb
Host	smart-a478ccd8-6a21-47ec-a48a-e0ca09f89efb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064868075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap .3064868075
Directory	/workspace/9.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/19.spi_device_mailbox.3022930163
Short name	T355
Test name
Test status
Simulation time	8361867012 ps
CPU time	90.46 seconds
Started	Apr 30 03:20:44 PM PDT 24
Finished	Apr 30 03:22:16 PM PDT 24
Peak memory	231836 kb
Host	smart-a98f6bec-baa1-45ab-b564-95c4a5b252f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022930163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3022930163
Directory	/workspace/19.spi_device_mailbox/latest

Test location	/workspace/coverage/default/46.spi_device_upload.4026224595
Short name	T204
Test name
Test status
Simulation time	4516441435 ps
CPU time	14.33 seconds
Started	Apr 30 03:22:27 PM PDT 24
Finished	Apr 30 03:22:42 PM PDT 24
Peak memory	224588 kb
Host	smart-15d737dd-7134-48d6-ae13-d70bfb48ef24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026224595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4026224595
Directory	/workspace/46.spi_device_upload/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_all.1221594818
Short name	T389
Test name
Test status
Simulation time	30772232504 ps
CPU time	35.9 seconds
Started	Apr 30 03:20:14 PM PDT 24
Finished	Apr 30 03:20:50 PM PDT 24
Peak memory	216488 kb
Host	smart-5023a183-87bc-45c3-a884-91d1d8075619
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221594818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1221594818
Directory	/workspace/10.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/16.spi_device_flash_mode.965490782
Short name	T353
Test name
Test status
Simulation time	6221455294 ps
CPU time	24.36 seconds
Started	Apr 30 03:20:32 PM PDT 24
Finished	Apr 30 03:20:58 PM PDT 24
Peak memory	232740 kb
Host	smart-8f3f7f7c-09d2-4796-b713-28ab476766d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965490782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.965490782
Directory	/workspace/16.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.556554360
Short name	T66
Test name
Test status
Simulation time	21974770522 ps
CPU time	18.35 seconds
Started	Apr 30 03:21:24 PM PDT 24
Finished	Apr 30 03:21:44 PM PDT 24
Peak memory	218952 kb
Host	smart-2118417c-c61e-48d3-81ca-b9ceeb95108a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556554360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap .556554360
Directory	/workspace/30.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/6.spi_device_cfg_cmd.925609994
Short name	T31
Test name
Test status
Simulation time	1378571954 ps
CPU time	15.68 seconds
Started	Apr 30 03:20:02 PM PDT 24
Finished	Apr 30 03:20:19 PM PDT 24
Peak memory	218608 kb
Host	smart-48e8d99d-140f-4493-a8a5-5dcf00bab8cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925609994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.925609994
Directory	/workspace/6.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/2.spi_device_intercept.4147636596
Short name	T298
Test name
Test status
Simulation time	1914159484 ps
CPU time	18.72 seconds
Started	Apr 30 03:19:42 PM PDT 24
Finished	Apr 30 03:20:02 PM PDT 24
Peak memory	232404 kb
Host	smart-521169c5-7764-400d-9c9c-d8e49dd6ae7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147636596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4147636596
Directory	/workspace/2.spi_device_intercept/latest

Test location	/workspace/coverage/default/34.spi_device_mailbox.4117826318
Short name	T306
Test name
Test status
Simulation time	3587371256 ps
CPU time	13.92 seconds
Started	Apr 30 03:21:42 PM PDT 24
Finished	Apr 30 03:21:56 PM PDT 24
Peak memory	234308 kb
Host	smart-301f9376-798b-42bc-ac94-a847301838fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4117826318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4117826318
Directory	/workspace/34.spi_device_mailbox/latest

Test location	/workspace/coverage/default/41.spi_device_pass_addr_payload_swap.625856750
Short name	T272
Test name
Test status
Simulation time	1003096889 ps
CPU time	7.48 seconds
Started	Apr 30 03:22:11 PM PDT 24
Finished	Apr 30 03:22:19 PM PDT 24
Peak memory	236196 kb
Host	smart-89ae0195-90e2-4d6e-a633-420ff805e965
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625856750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap .625856750
Directory	/workspace/41.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/18.spi_device_stress_all.418606884
Short name	T19
Test name
Test status
Simulation time	45986084 ps
CPU time	1.07 seconds
Started	Apr 30 03:20:40 PM PDT 24
Finished	Apr 30 03:20:42 PM PDT 24
Peak memory	207364 kb
Host	smart-6fae9aa7-68dd-437b-95ed-57a07df58139
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418606884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres s_all.418606884
Directory	/workspace/18.spi_device_stress_all/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_all.50812008
Short name	T425
Test name
Test status
Simulation time	67926236242 ps
CPU time	83.21 seconds
Started	Apr 30 03:20:27 PM PDT 24
Finished	Apr 30 03:21:51 PM PDT 24
Peak memory	216396 kb
Host	smart-0b6a3310-9f79-405a-81a2-19ceccc08e15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50812008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.50812008
Directory	/workspace/14.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/15.spi_device_intercept.2064274919
Short name	T119
Test name
Test status
Simulation time	1022639416 ps
CPU time	11.5 seconds
Started	Apr 30 03:20:32 PM PDT 24
Finished	Apr 30 03:20:46 PM PDT 24
Peak memory	222440 kb
Host	smart-b06b6adc-e47d-4293-900b-85171699b7e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2064274919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2064274919
Directory	/workspace/15.spi_device_intercept/latest

Test location	/workspace/coverage/default/22.spi_device_pass_addr_payload_swap.637538610
Short name	T325
Test name
Test status
Simulation time	2444435079 ps
CPU time	5.29 seconds
Started	Apr 30 03:20:56 PM PDT 24
Finished	Apr 30 03:21:02 PM PDT 24
Peak memory	218604 kb
Host	smart-57f15901-1ea4-48b7-baa6-669ce3fb035e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637538610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap .637538610
Directory	/workspace/22.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3011454431
Short name	T292
Test name
Test status
Simulation time	26981919514 ps
CPU time	19.83 seconds
Started	Apr 30 03:20:57 PM PDT 24
Finished	Apr 30 03:21:18 PM PDT 24
Peak memory	234956 kb
Host	smart-92821778-01a2-40cc-bbca-011a71077663
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011454431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa p.3011454431
Directory	/workspace/23.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/26.spi_device_intercept.4199215642
Short name	T188
Test name
Test status
Simulation time	96345774 ps
CPU time	3.46 seconds
Started	Apr 30 03:21:04 PM PDT 24
Finished	Apr 30 03:21:08 PM PDT 24
Peak memory	224028 kb
Host	smart-8450e120-d77d-4319-9516-98321eb61831
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4199215642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4199215642
Directory	/workspace/26.spi_device_intercept/latest

Test location	/workspace/coverage/default/0.spi_device_flash_mode.3552641821
Short name	T346
Test name
Test status
Simulation time	3341161889 ps
CPU time	46.17 seconds
Started	Apr 30 03:19:41 PM PDT 24
Finished	Apr 30 03:20:28 PM PDT 24
Peak memory	237136 kb
Host	smart-09d1a330-7d18-4f14-9276-8c1a7f5fc4f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552641821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3552641821
Directory	/workspace/0.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/0.spi_device_intercept.1908229930
Short name	T202
Test name
Test status
Simulation time	4440013992 ps
CPU time	12.09 seconds
Started	Apr 30 03:19:39 PM PDT 24
Finished	Apr 30 03:19:52 PM PDT 24
Peak memory	219108 kb
Host	smart-bfda3682-a1a9-4e30-a3b6-73ef8cb8bdd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908229930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1908229930
Directory	/workspace/0.spi_device_intercept/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_all.1210332194
Short name	T102
Test name
Test status
Simulation time	1564506450 ps
CPU time	14.75 seconds
Started	Apr 30 03:19:41 PM PDT 24
Finished	Apr 30 03:19:57 PM PDT 24
Peak memory	216508 kb
Host	smart-1d7dea42-16d9-4b0b-9055-7815d5296de1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210332194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1210332194
Directory	/workspace/1.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/19.spi_device_pass_cmd_filtering.2796934277
Short name	T269
Test name
Test status
Simulation time	65557567122 ps
CPU time	46.6 seconds
Started	Apr 30 03:20:39 PM PDT 24
Finished	Apr 30 03:21:26 PM PDT 24
Peak memory	232612 kb
Host	smart-6207f851-6ba3-4be4-b078-ecf13c1db3fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796934277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2796934277
Directory	/workspace/19.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/40.spi_device_mailbox.3467695780
Short name	T200
Test name
Test status
Simulation time	10425612232 ps
CPU time	45.18 seconds
Started	Apr 30 03:22:03 PM PDT 24
Finished	Apr 30 03:22:49 PM PDT 24
Peak memory	249132 kb
Host	smart-727c6acb-d514-49d8-a444-45bfd336982d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467695780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3467695780
Directory	/workspace/40.spi_device_mailbox/latest

Test location	/workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3207989502
Short name	T232
Test name
Test status
Simulation time	774183150 ps
CPU time	7.45 seconds
Started	Apr 30 03:20:21 PM PDT 24
Finished	Apr 30 03:20:30 PM PDT 24
Peak memory	234144 kb
Host	smart-c1f7ed47-455a-48ca-8451-506887dc3cd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207989502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa p.3207989502
Directory	/workspace/12.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/14.spi_device_intercept.1028103921
Short name	T248
Test name
Test status
Simulation time	433713300 ps
CPU time	4.2 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:29 PM PDT 24
Peak memory	218792 kb
Host	smart-c7e36efc-3601-47a5-bf90-38517fa92901
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028103921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1028103921
Directory	/workspace/14.spi_device_intercept/latest

Test location	/workspace/coverage/default/21.spi_device_upload.3457226477
Short name	T323
Test name
Test status
Simulation time	7282904623 ps
CPU time	25.22 seconds
Started	Apr 30 03:20:50 PM PDT 24
Finished	Apr 30 03:21:16 PM PDT 24
Peak memory	232664 kb
Host	smart-252960ce-6fa6-49b9-bb5e-41a32ce78836
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457226477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3457226477
Directory	/workspace/21.spi_device_upload/latest

Test location	/workspace/coverage/default/24.spi_device_mailbox.4073184667
Short name	T303
Test name
Test status
Simulation time	56112383 ps
CPU time	2.47 seconds
Started	Apr 30 03:21:05 PM PDT 24
Finished	Apr 30 03:21:09 PM PDT 24
Peak memory	223208 kb
Host	smart-0c1e861e-4484-4f58-aa0f-64b0cb570cf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073184667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4073184667
Directory	/workspace/24.spi_device_mailbox/latest

Test location	/workspace/coverage/default/29.spi_device_flash_mode.3605941452
Short name	T341
Test name
Test status
Simulation time	9369351077 ps
CPU time	82.74 seconds
Started	Apr 30 03:21:21 PM PDT 24
Finished	Apr 30 03:22:44 PM PDT 24
Peak memory	249096 kb
Host	smart-c6900253-457c-4670-a539-da6ec2e571a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605941452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3605941452
Directory	/workspace/29.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/3.spi_device_intercept.1069027096
Short name	T230
Test name
Test status
Simulation time	2890013941 ps
CPU time	11.75 seconds
Started	Apr 30 03:19:50 PM PDT 24
Finished	Apr 30 03:20:02 PM PDT 24
Peak memory	223596 kb
Host	smart-8d9cd80e-5f9a-49c7-a794-def613c6746b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069027096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1069027096
Directory	/workspace/3.spi_device_intercept/latest

Test location	/workspace/coverage/default/3.spi_device_pass_addr_payload_swap.800116387
Short name	T71
Test name
Test status
Simulation time	14900509321 ps
CPU time	40.07 seconds
Started	Apr 30 03:19:58 PM PDT 24
Finished	Apr 30 03:20:39 PM PDT 24
Peak memory	234580 kb
Host	smart-13d0c238-a2a6-4aba-b0de-321ab5f494b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800116387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap. 800116387
Directory	/workspace/3.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1530180949
Short name	T69
Test name
Test status
Simulation time	14968352021 ps
CPU time	10.01 seconds
Started	Apr 30 03:21:43 PM PDT 24
Finished	Apr 30 03:21:54 PM PDT 24
Peak memory	230212 kb
Host	smart-a5213271-f013-459e-8969-dc6d83d8e710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530180949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa p.1530180949
Directory	/workspace/36.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2847363599
Short name	T70
Test name
Test status
Simulation time	3983909754 ps
CPU time	8.45 seconds
Started	Apr 30 03:21:51 PM PDT 24
Finished	Apr 30 03:22:00 PM PDT 24
Peak memory	216996 kb
Host	smart-a0b40d8c-6b7a-4de7-b28a-90050cfb71a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847363599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa p.2847363599
Directory	/workspace/38.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1087682329
Short name	T254
Test name
Test status
Simulation time	47123476071 ps
CPU time	27.05 seconds
Started	Apr 30 03:22:02 PM PDT 24
Finished	Apr 30 03:22:30 PM PDT 24
Peak memory	235484 kb
Host	smart-5265d822-0203-4b9d-8837-ceb2492c3f18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087682329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa p.1087682329
Directory	/workspace/40.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2583655509
Short name	T131
Test name
Test status
Simulation time	397717544 ps
CPU time	3.79 seconds
Started	Apr 30 03:01:56 PM PDT 24
Finished	Apr 30 03:02:01 PM PDT 24
Peak memory	215152 kb
Host	smart-9e28c721-46b5-4c4f-8744-ebad41771ab1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583655509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors. 2583655509
Directory	/workspace/18.spi_device_tl_errors/latest

Test location	/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.67241420
Short name	T67
Test name
Test status
Simulation time	8399166565 ps
CPU time	7.23 seconds
Started	Apr 30 03:20:34 PM PDT 24
Finished	Apr 30 03:20:43 PM PDT 24
Peak memory	218120 kb
Host	smart-7551ae9d-adc4-4aa1-8c30-b2e0977cf510
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67241420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.67241420
Directory	/workspace/15.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/48.spi_device_flash_mode.1785497617
Short name	T124
Test name
Test status
Simulation time	7264740486 ps
CPU time	98.49 seconds
Started	Apr 30 03:22:35 PM PDT 24
Finished	Apr 30 03:24:14 PM PDT 24
Peak memory	249076 kb
Host	smart-7bb65c00-38ae-4a6e-b3bf-bb90b04e781d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785497617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1785497617
Directory	/workspace/48.spi_device_flash_mode/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2764861499
Short name	T133
Test name
Test status
Simulation time	294614716 ps
CPU time	18.25 seconds
Started	Apr 30 03:02:00 PM PDT 24
Finished	Apr 30 03:02:19 PM PDT 24
Peak memory	215164 kb
Host	smart-7077ace4-5f27-45db-97ec-650b095ca7e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764861499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic e_tl_intg_err.2764861499
Directory	/workspace/14.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2328048291
Short name	T376
Test name
Test status
Simulation time	836129709 ps
CPU time	21.04 seconds
Started	Apr 30 03:01:50 PM PDT 24
Finished	Apr 30 03:02:12 PM PDT 24
Peak memory	215856 kb
Host	smart-397c3d5b-3cbf-4437-aa12-120ed782b6d4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328048291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device _tl_intg_err.2328048291
Directory	/workspace/2.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/0.spi_device_pass_cmd_filtering.2990621621
Short name	T250
Test name
Test status
Simulation time	186930980 ps
CPU time	3.78 seconds
Started	Apr 30 03:19:45 PM PDT 24
Finished	Apr 30 03:19:50 PM PDT 24
Peak memory	217820 kb
Host	smart-3fa9f9bd-5863-47e0-b926-71cb84658f5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990621621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2990621621
Directory	/workspace/0.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/13.spi_device_cfg_cmd.1200530479
Short name	T218
Test name
Test status
Simulation time	127207462 ps
CPU time	2.86 seconds
Started	Apr 30 03:20:18 PM PDT 24
Finished	Apr 30 03:20:21 PM PDT 24
Peak memory	232484 kb
Host	smart-25b76989-02b4-473f-b93c-e463b9621123
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200530479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1200530479
Directory	/workspace/13.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1129618333
Short name	T68
Test name
Test status
Simulation time	577596732 ps
CPU time	5.08 seconds
Started	Apr 30 03:20:27 PM PDT 24
Finished	Apr 30 03:20:34 PM PDT 24
Peak memory	223152 kb
Host	smart-283f4ac6-6818-4ecc-81ce-89315c5eee9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129618333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa p.1129618333
Directory	/workspace/14.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/14.spi_device_pass_cmd_filtering.1166468788
Short name	T220
Test name
Test status
Simulation time	15645114480 ps
CPU time	11.27 seconds
Started	Apr 30 03:20:24 PM PDT 24
Finished	Apr 30 03:20:37 PM PDT 24
Peak memory	221468 kb
Host	smart-59b04139-8210-4281-88e8-a34bc572e032
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166468788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1166468788
Directory	/workspace/14.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/15.spi_device_upload.2373738750
Short name	T236
Test name
Test status
Simulation time	7317568293 ps
CPU time	8.27 seconds
Started	Apr 30 03:20:29 PM PDT 24
Finished	Apr 30 03:20:38 PM PDT 24
Peak memory	222864 kb
Host	smart-1f7c20d4-320f-4242-9c40-5f98c7c8ee99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373738750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2373738750
Directory	/workspace/15.spi_device_upload/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_all.3800473447
Short name	T407
Test name
Test status
Simulation time	12212079139 ps
CPU time	61.67 seconds
Started	Apr 30 03:20:32 PM PDT 24
Finished	Apr 30 03:21:36 PM PDT 24
Peak memory	216324 kb
Host	smart-41756a5f-7436-4ea9-a669-cbe8aeb984c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3800473447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3800473447
Directory	/workspace/17.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/18.spi_device_pass_cmd_filtering.1467149514
Short name	T176
Test name
Test status
Simulation time	983563430 ps
CPU time	8.29 seconds
Started	Apr 30 03:20:45 PM PDT 24
Finished	Apr 30 03:20:54 PM PDT 24
Peak memory	233596 kb
Host	smart-d8f02ea6-2b1e-4999-8ad9-aff484e9dcfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467149514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1467149514
Directory	/workspace/18.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/21.spi_device_mailbox.3347778628
Short name	T191
Test name
Test status
Simulation time	5034619115 ps
CPU time	39.17 seconds
Started	Apr 30 03:20:50 PM PDT 24
Finished	Apr 30 03:21:30 PM PDT 24
Peak memory	237360 kb
Host	smart-a6d45c0d-2729-47ae-bb53-d133b50759b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347778628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3347778628
Directory	/workspace/21.spi_device_mailbox/latest

Test location	/workspace/coverage/default/22.spi_device_pass_cmd_filtering.2219402515
Short name	T58
Test name
Test status
Simulation time	1970821212 ps
CPU time	10.07 seconds
Started	Apr 30 03:20:57 PM PDT 24
Finished	Apr 30 03:21:08 PM PDT 24
Peak memory	228180 kb
Host	smart-c53c7248-f833-4064-87ad-5339edeaf371
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219402515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2219402515
Directory	/workspace/22.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/27.spi_device_mailbox.4170423136
Short name	T177
Test name
Test status
Simulation time	9767744496 ps
CPU time	94.33 seconds
Started	Apr 30 03:21:15 PM PDT 24
Finished	Apr 30 03:22:50 PM PDT 24
Peak memory	238732 kb
Host	smart-06e0f329-cdca-4d55-9ebc-8eda92fbd7ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170423136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4170423136
Directory	/workspace/27.spi_device_mailbox/latest

Test location	/workspace/coverage/default/3.spi_device_cfg_cmd.2126596764
Short name	T91
Test name
Test status
Simulation time	60099659 ps
CPU time	2.24 seconds
Started	Apr 30 03:19:52 PM PDT 24
Finished	Apr 30 03:19:55 PM PDT 24
Peak memory	218616 kb
Host	smart-b2debcc2-9afa-4a6a-84d3-d81d54e17e08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126596764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2126596764
Directory	/workspace/3.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/30.spi_device_pass_cmd_filtering.3555552111
Short name	T96
Test name
Test status
Simulation time	10028912866 ps
CPU time	35.87 seconds
Started	Apr 30 03:21:23 PM PDT 24
Finished	Apr 30 03:22:00 PM PDT 24
Peak memory	224408 kb
Host	smart-187effe2-538a-48ff-8ff4-c335eedf47e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555552111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3555552111
Directory	/workspace/30.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.64803489
Short name	T72
Test name
Test status
Simulation time	682838421 ps
CPU time	8.26 seconds
Started	Apr 30 03:21:22 PM PDT 24
Finished	Apr 30 03:21:31 PM PDT 24
Peak memory	218816 kb
Host	smart-01f37f63-b01f-4e89-ad4f-7821af6ddd48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64803489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.64803489
Directory	/workspace/31.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/33.spi_device_pass_cmd_filtering.2388813334
Short name	T276
Test name
Test status
Simulation time	493277755 ps
CPU time	3.92 seconds
Started	Apr 30 03:21:38 PM PDT 24
Finished	Apr 30 03:21:43 PM PDT 24
Peak memory	223012 kb
Host	smart-1f4a5ebf-ee2c-49f3-b90a-29a0192215d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388813334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2388813334
Directory	/workspace/33.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/36.spi_device_intercept.2045197188
Short name	T193
Test name
Test status
Simulation time	921394388 ps
CPU time	5.07 seconds
Started	Apr 30 03:21:43 PM PDT 24
Finished	Apr 30 03:21:49 PM PDT 24
Peak memory	218724 kb
Host	smart-2b10cdd7-8470-4271-92e4-852ddd94aa30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045197188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2045197188
Directory	/workspace/36.spi_device_intercept/latest

Test location	/workspace/coverage/default/36.spi_device_pass_cmd_filtering.707562719
Short name	T282
Test name
Test status
Simulation time	254928238 ps
CPU time	3.43 seconds
Started	Apr 30 03:21:45 PM PDT 24
Finished	Apr 30 03:21:49 PM PDT 24
Peak memory	222992 kb
Host	smart-3bd11444-de03-418a-ad3b-cba587854389
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707562719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.707562719
Directory	/workspace/36.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/37.spi_device_cfg_cmd.2456009879
Short name	T241
Test name
Test status
Simulation time	318856971 ps
CPU time	2.17 seconds
Started	Apr 30 03:21:52 PM PDT 24
Finished	Apr 30 03:21:54 PM PDT 24
Peak memory	218944 kb
Host	smart-bfa30bb0-d6a2-4759-8fd4-1fce95effb9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456009879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2456009879
Directory	/workspace/37.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/9.spi_device_pass_cmd_filtering.3396515874
Short name	T315
Test name
Test status
Simulation time	3899477918 ps
CPU time	14.77 seconds
Started	Apr 30 03:20:17 PM PDT 24
Finished	Apr 30 03:20:32 PM PDT 24
Peak memory	223220 kb
Host	smart-4a6019c9-ed1f-4aa9-a0c0-a14bc12191ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396515874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3396515874
Directory	/workspace/9.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/30.spi_device_mailbox.297043271
Short name	T85
Test name
Test status
Simulation time	189099489 ps
CPU time	5.34 seconds
Started	Apr 30 03:21:24 PM PDT 24
Finished	Apr 30 03:21:31 PM PDT 24
Peak memory	216812 kb
Host	smart-793ba9ec-1909-4637-b354-f4e10eea90ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=297043271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.297043271
Directory	/workspace/30.spi_device_mailbox/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_all.600912120
Short name	T107
Test name
Test status
Simulation time	7752823574 ps
CPU time	27.64 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:46 PM PDT 24
Peak memory	216292 kb
Host	smart-9873e9c0-be79-4465-89c3-fed063f9a03d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=600912120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.600912120
Directory	/workspace/29.spi_device_tpm_all/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.1911386716
Short name	T736
Test name
Test status
Simulation time	57699240 ps
CPU time	0.73 seconds
Started	Apr 30 03:02:09 PM PDT 24
Finished	Apr 30 03:02:11 PM PDT 24
Peak memory	204020 kb
Host	smart-b734e181-e254-4e2a-94cb-e8897a6d830e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911386716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test. 1911386716
Directory	/workspace/17.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2628673967
Short name	T375
Test name
Test status
Simulation time	55407458 ps
CPU time	1.98 seconds
Started	Apr 30 03:01:55 PM PDT 24
Finished	Apr 30 03:01:58 PM PDT 24
Peak memory	216272 kb
Host	smart-82ff69a8-baf8-4478-a812-56e2beb33f9f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628673967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2 628673967
Directory	/workspace/3.spi_device_tl_errors/latest

Test location	/workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3758922763
Short name	T205
Test name
Test status
Simulation time	2958918361 ps
CPU time	8.55 seconds
Started	Apr 30 03:19:43 PM PDT 24
Finished	Apr 30 03:19:52 PM PDT 24
Peak memory	218772 kb
Host	smart-e4f9f098-d2cf-42a1-a708-4af87db96397
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3758922763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap .3758922763
Directory	/workspace/0.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/1.spi_device_mailbox.3376352165
Short name	T93
Test name
Test status
Simulation time	3241575729 ps
CPU time	9.1 seconds
Started	Apr 30 03:19:45 PM PDT 24
Finished	Apr 30 03:19:55 PM PDT 24
Peak memory	218924 kb
Host	smart-56fc73e6-1c4e-4abe-9a21-319bb1bfc97f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376352165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3376352165
Directory	/workspace/1.spi_device_mailbox/latest

Test location	/workspace/coverage/default/1.spi_device_pass_addr_payload_swap.735728048
Short name	T291
Test name
Test status
Simulation time	86781004124 ps
CPU time	39.86 seconds
Started	Apr 30 03:19:44 PM PDT 24
Finished	Apr 30 03:20:25 PM PDT 24
Peak memory	236320 kb
Host	smart-e8c1ba9a-70b9-41b2-96a0-397588f85fb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735728048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap. 735728048
Directory	/workspace/1.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/10.spi_device_upload.735869090
Short name	T234
Test name
Test status
Simulation time	5315255052 ps
CPU time	4.23 seconds
Started	Apr 30 03:20:15 PM PDT 24
Finished	Apr 30 03:20:20 PM PDT 24
Peak memory	222680 kb
Host	smart-2cfcfef2-903a-4fa9-83be-aee4299e8c16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735869090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.735869090
Directory	/workspace/10.spi_device_upload/latest

Test location	/workspace/coverage/default/11.spi_device_intercept.1290810520
Short name	T122
Test name
Test status
Simulation time	9853051890 ps
CPU time	26.89 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:51 PM PDT 24
Peak memory	219120 kb
Host	smart-5be9911e-809e-44bc-9c72-cd14a048a170
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290810520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1290810520
Directory	/workspace/11.spi_device_intercept/latest

Test location	/workspace/coverage/default/12.spi_device_intercept.2150147027
Short name	T301
Test name
Test status
Simulation time	832306844 ps
CPU time	6.47 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:31 PM PDT 24
Peak memory	223732 kb
Host	smart-66a131c6-32bf-40c2-8c94-2468480fc4c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2150147027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2150147027
Directory	/workspace/12.spi_device_intercept/latest

Test location	/workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2100799304
Short name	T283
Test name
Test status
Simulation time	110224378 ps
CPU time	3.36 seconds
Started	Apr 30 03:20:22 PM PDT 24
Finished	Apr 30 03:20:26 PM PDT 24
Peak memory	222720 kb
Host	smart-6995f85f-016e-499a-af66-272439df1332
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100799304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa p.2100799304
Directory	/workspace/13.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/15.spi_device_mailbox.499304302
Short name	T357
Test name
Test status
Simulation time	7945574792 ps
CPU time	75.08 seconds
Started	Apr 30 03:20:31 PM PDT 24
Finished	Apr 30 03:21:48 PM PDT 24
Peak memory	240608 kb
Host	smart-5c3e4c76-3654-445f-b490-c3169005ca3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=499304302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.499304302
Directory	/workspace/15.spi_device_mailbox/latest

Test location	/workspace/coverage/default/16.spi_device_cfg_cmd.1840098409
Short name	T274
Test name
Test status
Simulation time	1510311429 ps
CPU time	14.75 seconds
Started	Apr 30 03:20:32 PM PDT 24
Finished	Apr 30 03:20:49 PM PDT 24
Peak memory	223960 kb
Host	smart-9cab7f51-95f3-43f1-aa08-a8b4f125bb08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840098409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1840098409
Directory	/workspace/16.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/16.spi_device_pass_addr_payload_swap.916786098
Short name	T231
Test name
Test status
Simulation time	1001456077 ps
CPU time	3.78 seconds
Started	Apr 30 03:20:33 PM PDT 24
Finished	Apr 30 03:20:39 PM PDT 24
Peak memory	222340 kb
Host	smart-4e152416-d430-4696-b61d-cf02185f5958
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916786098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap .916786098
Directory	/workspace/16.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1090762003
Short name	T226
Test name
Test status
Simulation time	543772552 ps
CPU time	3.57 seconds
Started	Apr 30 03:20:38 PM PDT 24
Finished	Apr 30 03:20:43 PM PDT 24
Peak memory	218492 kb
Host	smart-e6205798-2499-4114-a295-d6020f37a8de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090762003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa p.1090762003
Directory	/workspace/18.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2529727224
Short name	T333
Test name
Test status
Simulation time	1001861371 ps
CPU time	8.6 seconds
Started	Apr 30 03:20:39 PM PDT 24
Finished	Apr 30 03:20:49 PM PDT 24
Peak memory	234944 kb
Host	smart-44271a1b-6a6a-4135-a156-c45ee00e64e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2529727224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa p.2529727224
Directory	/workspace/19.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/22.spi_device_upload.673765950
Short name	T262
Test name
Test status
Simulation time	395161010 ps
CPU time	2.63 seconds
Started	Apr 30 03:20:57 PM PDT 24
Finished	Apr 30 03:21:00 PM PDT 24
Peak memory	216404 kb
Host	smart-a72047d3-00dc-48a1-bc79-db114331c044
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=673765950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.673765950
Directory	/workspace/22.spi_device_upload/latest

Test location	/workspace/coverage/default/23.spi_device_intercept.2750886206
Short name	T280
Test name
Test status
Simulation time	521596158 ps
CPU time	3.48 seconds
Started	Apr 30 03:21:01 PM PDT 24
Finished	Apr 30 03:21:05 PM PDT 24
Peak memory	218900 kb
Host	smart-b8c71d11-44fe-4368-9555-866de7a910f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2750886206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2750886206
Directory	/workspace/23.spi_device_intercept/latest

Test location	/workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4127308338
Short name	T329
Test name
Test status
Simulation time	335958330 ps
CPU time	4.13 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:12 PM PDT 24
Peak memory	221016 kb
Host	smart-863cbe24-619d-4bfe-9408-66a1a98642e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127308338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa p.4127308338
Directory	/workspace/25.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/25.spi_device_upload.568027640
Short name	T307
Test name
Test status
Simulation time	11113724412 ps
CPU time	19.84 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:27 PM PDT 24
Peak memory	219780 kb
Host	smart-1f7d75cd-3026-42ad-b752-e27679c34467
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568027640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.568027640
Directory	/workspace/25.spi_device_upload/latest

Test location	/workspace/coverage/default/27.spi_device_pass_cmd_filtering.1216309693
Short name	T264
Test name
Test status
Simulation time	553519530 ps
CPU time	4 seconds
Started	Apr 30 03:21:16 PM PDT 24
Finished	Apr 30 03:21:21 PM PDT 24
Peak memory	222740 kb
Host	smart-b7766ac5-b6af-4dae-b3ae-a173c0f5885a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216309693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1216309693
Directory	/workspace/27.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/28.spi_device_mailbox.4032674964
Short name	T321
Test name
Test status
Simulation time	10306947293 ps
CPU time	31.18 seconds
Started	Apr 30 03:21:18 PM PDT 24
Finished	Apr 30 03:21:50 PM PDT 24
Peak memory	237232 kb
Host	smart-74ad9acf-209d-4a16-86d3-799394302e4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4032674964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4032674964
Directory	/workspace/28.spi_device_mailbox/latest

Test location	/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1229990674
Short name	T216
Test name
Test status
Simulation time	508893470 ps
CPU time	5.38 seconds
Started	Apr 30 03:21:12 PM PDT 24
Finished	Apr 30 03:21:18 PM PDT 24
Peak memory	216820 kb
Host	smart-5c97f418-6a63-453e-b3c1-6a9f444b25a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229990674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa p.1229990674
Directory	/workspace/28.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.946742424
Short name	T212
Test name
Test status
Simulation time	585503697 ps
CPU time	6.62 seconds
Started	Apr 30 03:21:19 PM PDT 24
Finished	Apr 30 03:21:26 PM PDT 24
Peak memory	224400 kb
Host	smart-42eed6aa-75e1-40d7-a035-e1df592310ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946742424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap .946742424
Directory	/workspace/29.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/29.spi_device_upload.3995815080
Short name	T309
Test name
Test status
Simulation time	722575631 ps
CPU time	4.88 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:23 PM PDT 24
Peak memory	221664 kb
Host	smart-12b7d515-979b-481e-8305-535c8d2a9bfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995815080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3995815080
Directory	/workspace/29.spi_device_upload/latest

Test location	/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3276151938
Short name	T73
Test name
Test status
Simulation time	10099003319 ps
CPU time	16.38 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:21:51 PM PDT 24
Peak memory	234256 kb
Host	smart-dcc7a11c-b8e0-46bd-abdb-06a50058f9aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276151938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa p.3276151938
Directory	/workspace/33.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2068483380
Short name	T65
Test name
Test status
Simulation time	520474209 ps
CPU time	3.87 seconds
Started	Apr 30 03:21:43 PM PDT 24
Finished	Apr 30 03:21:47 PM PDT 24
Peak memory	221124 kb
Host	smart-a66efd0f-371e-4a2e-ac82-214239319ab2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068483380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa p.2068483380
Directory	/workspace/35.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/35.spi_device_pass_cmd_filtering.62426861
Short name	T63
Test name
Test status
Simulation time	32350992296 ps
CPU time	27.96 seconds
Started	Apr 30 03:21:41 PM PDT 24
Finished	Apr 30 03:22:10 PM PDT 24
Peak memory	232208 kb
Host	smart-2922ccff-fd09-46c6-b66b-4fc65bdeaac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62426861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.62426861
Directory	/workspace/35.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/36.spi_device_flash_mode.108318021
Short name	T339
Test name
Test status
Simulation time	1509063426 ps
CPU time	30.64 seconds
Started	Apr 30 03:21:53 PM PDT 24
Finished	Apr 30 03:22:24 PM PDT 24
Peak memory	234072 kb
Host	smart-17d34de4-f5a7-4487-a2f6-5119782bf733
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108318021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.108318021
Directory	/workspace/36.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/38.spi_device_pass_cmd_filtering.3569527102
Short name	T94
Test name
Test status
Simulation time	56861193545 ps
CPU time	32.8 seconds
Started	Apr 30 03:21:56 PM PDT 24
Finished	Apr 30 03:22:29 PM PDT 24
Peak memory	224428 kb
Host	smart-62969310-7f0b-428c-acf2-e6aab7e3776b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569527102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3569527102
Directory	/workspace/38.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/4.spi_device_mailbox.629149191
Short name	T304
Test name
Test status
Simulation time	18040076205 ps
CPU time	45.51 seconds
Started	Apr 30 03:19:59 PM PDT 24
Finished	Apr 30 03:20:46 PM PDT 24
Peak memory	221156 kb
Host	smart-2a0399e5-bb92-4eab-820f-300d15285053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629149191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.629149191
Directory	/workspace/4.spi_device_mailbox/latest

Test location	/workspace/coverage/default/4.spi_device_pass_addr_payload_swap.230214916
Short name	T190
Test name
Test status
Simulation time	4649819894 ps
CPU time	15.54 seconds
Started	Apr 30 03:19:53 PM PDT 24
Finished	Apr 30 03:20:10 PM PDT 24
Peak memory	237340 kb
Host	smart-1e3c129b-3db6-4417-a34b-5653c4d97892
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230214916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap. 230214916
Directory	/workspace/4.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/41.spi_device_mailbox.732244669
Short name	T318
Test name
Test status
Simulation time	1107029827 ps
CPU time	15.9 seconds
Started	Apr 30 03:22:13 PM PDT 24
Finished	Apr 30 03:22:30 PM PDT 24
Peak memory	224820 kb
Host	smart-719f55b1-56cf-4dd5-9dbd-181e06beaafa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=732244669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.732244669
Directory	/workspace/41.spi_device_mailbox/latest

Test location	/workspace/coverage/default/42.spi_device_flash_mode.2944404070
Short name	T343
Test name
Test status
Simulation time	7146673240 ps
CPU time	91.12 seconds
Started	Apr 30 03:22:09 PM PDT 24
Finished	Apr 30 03:23:41 PM PDT 24
Peak memory	250744 kb
Host	smart-8b348f45-6b82-4fb1-845a-702dc05e22a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2944404070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2944404070
Directory	/workspace/42.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/44.spi_device_flash_mode.3346939654
Short name	T354
Test name
Test status
Simulation time	319687437 ps
CPU time	11.04 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:32 PM PDT 24
Peak memory	249796 kb
Host	smart-2e9b535e-7e02-47a0-a73d-7ce54f2ab182
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346939654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3346939654
Directory	/workspace/44.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3529503409
Short name	T328
Test name
Test status
Simulation time	14663505632 ps
CPU time	23.86 seconds
Started	Apr 30 03:22:21 PM PDT 24
Finished	Apr 30 03:22:45 PM PDT 24
Peak memory	238000 kb
Host	smart-6ba8fbf2-ed5b-4ce4-a90d-3df39e4a3c0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529503409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa p.3529503409
Directory	/workspace/44.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4149071846
Short name	T267
Test name
Test status
Simulation time	47154151 ps
CPU time	2.4 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:23 PM PDT 24
Peak memory	222868 kb
Host	smart-4be229ed-a2d6-4f5f-b5e8-21e9b4e88c8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4149071846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa p.4149071846
Directory	/workspace/45.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/46.spi_device_pass_addr_payload_swap.155303324
Short name	T265
Test name
Test status
Simulation time	2022230512 ps
CPU time	11.94 seconds
Started	Apr 30 03:22:27 PM PDT 24
Finished	Apr 30 03:22:40 PM PDT 24
Peak memory	234832 kb
Host	smart-f9d002d6-5980-4cd9-82a3-1008ec26c8b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155303324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap .155303324
Directory	/workspace/46.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/49.spi_device_flash_mode.2255736262
Short name	T348
Test name
Test status
Simulation time	915536922 ps
CPU time	15.13 seconds
Started	Apr 30 03:22:42 PM PDT 24
Finished	Apr 30 03:22:57 PM PDT 24
Peak memory	236428 kb
Host	smart-27ee5a3e-e072-4c60-98a9-fa7a3d25a092
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2255736262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2255736262
Directory	/workspace/49.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2559536563
Short name	T75
Test name
Test status
Simulation time	18853602570 ps
CPU time	14.16 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:20:18 PM PDT 24
Peak memory	219188 kb
Host	smart-a7bc7090-fc9a-4162-8bdd-6ace61712ad8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559536563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap .2559536563
Directory	/workspace/5.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/6.spi_device_intercept.495062770
Short name	T313
Test name
Test status
Simulation time	1003047761 ps
CPU time	11.94 seconds
Started	Apr 30 03:20:02 PM PDT 24
Finished	Apr 30 03:20:16 PM PDT 24
Peak memory	218368 kb
Host	smart-3bb78ffe-c81e-47b6-9833-b0aa8f72751e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495062770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.495062770
Directory	/workspace/6.spi_device_intercept/latest

Test location	/workspace/coverage/default/7.spi_device_intercept.2728694136
Short name	T88
Test name
Test status
Simulation time	116756740 ps
CPU time	4.12 seconds
Started	Apr 30 03:20:15 PM PDT 24
Finished	Apr 30 03:20:21 PM PDT 24
Peak memory	222876 kb
Host	smart-40ac0ac9-5423-4786-a52b-18007ab1e60b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728694136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2728694136
Directory	/workspace/7.spi_device_intercept/latest

Test location	/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3202359612
Short name	T246
Test name
Test status
Simulation time	6781265223 ps
CPU time	19.69 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:20:24 PM PDT 24
Peak memory	226816 kb
Host	smart-81156fb8-568a-4ab1-b11d-2c02324b0e02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202359612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap .3202359612
Directory	/workspace/7.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/9.spi_device_cfg_cmd.3788354289
Short name	T203
Test name
Test status
Simulation time	565622663 ps
CPU time	2.81 seconds
Started	Apr 30 03:20:10 PM PDT 24
Finished	Apr 30 03:20:14 PM PDT 24
Peak memory	218912 kb
Host	smart-afdb2678-0e16-4b2d-9451-5ddb08db29f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788354289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3788354289
Directory	/workspace/9.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/20.spi_device_read_buffer_direct.2733311058
Short name	T114
Test name
Test status
Simulation time	160824974 ps
CPU time	3.51 seconds
Started	Apr 30 03:20:50 PM PDT 24
Finished	Apr 30 03:20:54 PM PDT 24
Peak memory	220064 kb
Host	smart-27fc563d-e911-43d9-9353-77580c61ac24
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2733311058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir ect.2733311058
Directory	/workspace/20.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3786379165
Short name	T99
Test name
Test status
Simulation time	32208829 ps
CPU time	1.21 seconds
Started	Apr 30 03:01:33 PM PDT 24
Finished	Apr 30 03:01:35 PM PDT 24
Peak memory	206900 kb
Host	smart-0124a5da-033a-47e1-8f0a-6d5fa32fcc32
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786379165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_hw_reset.3786379165
Directory	/workspace/0.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3828575810
Short name	T799
Test name
Test status
Simulation time	781819655 ps
CPU time	9.02 seconds
Started	Apr 30 03:01:35 PM PDT 24
Finished	Apr 30 03:01:45 PM PDT 24
Peak memory	206892 kb
Host	smart-49c8f172-e129-464f-9927-f6ef2f3ccdbc
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828575810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_aliasing.3828575810
Directory	/workspace/0.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.796206707
Short name	T779
Test name
Test status
Simulation time	7577918933 ps
CPU time	37.7 seconds
Started	Apr 30 03:01:43 PM PDT 24
Finished	Apr 30 03:02:22 PM PDT 24
Peak memory	206956 kb
Host	smart-58344d05-8bb5-4d13-85e3-3ff3d6e00949
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796206707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr _bit_bash.796206707
Directory	/workspace/0.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3280379819
Short name	T828
Test name
Test status
Simulation time	115388073 ps
CPU time	3.01 seconds
Started	Apr 30 03:01:44 PM PDT 24
Finished	Apr 30 03:01:48 PM PDT 24
Peak memory	216212 kb
Host	smart-249374a6-6d25-416c-9750-60de6c3b24ee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280379819 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3280379819
Directory	/workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2735667995
Short name	T769
Test name
Test status
Simulation time	27561241 ps
CPU time	1.94 seconds
Started	Apr 30 03:01:41 PM PDT 24
Finished	Apr 30 03:01:43 PM PDT 24
Peak memory	214920 kb
Host	smart-23aafa54-33cc-4f1e-9e62-a05c157f3f26
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735667995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2 735667995
Directory	/workspace/0.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3995298427
Short name	T761
Test name
Test status
Simulation time	21000277 ps
CPU time	0.8 seconds
Started	Apr 30 03:01:34 PM PDT 24
Finished	Apr 30 03:01:35 PM PDT 24
Peak memory	203772 kb
Host	smart-1f7d0f80-22c8-4b3a-9e1a-1362d90925df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995298427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3 995298427
Directory	/workspace/0.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1181476411
Short name	T813
Test name
Test status
Simulation time	47449523 ps
CPU time	1.78 seconds
Started	Apr 30 03:01:42 PM PDT 24
Finished	Apr 30 03:01:45 PM PDT 24
Peak memory	215172 kb
Host	smart-514897ab-0b6e-49b6-ac54-d5ea459bc195
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181476411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi _device_mem_partial_access.1181476411
Directory	/workspace/0.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.157693816
Short name	T743
Test name
Test status
Simulation time	32330604 ps
CPU time	0.65 seconds
Started	Apr 30 03:01:36 PM PDT 24
Finished	Apr 30 03:01:37 PM PDT 24
Peak memory	203364 kb
Host	smart-506fc7d4-b093-4255-b27c-a5f71332af45
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157693816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem _walk.157693816
Directory	/workspace/0.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4159106323
Short name	T155
Test name
Test status
Simulation time	29673447 ps
CPU time	1.91 seconds
Started	Apr 30 03:01:36 PM PDT 24
Finished	Apr 30 03:01:38 PM PDT 24
Peak memory	215076 kb
Host	smart-ab31aa8e-ac97-4363-9c3e-261fb4586bc9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159106323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s pi_device_same_csr_outstanding.4159106323
Directory	/workspace/0.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1952295587
Short name	T810
Test name
Test status
Simulation time	467275725 ps
CPU time	4.36 seconds
Started	Apr 30 03:01:36 PM PDT 24
Finished	Apr 30 03:01:41 PM PDT 24
Peak memory	215332 kb
Host	smart-2ea37cc3-2591-464e-ab48-87edd2d1f1f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952295587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1 952295587
Directory	/workspace/0.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3768790089
Short name	T845
Test name
Test status
Simulation time	550469088 ps
CPU time	14.45 seconds
Started	Apr 30 03:01:40 PM PDT 24
Finished	Apr 30 03:01:55 PM PDT 24
Peak memory	215468 kb
Host	smart-b370bbcb-2ad9-4193-9a92-e1e3f4957d0d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768790089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device _tl_intg_err.3768790089
Directory	/workspace/0.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1411524939
Short name	T151
Test name
Test status
Simulation time	208497842 ps
CPU time	15.64 seconds
Started	Apr 30 03:01:38 PM PDT 24
Finished	Apr 30 03:01:54 PM PDT 24
Peak memory	215068 kb
Host	smart-e673efbf-7534-4bc0-bac7-f9282d041503
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411524939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_aliasing.1411524939
Directory	/workspace/1.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1219429216
Short name	T763
Test name
Test status
Simulation time	7236328309 ps
CPU time	26.01 seconds
Started	Apr 30 03:01:35 PM PDT 24
Finished	Apr 30 03:02:01 PM PDT 24
Peak memory	215052 kb
Host	smart-8b1c5496-bc20-4ce6-b112-b2069affef3c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219429216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_bit_bash.1219429216
Directory	/workspace/1.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2250433257
Short name	T100
Test name
Test status
Simulation time	76578195 ps
CPU time	1.4 seconds
Started	Apr 30 03:01:36 PM PDT 24
Finished	Apr 30 03:01:38 PM PDT 24
Peak memory	216144 kb
Host	smart-ad728c63-5532-4edc-ba59-4861cab197b2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250433257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_hw_reset.2250433257
Directory	/workspace/1.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2030408862
Short name	T781
Test name
Test status
Simulation time	71735221 ps
CPU time	2.94 seconds
Started	Apr 30 03:01:41 PM PDT 24
Finished	Apr 30 03:01:44 PM PDT 24
Peak memory	216476 kb
Host	smart-a8c9f2d5-5ebc-408c-902b-f2fd45fb404a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030408862 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2030408862
Directory	/workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1121242232
Short name	T742
Test name
Test status
Simulation time	41587792 ps
CPU time	1.43 seconds
Started	Apr 30 03:01:47 PM PDT 24
Finished	Apr 30 03:01:49 PM PDT 24
Peak memory	206856 kb
Host	smart-d4b1c408-b52a-47e3-ae1c-d44f17aa7f44
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121242232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1 121242232
Directory	/workspace/1.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.1278097800
Short name	T745
Test name
Test status
Simulation time	14300209 ps
CPU time	0.73 seconds
Started	Apr 30 03:01:44 PM PDT 24
Finished	Apr 30 03:01:45 PM PDT 24
Peak memory	203792 kb
Host	smart-04b290c1-daab-492f-a632-904c2c56f22a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278097800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1 278097800
Directory	/workspace/1.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.605728057
Short name	T841
Test name
Test status
Simulation time	215298596 ps
CPU time	1.25 seconds
Started	Apr 30 03:01:36 PM PDT 24
Finished	Apr 30 03:01:38 PM PDT 24
Peak memory	215172 kb
Host	smart-ed1015af-c5d6-4de1-b06e-f5da2e2a0772
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605728057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_ device_mem_partial_access.605728057
Directory	/workspace/1.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4067402698
Short name	T771
Test name
Test status
Simulation time	33206074 ps
CPU time	0.66 seconds
Started	Apr 30 03:01:36 PM PDT 24
Finished	Apr 30 03:01:37 PM PDT 24
Peak memory	203356 kb
Host	smart-abd3919b-3afc-44a4-8238-3af0d8951e9d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067402698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me m_walk.4067402698
Directory	/workspace/1.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2053790212
Short name	T154
Test name
Test status
Simulation time	121251591 ps
CPU time	3.76 seconds
Started	Apr 30 03:01:50 PM PDT 24
Finished	Apr 30 03:01:55 PM PDT 24
Peak memory	215028 kb
Host	smart-f942e303-8f06-4cdf-a7b0-98455931b8bf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053790212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s pi_device_same_csr_outstanding.2053790212
Directory	/workspace/1.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1222368885
Short name	T819
Test name
Test status
Simulation time	152538421 ps
CPU time	3.28 seconds
Started	Apr 30 03:01:37 PM PDT 24
Finished	Apr 30 03:01:41 PM PDT 24
Peak memory	216424 kb
Host	smart-9c0d79c4-965c-4b8e-bf8b-6314cd083c12
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222368885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1 222368885
Directory	/workspace/1.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.920342617
Short name	T381
Test name
Test status
Simulation time	291737971 ps
CPU time	19.93 seconds
Started	Apr 30 03:01:35 PM PDT 24
Finished	Apr 30 03:01:55 PM PDT 24
Peak memory	215056 kb
Host	smart-be6f33bb-39db-4492-90f8-2f15c795415a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920342617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_ tl_intg_err.920342617
Directory	/workspace/1.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2083529678
Short name	T842
Test name
Test status
Simulation time	170557026 ps
CPU time	1.8 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:09 PM PDT 24
Peak memory	215180 kb
Host	smart-e1f345bc-fff5-4a40-93cf-403c2b561c0a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083529678 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2083529678
Directory	/workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2574525893
Short name	T790
Test name
Test status
Simulation time	111387787 ps
CPU time	1.87 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	206868 kb
Host	smart-b33af22e-800b-443b-814c-5d0712fe7b62
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574525893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw. 2574525893
Directory	/workspace/10.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1496740838
Short name	T806
Test name
Test status
Simulation time	70127469 ps
CPU time	0.7 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	203500 kb
Host	smart-532d3f0d-1093-490e-814a-19575cca3b72
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496740838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test. 1496740838
Directory	/workspace/10.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3181078909
Short name	T830
Test name
Test status
Simulation time	196044221 ps
CPU time	3.18 seconds
Started	Apr 30 03:01:59 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	215092 kb
Host	smart-e2d673cd-0ffb-45ac-a2a5-b7f149f0aad0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181078909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. spi_device_same_csr_outstanding.3181078909
Directory	/workspace/10.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2007981732
Short name	T128
Test name
Test status
Simulation time	226976886 ps
CPU time	2.36 seconds
Started	Apr 30 03:01:57 PM PDT 24
Finished	Apr 30 03:02:00 PM PDT 24
Peak memory	215204 kb
Host	smart-da8e5c4f-9333-4fe1-8872-d143b66b4590
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007981732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors. 2007981732
Directory	/workspace/10.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3155482875
Short name	T382
Test name
Test status
Simulation time	3404878570 ps
CPU time	19.94 seconds
Started	Apr 30 03:02:00 PM PDT 24
Finished	Apr 30 03:02:21 PM PDT 24
Peak memory	215140 kb
Host	smart-8fabe2b1-5eb7-4b84-a3dd-e236f7003771
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155482875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic e_tl_intg_err.3155482875
Directory	/workspace/10.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3272137153
Short name	T744
Test name
Test status
Simulation time	46617758 ps
CPU time	1.82 seconds
Started	Apr 30 03:01:59 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	215160 kb
Host	smart-5ba9cf29-e806-49e7-8b0f-76aea935d25a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272137153 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3272137153
Directory	/workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4051479210
Short name	T821
Test name
Test status
Simulation time	109136087 ps
CPU time	1.96 seconds
Started	Apr 30 03:01:52 PM PDT 24
Finished	Apr 30 03:01:54 PM PDT 24
Peak memory	206936 kb
Host	smart-e895bccf-7809-4a4a-9094-b2234e863d51
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051479210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw. 4051479210
Directory	/workspace/11.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.647937698
Short name	T765
Test name
Test status
Simulation time	16254702 ps
CPU time	0.77 seconds
Started	Apr 30 03:02:01 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	203492 kb
Host	smart-44067fe6-132f-47db-b775-bf79485d8fa8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647937698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.647937698
Directory	/workspace/11.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2748398007
Short name	T756
Test name
Test status
Simulation time	230804875 ps
CPU time	2.17 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	215136 kb
Host	smart-4c9b4ffc-7441-4c6d-9bfb-6009e4c6b718
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748398007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. spi_device_same_csr_outstanding.2748398007
Directory	/workspace/11.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.101100729
Short name	T39
Test name
Test status
Simulation time	124913275 ps
CPU time	2.14 seconds
Started	Apr 30 03:01:58 PM PDT 24
Finished	Apr 30 03:02:01 PM PDT 24
Peak memory	215224 kb
Host	smart-760c1518-c67b-44ae-a232-617ec4a38dd5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101100729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.101100729
Directory	/workspace/11.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1845336022
Short name	T793
Test name
Test status
Simulation time	299924810 ps
CPU time	3.63 seconds
Started	Apr 30 03:02:11 PM PDT 24
Finished	Apr 30 03:02:16 PM PDT 24
Peak memory	216704 kb
Host	smart-5514f4ba-6f9c-4b24-9e5e-dd6c4c79b39a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845336022 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1845336022
Directory	/workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1204080225
Short name	T824
Test name
Test status
Simulation time	110897400 ps
CPU time	1.28 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	206864 kb
Host	smart-c721a28e-c132-4deb-b267-37166225c27c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204080225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw. 1204080225
Directory	/workspace/12.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2448169415
Short name	T804
Test name
Test status
Simulation time	28240120 ps
CPU time	0.68 seconds
Started	Apr 30 03:02:01 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	203512 kb
Host	smart-c1896c3f-d328-4ada-a950-09e0788caeaf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448169415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test. 2448169415
Directory	/workspace/12.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4127689400
Short name	T747
Test name
Test status
Simulation time	228030592 ps
CPU time	4.17 seconds
Started	Apr 30 03:02:00 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	215136 kb
Host	smart-b5276f3a-54d9-41c5-a77d-26f4fa4b3922
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127689400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. spi_device_same_csr_outstanding.4127689400
Directory	/workspace/12.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1950885170
Short name	T123
Test name
Test status
Simulation time	166349646 ps
CPU time	2.4 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:07 PM PDT 24
Peak memory	215272 kb
Host	smart-0420c319-7bc0-4c53-a0a9-bc048fca3d08
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950885170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors. 1950885170
Directory	/workspace/12.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2255833987
Short name	T118
Test name
Test status
Simulation time	2229147941 ps
CPU time	8.21 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:14 PM PDT 24
Peak memory	215400 kb
Host	smart-a3ef858f-f7a4-4bfc-b9da-8229aac6db12
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255833987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic e_tl_intg_err.2255833987
Directory	/workspace/12.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4039409254
Short name	T822
Test name
Test status
Simulation time	684342195 ps
CPU time	3.87 seconds
Started	Apr 30 03:01:58 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	217048 kb
Host	smart-b7ab9f25-e175-49d5-8c99-18468931d471
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039409254 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4039409254
Directory	/workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1717923574
Short name	T735
Test name
Test status
Simulation time	37350969 ps
CPU time	0.71 seconds
Started	Apr 30 03:01:56 PM PDT 24
Finished	Apr 30 03:01:58 PM PDT 24
Peak memory	203484 kb
Host	smart-99757a1d-91ef-497a-92eb-1f35fe2f6b52
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717923574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test. 1717923574
Directory	/workspace/13.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3999958660
Short name	T134
Test name
Test status
Simulation time	285258659 ps
CPU time	1.95 seconds
Started	Apr 30 03:01:57 PM PDT 24
Finished	Apr 30 03:01:59 PM PDT 24
Peak memory	215060 kb
Host	smart-dc530bed-ab0c-49cb-9797-b41cdd15a90b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999958660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. spi_device_same_csr_outstanding.3999958660
Directory	/workspace/13.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.127962514
Short name	T787
Test name
Test status
Simulation time	1044184169 ps
CPU time	2.61 seconds
Started	Apr 30 03:02:00 PM PDT 24
Finished	Apr 30 03:02:04 PM PDT 24
Peak memory	215152 kb
Host	smart-0cb50567-b0c6-4765-9ba3-06e08cd175bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127962514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.127962514
Directory	/workspace/13.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.838662123
Short name	T380
Test name
Test status
Simulation time	106126636 ps
CPU time	7.37 seconds
Started	Apr 30 03:01:56 PM PDT 24
Finished	Apr 30 03:02:04 PM PDT 24
Peak memory	215132 kb
Host	smart-f260c054-dc38-4068-8102-2208a2c66f46
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838662123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device _tl_intg_err.838662123
Directory	/workspace/13.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4019499962
Short name	T161
Test name
Test status
Simulation time	423897250 ps
CPU time	4.04 seconds
Started	Apr 30 03:01:56 PM PDT 24
Finished	Apr 30 03:02:01 PM PDT 24
Peak memory	217012 kb
Host	smart-7516a7f0-a883-4cf3-9f73-339d8badb17a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019499962 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4019499962
Directory	/workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1013226715
Short name	T760
Test name
Test status
Simulation time	69355763 ps
CPU time	1.45 seconds
Started	Apr 30 03:02:00 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	206876 kb
Host	smart-f6c7c379-54ad-42ec-ad27-ba01ebe1659d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013226715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw. 1013226715
Directory	/workspace/14.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.3808938670
Short name	T788
Test name
Test status
Simulation time	25537136 ps
CPU time	0.7 seconds
Started	Apr 30 03:01:59 PM PDT 24
Finished	Apr 30 03:02:01 PM PDT 24
Peak memory	203796 kb
Host	smart-6b3803ef-fca7-4f0e-803f-cf3054e8268a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808938670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test. 3808938670
Directory	/workspace/14.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.494189490
Short name	T775
Test name
Test status
Simulation time	113840000 ps
CPU time	3.62 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	215028 kb
Host	smart-e5b903ab-6941-4c92-ab68-103072911c42
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494189490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s pi_device_same_csr_outstanding.494189490
Directory	/workspace/14.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3927081257
Short name	T132
Test name
Test status
Simulation time	258690048 ps
CPU time	1.94 seconds
Started	Apr 30 03:02:08 PM PDT 24
Finished	Apr 30 03:02:11 PM PDT 24
Peak memory	215324 kb
Host	smart-63d1b9e0-df14-41cd-9733-3b09a81cb36a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927081257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors. 3927081257
Directory	/workspace/14.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2397390892
Short name	T815
Test name
Test status
Simulation time	1898801204 ps
CPU time	3.72 seconds
Started	Apr 30 03:02:10 PM PDT 24
Finished	Apr 30 03:02:15 PM PDT 24
Peak memory	216804 kb
Host	smart-30ee18b4-3769-4069-8d21-0a239534ef11
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397390892 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2397390892
Directory	/workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.780513779
Short name	T786
Test name
Test status
Simulation time	140886692 ps
CPU time	2.09 seconds
Started	Apr 30 03:01:55 PM PDT 24
Finished	Apr 30 03:01:58 PM PDT 24
Peak memory	215080 kb
Host	smart-18760e03-0b42-461d-980c-ac4fd94d1ba6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780513779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.780513779
Directory	/workspace/15.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3599572581
Short name	T168
Test name
Test status
Simulation time	18009102 ps
CPU time	0.77 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:04 PM PDT 24
Peak memory	203564 kb
Host	smart-5c72c47a-a7bb-41b9-b258-0566250e30bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599572581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test. 3599572581
Directory	/workspace/15.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2850585121
Short name	T751
Test name
Test status
Simulation time	2056132604 ps
CPU time	2.89 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:07 PM PDT 24
Peak memory	215064 kb
Host	smart-287a3dd6-a9d8-4bb7-a0cf-00d0b6bf8f29
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850585121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. spi_device_same_csr_outstanding.2850585121
Directory	/workspace/15.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.323449491
Short name	T129
Test name
Test status
Simulation time	88432394 ps
CPU time	3.39 seconds
Started	Apr 30 03:01:58 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	215384 kb
Host	smart-49ae3c9f-490a-4b2d-8ef3-d13b458b3e5c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323449491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.323449491
Directory	/workspace/15.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3855578047
Short name	T378
Test name
Test status
Simulation time	109998141 ps
CPU time	6.56 seconds
Started	Apr 30 03:01:57 PM PDT 24
Finished	Apr 30 03:02:04 PM PDT 24
Peak memory	215112 kb
Host	smart-8902ad8a-c7fb-47c8-abf8-8f2b4ac32826
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855578047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic e_tl_intg_err.3855578047
Directory	/workspace/15.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4249202884
Short name	T140
Test name
Test status
Simulation time	179910695 ps
CPU time	1.77 seconds
Started	Apr 30 03:02:05 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	215148 kb
Host	smart-eeb6f079-c07e-4225-a59d-176c2e8e009c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249202884 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4249202884
Directory	/workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3684930746
Short name	T145
Test name
Test status
Simulation time	21871625 ps
CPU time	1.31 seconds
Started	Apr 30 03:02:08 PM PDT 24
Finished	Apr 30 03:02:10 PM PDT 24
Peak memory	215084 kb
Host	smart-5fc9567b-bebd-4516-9dde-d7685264fcad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684930746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw. 3684930746
Directory	/workspace/16.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.600028945
Short name	T846
Test name
Test status
Simulation time	31653805 ps
CPU time	0.69 seconds
Started	Apr 30 03:02:09 PM PDT 24
Finished	Apr 30 03:02:11 PM PDT 24
Peak memory	203480 kb
Host	smart-1e7b4e94-a432-4ec7-baf7-48039bb0654f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600028945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.600028945
Directory	/workspace/16.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2651240413
Short name	T41
Test name
Test status
Simulation time	158214818 ps
CPU time	2.65 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:10 PM PDT 24
Peak memory	215124 kb
Host	smart-27965e89-e25d-494d-a544-170f58634ec3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651240413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. spi_device_same_csr_outstanding.2651240413
Directory	/workspace/16.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.846567285
Short name	T825
Test name
Test status
Simulation time	737427032 ps
CPU time	2.11 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:09 PM PDT 24
Peak memory	215300 kb
Host	smart-de31c9fb-173e-4dc4-9521-6ba201c32cb9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846567285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.846567285
Directory	/workspace/16.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2339907515
Short name	T377
Test name
Test status
Simulation time	119071684 ps
CPU time	7.23 seconds
Started	Apr 30 03:01:59 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	215104 kb
Host	smart-affac48c-ac38-422f-8b39-3b834e2061ca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339907515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic e_tl_intg_err.2339907515
Directory	/workspace/16.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2454038158
Short name	T40
Test name
Test status
Simulation time	54776244 ps
CPU time	3.54 seconds
Started	Apr 30 03:02:05 PM PDT 24
Finished	Apr 30 03:02:10 PM PDT 24
Peak memory	217216 kb
Host	smart-e3c9ffb7-22c7-4d4d-9497-1ed1a2176ebe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454038158 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2454038158
Directory	/workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.342218476
Short name	T773
Test name
Test status
Simulation time	73138548 ps
CPU time	2.21 seconds
Started	Apr 30 03:01:59 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	206908 kb
Host	smart-b9c460d3-6840-4b61-a4e3-ba82826c08aa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342218476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.342218476
Directory	/workspace/17.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2309721437
Short name	T839
Test name
Test status
Simulation time	300503760 ps
CPU time	4.63 seconds
Started	Apr 30 03:01:59 PM PDT 24
Finished	Apr 30 03:02:04 PM PDT 24
Peak memory	215284 kb
Host	smart-e46db12c-b65f-4e31-9d30-23090e217d47
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309721437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. spi_device_same_csr_outstanding.2309721437
Directory	/workspace/17.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1306183604
Short name	T136
Test name
Test status
Simulation time	252563573 ps
CPU time	4.83 seconds
Started	Apr 30 03:01:57 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	215204 kb
Host	smart-15d1fe1e-c0a3-4549-ad0e-c622b41ed4f8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306183604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors. 1306183604
Directory	/workspace/17.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.10122103
Short name	T801
Test name
Test status
Simulation time	306398694 ps
CPU time	19.84 seconds
Started	Apr 30 03:02:08 PM PDT 24
Finished	Apr 30 03:02:29 PM PDT 24
Peak memory	215508 kb
Host	smart-c315fe31-67eb-47f9-af6a-1eb1c3f7c60a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10122103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_ tl_intg_err.10122103
Directory	/workspace/17.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2676602263
Short name	T838
Test name
Test status
Simulation time	103955981 ps
CPU time	1.73 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:04 PM PDT 24
Peak memory	215196 kb
Host	smart-2b9b0c0d-aa25-41a7-be4f-4465f946adea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676602263 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2676602263
Directory	/workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.713481991
Short name	T741
Test name
Test status
Simulation time	22240875 ps
CPU time	1.25 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:07 PM PDT 24
Peak memory	206856 kb
Host	smart-2c29719b-798f-4c5f-b10b-6dc6b517336f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713481991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.713481991
Directory	/workspace/18.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2342881936
Short name	T836
Test name
Test status
Simulation time	17147514 ps
CPU time	0.74 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	203536 kb
Host	smart-3d5f629d-3969-422b-851f-753f39fd9790
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342881936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test. 2342881936
Directory	/workspace/18.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2299782251
Short name	T772
Test name
Test status
Simulation time	1183442669 ps
CPU time	2.91 seconds
Started	Apr 30 03:02:01 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	215136 kb
Host	smart-6bfcb110-9ff5-41d4-b424-966748fc8897
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299782251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. spi_device_same_csr_outstanding.2299782251
Directory	/workspace/18.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.376343038
Short name	T379
Test name
Test status
Simulation time	857578931 ps
CPU time	22.6 seconds
Started	Apr 30 03:02:08 PM PDT 24
Finished	Apr 30 03:02:32 PM PDT 24
Peak memory	216476 kb
Host	smart-d313424d-27c7-4ae0-a46b-20b761314728
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376343038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device _tl_intg_err.376343038
Directory	/workspace/18.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.296894898
Short name	T792
Test name
Test status
Simulation time	249168703 ps
CPU time	3.67 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:11 PM PDT 24
Peak memory	217304 kb
Host	smart-7b7bf098-eb2c-42d5-887e-78c7fd48a107
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296894898 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.296894898
Directory	/workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2779873764
Short name	T144
Test name
Test status
Simulation time	65982075 ps
CPU time	2.42 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:09 PM PDT 24
Peak memory	215060 kb
Host	smart-d1edf747-853d-4624-b6eb-ba4849c15260
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779873764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw. 2779873764
Directory	/workspace/19.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1374724006
Short name	T732
Test name
Test status
Simulation time	12710855 ps
CPU time	0.71 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:07 PM PDT 24
Peak memory	203804 kb
Host	smart-9b3f5f77-4b22-4115-9430-bd6dad80f895
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374724006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test. 1374724006
Directory	/workspace/19.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.320610757
Short name	T754
Test name
Test status
Simulation time	231971636 ps
CPU time	1.81 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:09 PM PDT 24
Peak memory	215036 kb
Host	smart-a8ede22a-058e-4b79-9c58-c65a08b08a9e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320610757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s pi_device_same_csr_outstanding.320610757
Directory	/workspace/19.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1014335425
Short name	T812
Test name
Test status
Simulation time	126185360 ps
CPU time	3 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:10 PM PDT 24
Peak memory	216328 kb
Host	smart-7ab7e1f3-0f79-4ebf-86ce-1cc8c512e5f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014335425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors. 1014335425
Directory	/workspace/19.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3167629864
Short name	T383
Test name
Test status
Simulation time	407456397 ps
CPU time	6.81 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:14 PM PDT 24
Peak memory	215464 kb
Host	smart-835069ca-8f63-468d-aa6c-fff2b67bae5a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167629864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic e_tl_intg_err.3167629864
Directory	/workspace/19.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3400409540
Short name	T784
Test name
Test status
Simulation time	119004104 ps
CPU time	8.33 seconds
Started	Apr 30 03:01:52 PM PDT 24
Finished	Apr 30 03:02:01 PM PDT 24
Peak memory	215072 kb
Host	smart-d49c8a6f-1d15-412f-8bc6-de2af41382d1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400409540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_aliasing.3400409540
Directory	/workspace/2.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3315265835
Short name	T789
Test name
Test status
Simulation time	353313795 ps
CPU time	23.01 seconds
Started	Apr 30 03:01:52 PM PDT 24
Finished	Apr 30 03:02:16 PM PDT 24
Peak memory	206876 kb
Host	smart-104a62c6-54db-44ac-830d-e27b1d475365
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315265835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_bit_bash.3315265835
Directory	/workspace/2.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3011579373
Short name	T776
Test name
Test status
Simulation time	62728739 ps
CPU time	1.14 seconds
Started	Apr 30 03:01:54 PM PDT 24
Finished	Apr 30 03:01:56 PM PDT 24
Peak memory	216080 kb
Host	smart-7de083ef-8e0c-42aa-83af-c58e03735fd7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011579373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_hw_reset.3011579373
Directory	/workspace/2.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.803209380
Short name	T38
Test name
Test status
Simulation time	274173493 ps
CPU time	1.66 seconds
Started	Apr 30 03:01:49 PM PDT 24
Finished	Apr 30 03:01:51 PM PDT 24
Peak memory	215164 kb
Host	smart-bfbbdb53-efff-4f8e-bc59-c69237fe0a1f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803209380 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.803209380
Directory	/workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.922115774
Short name	T798
Test name
Test status
Simulation time	28008081 ps
CPU time	1.3 seconds
Started	Apr 30 03:01:43 PM PDT 24
Finished	Apr 30 03:01:45 PM PDT 24
Peak memory	215140 kb
Host	smart-07ea064f-873d-44ca-aa5a-0496e46c4a39
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922115774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.922115774
Directory	/workspace/2.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.2683516320
Short name	T791
Test name
Test status
Simulation time	14356974 ps
CPU time	0.73 seconds
Started	Apr 30 03:01:54 PM PDT 24
Finished	Apr 30 03:01:55 PM PDT 24
Peak memory	203436 kb
Host	smart-d06b147f-5e14-4caa-96e6-201676cfa850
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683516320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2 683516320
Directory	/workspace/2.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1700333748
Short name	T774
Test name
Test status
Simulation time	78616384 ps
CPU time	1.36 seconds
Started	Apr 30 03:01:45 PM PDT 24
Finished	Apr 30 03:01:47 PM PDT 24
Peak memory	215116 kb
Host	smart-c0ad3177-829e-4607-9610-e2b615cca050
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700333748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi _device_mem_partial_access.1700333748
Directory	/workspace/2.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2065192062
Short name	T762
Test name
Test status
Simulation time	12554742 ps
CPU time	0.68 seconds
Started	Apr 30 03:01:51 PM PDT 24
Finished	Apr 30 03:01:52 PM PDT 24
Peak memory	203356 kb
Host	smart-a7c8ffde-a422-47af-9646-fd8390612741
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065192062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me m_walk.2065192062
Directory	/workspace/2.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3239228255
Short name	T820
Test name
Test status
Simulation time	2171418681 ps
CPU time	3.18 seconds
Started	Apr 30 03:01:48 PM PDT 24
Finished	Apr 30 03:01:51 PM PDT 24
Peak memory	215128 kb
Host	smart-c8087833-8c2d-4ce4-96c7-e69bae29d7a6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239228255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s pi_device_same_csr_outstanding.3239228255
Directory	/workspace/2.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3032453833
Short name	T139
Test name
Test status
Simulation time	307296102 ps
CPU time	2.47 seconds
Started	Apr 30 03:01:49 PM PDT 24
Finished	Apr 30 03:01:52 PM PDT 24
Peak memory	215204 kb
Host	smart-921c3026-3c3a-4df1-a6b8-4a8a144f383b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032453833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3 032453833
Directory	/workspace/2.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.444194484
Short name	T167
Test name
Test status
Simulation time	41611392 ps
CPU time	0.68 seconds
Started	Apr 30 03:02:12 PM PDT 24
Finished	Apr 30 03:02:14 PM PDT 24
Peak memory	203516 kb
Host	smart-5e3a6d5e-02bf-4bbf-917b-45d809782a4b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444194484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.444194484
Directory	/workspace/20.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.1041668651
Short name	T740
Test name
Test status
Simulation time	11108052 ps
CPU time	0.75 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	203564 kb
Host	smart-1c0d8b4d-bc9f-46db-863e-a036e4c09be8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041668651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test. 1041668651
Directory	/workspace/21.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1989980521
Short name	T818
Test name
Test status
Simulation time	34112868 ps
CPU time	0.7 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	203828 kb
Host	smart-8904ea93-2d18-4ef9-b1f0-25f3f53fb0ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989980521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test. 1989980521
Directory	/workspace/22.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.4107740485
Short name	T794
Test name
Test status
Simulation time	13241106 ps
CPU time	0.72 seconds
Started	Apr 30 03:02:08 PM PDT 24
Finished	Apr 30 03:02:10 PM PDT 24
Peak memory	203456 kb
Host	smart-b5f728e0-e0bf-4d1a-8ea8-090e4ba4c53c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107740485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test. 4107740485
Directory	/workspace/23.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.4070320355
Short name	T807
Test name
Test status
Simulation time	44715977 ps
CPU time	0.73 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	203500 kb
Host	smart-bdce1816-6c57-4d75-bc93-dce2d8e1c289
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070320355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test. 4070320355
Directory	/workspace/24.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.3103155453
Short name	T817
Test name
Test status
Simulation time	15312207 ps
CPU time	0.7 seconds
Started	Apr 30 03:02:05 PM PDT 24
Finished	Apr 30 03:02:07 PM PDT 24
Peak memory	203456 kb
Host	smart-19436e3a-ebb2-4864-8694-2ca2a212f6f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103155453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test. 3103155453
Directory	/workspace/25.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.4093112149
Short name	T752
Test name
Test status
Simulation time	26050856 ps
CPU time	0.72 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:12 PM PDT 24
Peak memory	203820 kb
Host	smart-ba3885eb-f1e4-497a-bb31-db0b82dc0835
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093112149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test. 4093112149
Directory	/workspace/26.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.2865406178
Short name	T767
Test name
Test status
Simulation time	12490620 ps
CPU time	0.73 seconds
Started	Apr 30 03:02:07 PM PDT 24
Finished	Apr 30 03:02:09 PM PDT 24
Peak memory	203492 kb
Host	smart-00991fad-ca9f-4e40-98ec-e641312cfbd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865406178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test. 2865406178
Directory	/workspace/27.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.3748272620
Short name	T757
Test name
Test status
Simulation time	23292456 ps
CPU time	0.74 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	203864 kb
Host	smart-2c3ce36d-cbb2-422a-9139-b24e18421205
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748272620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test. 3748272620
Directory	/workspace/28.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.897861272
Short name	T785
Test name
Test status
Simulation time	14858782 ps
CPU time	0.76 seconds
Started	Apr 30 03:02:11 PM PDT 24
Finished	Apr 30 03:02:14 PM PDT 24
Peak memory	203508 kb
Host	smart-68605dc6-edba-4fdc-b438-3da624f2ebd9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897861272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.897861272
Directory	/workspace/29.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.288786662
Short name	T149
Test name
Test status
Simulation time	636306296 ps
CPU time	16.11 seconds
Started	Apr 30 03:01:51 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	215040 kb
Host	smart-291ea99a-9156-4f09-87d0-8d41d815d180
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288786662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr _aliasing.288786662
Directory	/workspace/3.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3914371548
Short name	T777
Test name
Test status
Simulation time	7538287489 ps
CPU time	38.59 seconds
Started	Apr 30 03:01:46 PM PDT 24
Finished	Apr 30 03:02:25 PM PDT 24
Peak memory	206884 kb
Host	smart-b62e94b5-cbe4-4a1e-aabc-2e83283f724b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914371548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_bit_bash.3914371548
Directory	/workspace/3.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.332889677
Short name	T98
Test name
Test status
Simulation time	19539792 ps
CPU time	1.16 seconds
Started	Apr 30 03:01:56 PM PDT 24
Finished	Apr 30 03:01:58 PM PDT 24
Peak memory	206872 kb
Host	smart-ce82d573-68e5-4383-b93c-d635c1a588d7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332889677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr _hw_reset.332889677
Directory	/workspace/3.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2185864248
Short name	T800
Test name
Test status
Simulation time	58040435 ps
CPU time	3.99 seconds
Started	Apr 30 03:01:46 PM PDT 24
Finished	Apr 30 03:01:51 PM PDT 24
Peak memory	217208 kb
Host	smart-783bebe6-17f3-4d17-92f0-d60c740b0c78
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185864248 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2185864248
Directory	/workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2602189855
Short name	T829
Test name
Test status
Simulation time	139703371 ps
CPU time	2.95 seconds
Started	Apr 30 03:01:57 PM PDT 24
Finished	Apr 30 03:02:01 PM PDT 24
Peak memory	206816 kb
Host	smart-01f31ee0-c808-497d-9a17-9cd98de58dc3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602189855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2 602189855
Directory	/workspace/3.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2121643301
Short name	T833
Test name
Test status
Simulation time	15285777 ps
CPU time	0.68 seconds
Started	Apr 30 03:01:45 PM PDT 24
Finished	Apr 30 03:01:46 PM PDT 24
Peak memory	203536 kb
Host	smart-2402472b-dab5-4288-8d8d-929644f5465e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121643301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2 121643301
Directory	/workspace/3.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2505640045
Short name	T150
Test name
Test status
Simulation time	168302447 ps
CPU time	1.89 seconds
Started	Apr 30 03:01:47 PM PDT 24
Finished	Apr 30 03:01:49 PM PDT 24
Peak memory	215296 kb
Host	smart-1d732074-6066-4d35-abf2-333a7c84a619
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505640045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi _device_mem_partial_access.2505640045
Directory	/workspace/3.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.767956351
Short name	T731
Test name
Test status
Simulation time	162595676 ps
CPU time	0.68 seconds
Started	Apr 30 03:01:43 PM PDT 24
Finished	Apr 30 03:01:45 PM PDT 24
Peak memory	203348 kb
Host	smart-da4a4772-73fe-427d-bba9-c945b00d1dc1
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767956351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem _walk.767956351
Directory	/workspace/3.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.910929487
Short name	T811
Test name
Test status
Simulation time	56828564 ps
CPU time	3.42 seconds
Started	Apr 30 03:01:44 PM PDT 24
Finished	Apr 30 03:01:48 PM PDT 24
Peak memory	215060 kb
Host	smart-eda1a0e8-d368-4db7-80d7-ebf247d843fa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910929487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp i_device_same_csr_outstanding.910929487
Directory	/workspace/3.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1805467813
Short name	T141
Test name
Test status
Simulation time	565369253 ps
CPU time	15.39 seconds
Started	Apr 30 03:01:49 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	216388 kb
Host	smart-3f44b9a7-ab5c-48dd-9e20-8b9945d6d8bf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805467813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device _tl_intg_err.1805467813
Directory	/workspace/3.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.2371105004
Short name	T768
Test name
Test status
Simulation time	62194535 ps
CPU time	0.72 seconds
Started	Apr 30 03:02:09 PM PDT 24
Finished	Apr 30 03:02:11 PM PDT 24
Peak memory	203496 kb
Host	smart-eabd4f73-e053-471b-8c32-9c67c0b9f9cc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371105004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test. 2371105004
Directory	/workspace/30.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.4208780424
Short name	T738
Test name
Test status
Simulation time	16719299 ps
CPU time	0.74 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	203444 kb
Host	smart-9af8b37e-eb13-444e-92f8-e572637c87f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208780424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test. 4208780424
Directory	/workspace/31.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.529116422
Short name	T753
Test name
Test status
Simulation time	57919772 ps
CPU time	0.74 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	203528 kb
Host	smart-155b7e1c-7d8e-48e9-a842-a13ea4f99c63
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529116422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.529116422
Directory	/workspace/32.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.1434256156
Short name	T764
Test name
Test status
Simulation time	14366550 ps
CPU time	0.73 seconds
Started	Apr 30 03:02:11 PM PDT 24
Finished	Apr 30 03:02:14 PM PDT 24
Peak memory	203796 kb
Host	smart-bf817ed6-d01e-4a97-aab6-2dcf4b72cf74
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434256156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test. 1434256156
Directory	/workspace/33.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.2425077397
Short name	T803
Test name
Test status
Simulation time	45381017 ps
CPU time	0.77 seconds
Started	Apr 30 03:02:12 PM PDT 24
Finished	Apr 30 03:02:14 PM PDT 24
Peak memory	203440 kb
Host	smart-9f3adc4e-af5f-450f-bb5a-54dd3f0279b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425077397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test. 2425077397
Directory	/workspace/34.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3133012297
Short name	T780
Test name
Test status
Simulation time	44074734 ps
CPU time	0.78 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	203504 kb
Host	smart-b20794a9-baec-4e04-a570-c077f8e630d5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133012297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test. 3133012297
Directory	/workspace/35.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.3275228333
Short name	T844
Test name
Test status
Simulation time	49462870 ps
CPU time	0.74 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	203444 kb
Host	smart-b5b449a7-6079-4ef4-bf3c-49d81268a978
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275228333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test. 3275228333
Directory	/workspace/36.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.1989462812
Short name	T835
Test name
Test status
Simulation time	45136551 ps
CPU time	0.74 seconds
Started	Apr 30 03:02:08 PM PDT 24
Finished	Apr 30 03:02:10 PM PDT 24
Peak memory	203728 kb
Host	smart-5819b6de-9ed2-449b-b007-882bd11720dc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989462812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test. 1989462812
Directory	/workspace/37.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.1598605089
Short name	T739
Test name
Test status
Simulation time	14209099 ps
CPU time	0.79 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:11 PM PDT 24
Peak memory	203368 kb
Host	smart-451aff67-1737-4f26-b184-06d578c8cffb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598605089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test. 1598605089
Directory	/workspace/38.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1210520352
Short name	T834
Test name
Test status
Simulation time	27729677 ps
CPU time	0.74 seconds
Started	Apr 30 03:02:07 PM PDT 24
Finished	Apr 30 03:02:09 PM PDT 24
Peak memory	203508 kb
Host	smart-dbecab6f-f4a2-4fdc-aed3-668e95af8533
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210520352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test. 1210520352
Directory	/workspace/39.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1961104330
Short name	T827
Test name
Test status
Simulation time	1425248300 ps
CPU time	15.64 seconds
Started	Apr 30 03:01:50 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	206808 kb
Host	smart-5bd38f12-39bb-479b-8a83-80bf7c936c57
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961104330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_aliasing.1961104330
Directory	/workspace/4.spi_device_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.86657877
Short name	T152
Test name
Test status
Simulation time	1817136899 ps
CPU time	27.11 seconds
Started	Apr 30 03:01:49 PM PDT 24
Finished	Apr 30 03:02:17 PM PDT 24
Peak memory	215120 kb
Host	smart-8b7bf246-cf5d-4e12-8702-26235cca3908
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86657877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_ bit_bash.86657877
Directory	/workspace/4.spi_device_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.428056810
Short name	T97
Test name
Test status
Simulation time	20078859 ps
CPU time	1.02 seconds
Started	Apr 30 03:01:51 PM PDT 24
Finished	Apr 30 03:01:52 PM PDT 24
Peak memory	206732 kb
Host	smart-e815a4a9-40b9-4204-af2e-1697b267f83e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428056810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr _hw_reset.428056810
Directory	/workspace/4.spi_device_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4125624427
Short name	T159
Test name
Test status
Simulation time	103862754 ps
CPU time	2.65 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	216172 kb
Host	smart-10d8e6f2-ddd7-4548-8bab-08b4a2c64471
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125624427 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4125624427
Directory	/workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3943874048
Short name	T146
Test name
Test status
Simulation time	38489280 ps
CPU time	2.61 seconds
Started	Apr 30 03:01:52 PM PDT 24
Finished	Apr 30 03:01:55 PM PDT 24
Peak memory	215056 kb
Host	smart-4eca6ef7-3e46-41a1-a715-5da49988de75
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943874048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3 943874048
Directory	/workspace/4.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.261040711
Short name	T746
Test name
Test status
Simulation time	47041270 ps
CPU time	0.73 seconds
Started	Apr 30 03:01:53 PM PDT 24
Finished	Apr 30 03:01:54 PM PDT 24
Peak memory	203504 kb
Host	smart-9a2be6ec-7284-4f25-a13c-fc5c62af1342
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261040711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.261040711
Directory	/workspace/4.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3920473443
Short name	T148
Test name
Test status
Simulation time	125921649 ps
CPU time	1.35 seconds
Started	Apr 30 03:01:50 PM PDT 24
Finished	Apr 30 03:01:52 PM PDT 24
Peak memory	215140 kb
Host	smart-8b42fde1-3482-45bd-8894-712bb9d4c3e2
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920473443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi _device_mem_partial_access.3920473443
Directory	/workspace/4.spi_device_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3662230191
Short name	T805
Test name
Test status
Simulation time	32083876 ps
CPU time	0.68 seconds
Started	Apr 30 03:01:46 PM PDT 24
Finished	Apr 30 03:01:48 PM PDT 24
Peak memory	203384 kb
Host	smart-9f2a9ce4-4520-4fdf-a1e8-87b4874a1743
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662230191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me m_walk.3662230191
Directory	/workspace/4.spi_device_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3430142804
Short name	T156
Test name
Test status
Simulation time	370968328 ps
CPU time	4.12 seconds
Started	Apr 30 03:01:43 PM PDT 24
Finished	Apr 30 03:01:48 PM PDT 24
Peak memory	215160 kb
Host	smart-0279f1b7-8dca-490e-8220-f7c7fc30d6dc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430142804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s pi_device_same_csr_outstanding.3430142804
Directory	/workspace/4.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3986582131
Short name	T135
Test name
Test status
Simulation time	620840751 ps
CPU time	5.33 seconds
Started	Apr 30 03:01:51 PM PDT 24
Finished	Apr 30 03:01:57 PM PDT 24
Peak memory	216228 kb
Host	smart-7916ff3e-4947-4ceb-8f23-c4c0ebaaf5ef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986582131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3 986582131
Directory	/workspace/4.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2201776908
Short name	T116
Test name
Test status
Simulation time	1599990796 ps
CPU time	8.72 seconds
Started	Apr 30 03:01:48 PM PDT 24
Finished	Apr 30 03:01:58 PM PDT 24
Peak memory	215172 kb
Host	smart-57e847ae-a683-44cd-971b-93256ae29ed4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201776908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device _tl_intg_err.2201776908
Directory	/workspace/4.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.1322077814
Short name	T796
Test name
Test status
Simulation time	13911689 ps
CPU time	0.74 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	203488 kb
Host	smart-687d4c77-3da0-43c4-9a0e-ddce74e2f09f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322077814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test. 1322077814
Directory	/workspace/40.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3747387324
Short name	T809
Test name
Test status
Simulation time	19746084 ps
CPU time	0.68 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:07 PM PDT 24
Peak memory	203544 kb
Host	smart-14b186dc-0f61-46ec-9ca8-b1062c007275
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747387324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test. 3747387324
Directory	/workspace/41.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.4286482337
Short name	T782
Test name
Test status
Simulation time	14119740 ps
CPU time	0.73 seconds
Started	Apr 30 03:02:09 PM PDT 24
Finished	Apr 30 03:02:10 PM PDT 24
Peak memory	203516 kb
Host	smart-873a990f-98ae-4915-8cc1-5e27b04f9acb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286482337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test. 4286482337
Directory	/workspace/42.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.3905847481
Short name	T734
Test name
Test status
Simulation time	17124646 ps
CPU time	0.74 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:04 PM PDT 24
Peak memory	203428 kb
Host	smart-7e64d716-a47f-490a-944e-3b2afefa8194
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905847481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test. 3905847481
Directory	/workspace/43.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.4213305180
Short name	T783
Test name
Test status
Simulation time	14636074 ps
CPU time	0.73 seconds
Started	Apr 30 03:02:11 PM PDT 24
Finished	Apr 30 03:02:13 PM PDT 24
Peak memory	203496 kb
Host	smart-a94f0649-3828-4a02-b938-7146968ac75d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213305180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test. 4213305180
Directory	/workspace/44.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.3584616486
Short name	T832
Test name
Test status
Simulation time	12519651 ps
CPU time	0.72 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	203488 kb
Host	smart-17a3ea11-dbd0-4b7b-b120-93cd18d5bb4b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584616486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test. 3584616486
Directory	/workspace/45.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.218271850
Short name	T778
Test name
Test status
Simulation time	44430440 ps
CPU time	0.71 seconds
Started	Apr 30 03:02:05 PM PDT 24
Finished	Apr 30 03:02:07 PM PDT 24
Peak memory	203436 kb
Host	smart-366c5e93-3b0b-4b08-aed1-c0a068d0d13a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218271850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.218271850
Directory	/workspace/46.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.4021537
Short name	T737
Test name
Test status
Simulation time	51302472 ps
CPU time	0.73 seconds
Started	Apr 30 03:02:06 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	203520 kb
Host	smart-4980cd1d-23d7-42c8-92de-35c7f46d3c9a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.4021537
Directory	/workspace/47.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.3725283935
Short name	T166
Test name
Test status
Simulation time	15675099 ps
CPU time	0.7 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	203372 kb
Host	smart-ab062806-c054-40a2-ab65-8a1396e2b454
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725283935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test. 3725283935
Directory	/workspace/48.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.292467194
Short name	T755
Test name
Test status
Simulation time	27862650 ps
CPU time	0.77 seconds
Started	Apr 30 03:02:09 PM PDT 24
Finished	Apr 30 03:02:10 PM PDT 24
Peak memory	203524 kb
Host	smart-ce9f49a1-6bb5-4792-afb1-fd882e1d546c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292467194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.292467194
Directory	/workspace/49.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2392698884
Short name	T759
Test name
Test status
Simulation time	77722421 ps
CPU time	2.84 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	216720 kb
Host	smart-7fe80db1-99e8-4818-9660-b8fc98bf0bfc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392698884 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2392698884
Directory	/workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.260700023
Short name	T823
Test name
Test status
Simulation time	243503290 ps
CPU time	2.39 seconds
Started	Apr 30 03:01:59 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	206884 kb
Host	smart-a352a2a4-d533-475d-9a48-a25086328116
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260700023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.260700023
Directory	/workspace/5.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.2774979372
Short name	T816
Test name
Test status
Simulation time	22288221 ps
CPU time	0.75 seconds
Started	Apr 30 03:02:01 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	203836 kb
Host	smart-ded9f045-47ca-4102-9e76-9f1fb76c0e61
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774979372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2 774979372
Directory	/workspace/5.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.615609733
Short name	T162
Test name
Test status
Simulation time	137073701 ps
CPU time	1.78 seconds
Started	Apr 30 03:01:54 PM PDT 24
Finished	Apr 30 03:01:56 PM PDT 24
Peak memory	215164 kb
Host	smart-2e883fb8-e3ed-4b6f-bbf6-dec67345b51d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615609733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp i_device_same_csr_outstanding.615609733
Directory	/workspace/5.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.447996909
Short name	T130
Test name
Test status
Simulation time	65227207 ps
CPU time	4.63 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:07 PM PDT 24
Peak memory	215152 kb
Host	smart-c92b2c35-d757-460e-a803-e27425a6f8bf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447996909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.447996909
Directory	/workspace/5.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2296567759
Short name	T837
Test name
Test status
Simulation time	1214204349 ps
CPU time	11.61 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:15 PM PDT 24
Peak memory	215256 kb
Host	smart-e6f5d702-9ad6-4d18-bd20-2f6b797f0c6c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296567759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device _tl_intg_err.2296567759
Directory	/workspace/5.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4204683218
Short name	T795
Test name
Test status
Simulation time	134915693 ps
CPU time	3.65 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:07 PM PDT 24
Peak memory	216456 kb
Host	smart-1e80ec61-453b-4b5b-91d8-82991a954a8b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204683218 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4204683218
Directory	/workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2682601442
Short name	T147
Test name
Test status
Simulation time	303505260 ps
CPU time	2.31 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:08 PM PDT 24
Peak memory	215168 kb
Host	smart-57172765-be31-45e9-bfee-2585a05c82a1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682601442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2 682601442
Directory	/workspace/6.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.3241253380
Short name	T770
Test name
Test status
Simulation time	27467161 ps
CPU time	0.73 seconds
Started	Apr 30 03:02:04 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	203836 kb
Host	smart-0af51d13-809f-48cb-bfd2-28189eed33b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241253380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3 241253380
Directory	/workspace/6.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2790873061
Short name	T758
Test name
Test status
Simulation time	64958361 ps
CPU time	1.95 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	215540 kb
Host	smart-f929f268-a991-49e8-8414-97715f29a897
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790873061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s pi_device_same_csr_outstanding.2790873061
Directory	/workspace/6.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3397557467
Short name	T814
Test name
Test status
Simulation time	1210908029 ps
CPU time	4.1 seconds
Started	Apr 30 03:01:58 PM PDT 24
Finished	Apr 30 03:02:02 PM PDT 24
Peak memory	215320 kb
Host	smart-22abb0b8-8939-4fea-9add-eeabe497806c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397557467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3 397557467
Directory	/workspace/6.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3633299798
Short name	T808
Test name
Test status
Simulation time	2009288717 ps
CPU time	14.84 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:18 PM PDT 24
Peak memory	215192 kb
Host	smart-060eb101-366c-4c02-b323-8f5ee060dfc5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633299798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device _tl_intg_err.3633299798
Directory	/workspace/6.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1149530647
Short name	T750
Test name
Test status
Simulation time	50069310 ps
CPU time	1.82 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:06 PM PDT 24
Peak memory	216168 kb
Host	smart-13b18da9-8043-409b-8f03-0315546c1ae9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149530647 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1149530647
Directory	/workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3303749835
Short name	T153
Test name
Test status
Simulation time	158636383 ps
CPU time	3.04 seconds
Started	Apr 30 03:02:00 PM PDT 24
Finished	Apr 30 03:02:03 PM PDT 24
Peak memory	215084 kb
Host	smart-bcc5848b-240e-4a85-845d-9e249ee64b64
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303749835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3 303749835
Directory	/workspace/7.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.758196757
Short name	T748
Test name
Test status
Simulation time	12315017 ps
CPU time	0.76 seconds
Started	Apr 30 03:01:57 PM PDT 24
Finished	Apr 30 03:01:59 PM PDT 24
Peak memory	203504 kb
Host	smart-c5822d24-b3eb-488d-a6e9-3081c2d5155a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758196757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.758196757
Directory	/workspace/7.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3580104116
Short name	T831
Test name
Test status
Simulation time	261968603 ps
CPU time	2.99 seconds
Started	Apr 30 03:02:01 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	215136 kb
Host	smart-4e2f7197-071f-4624-9b25-095c3bb9b745
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580104116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s pi_device_same_csr_outstanding.3580104116
Directory	/workspace/7.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.608447251
Short name	T797
Test name
Test status
Simulation time	207374151 ps
CPU time	12.74 seconds
Started	Apr 30 03:02:08 PM PDT 24
Finished	Apr 30 03:02:21 PM PDT 24
Peak memory	215124 kb
Host	smart-98fe5f5a-5e53-488c-979c-79f599ed6a05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608447251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_ tl_intg_err.608447251
Directory	/workspace/7.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2472476350
Short name	T749
Test name
Test status
Simulation time	32164522 ps
CPU time	1.93 seconds
Started	Apr 30 03:01:58 PM PDT 24
Finished	Apr 30 03:02:00 PM PDT 24
Peak memory	216132 kb
Host	smart-b00c963a-4cda-4eda-9101-6409f5e7fd4f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472476350 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2472476350
Directory	/workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3206930743
Short name	T843
Test name
Test status
Simulation time	26458314 ps
CPU time	1.73 seconds
Started	Apr 30 03:01:55 PM PDT 24
Finished	Apr 30 03:01:57 PM PDT 24
Peak memory	215112 kb
Host	smart-49a9b963-10b2-40fe-bd0a-3e422fe9f0c0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206930743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3 206930743
Directory	/workspace/8.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.3501172482
Short name	T733
Test name
Test status
Simulation time	19412683 ps
CPU time	0.77 seconds
Started	Apr 30 03:01:56 PM PDT 24
Finished	Apr 30 03:01:57 PM PDT 24
Peak memory	203548 kb
Host	smart-39279207-7c3a-4cd8-ae02-bd6575445567
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501172482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3 501172482
Directory	/workspace/8.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2317726888
Short name	T802
Test name
Test status
Simulation time	208985324 ps
CPU time	5.35 seconds
Started	Apr 30 03:01:59 PM PDT 24
Finished	Apr 30 03:02:05 PM PDT 24
Peak memory	215076 kb
Host	smart-af397478-ddb8-4cd6-9a05-0c8af5c49987
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317726888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s pi_device_same_csr_outstanding.2317726888
Directory	/workspace/8.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2433699095
Short name	T137
Test name
Test status
Simulation time	39499502 ps
CPU time	2.98 seconds
Started	Apr 30 03:02:00 PM PDT 24
Finished	Apr 30 03:02:03 PM PDT 24
Peak memory	216292 kb
Host	smart-596eb627-b645-49d2-8273-d1962e26bf3f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433699095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2 433699095
Directory	/workspace/8.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3857316395
Short name	T826
Test name
Test status
Simulation time	328904088 ps
CPU time	19.64 seconds
Started	Apr 30 03:02:02 PM PDT 24
Finished	Apr 30 03:02:22 PM PDT 24
Peak memory	215624 kb
Host	smart-81fe4335-19b7-4f78-96e3-4767a68a50a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857316395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device _tl_intg_err.3857316395
Directory	/workspace/8.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.621994055
Short name	T766
Test name
Test status
Simulation time	92489315 ps
CPU time	3.89 seconds
Started	Apr 30 03:01:57 PM PDT 24
Finished	Apr 30 03:02:01 PM PDT 24
Peak memory	217792 kb
Host	smart-c389b04c-4073-430a-93af-9823c179cf9b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621994055 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.621994055
Directory	/workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2442783782
Short name	T42
Test name
Test status
Simulation time	41660896 ps
CPU time	2.14 seconds
Started	Apr 30 03:01:57 PM PDT 24
Finished	Apr 30 03:02:00 PM PDT 24
Peak memory	215056 kb
Host	smart-021a4dce-b123-4b02-a7ee-4298f987a74b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442783782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2 442783782
Directory	/workspace/9.spi_device_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.1182397615
Short name	T840
Test name
Test status
Simulation time	44034451 ps
CPU time	0.7 seconds
Started	Apr 30 03:01:59 PM PDT 24
Finished	Apr 30 03:02:00 PM PDT 24
Peak memory	203516 kb
Host	smart-ac87c92b-3407-4034-b896-5a12197284e7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182397615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1 182397615
Directory	/workspace/9.spi_device_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.624527765
Short name	T160
Test name
Test status
Simulation time	422973304 ps
CPU time	4.27 seconds
Started	Apr 30 03:01:55 PM PDT 24
Finished	Apr 30 03:02:00 PM PDT 24
Peak memory	215120 kb
Host	smart-7c840885-ecf7-4ae2-9031-32d340ca057e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624527765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp i_device_same_csr_outstanding.624527765
Directory	/workspace/9.spi_device_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1585243271
Short name	T138
Test name
Test status
Simulation time	60741562 ps
CPU time	3.54 seconds
Started	Apr 30 03:02:07 PM PDT 24
Finished	Apr 30 03:02:12 PM PDT 24
Peak memory	215240 kb
Host	smart-5d529797-4572-4865-8cf3-df8355a01e04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585243271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1 585243271
Directory	/workspace/9.spi_device_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3096457780
Short name	T158
Test name
Test status
Simulation time	8122862549 ps
CPU time	16.15 seconds
Started	Apr 30 03:02:03 PM PDT 24
Finished	Apr 30 03:02:20 PM PDT 24
Peak memory	215384 kb
Host	smart-37084eba-dfdd-4ea1-8f14-358f808d3cb6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096457780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device _tl_intg_err.3096457780
Directory	/workspace/9.spi_device_tl_intg_err/latest

Test location	/workspace/coverage/default/0.spi_device_alert_test.2979240811
Short name	T495
Test name
Test status
Simulation time	67102204 ps
CPU time	0.73 seconds
Started	Apr 30 03:19:41 PM PDT 24
Finished	Apr 30 03:19:43 PM PDT 24
Peak memory	204824 kb
Host	smart-742b6ecf-cbe1-4360-bf32-7b270a89043b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979240811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2 979240811
Directory	/workspace/0.spi_device_alert_test/latest

Test location	/workspace/coverage/default/0.spi_device_csb_read.3271282974
Short name	T432
Test name
Test status
Simulation time	17578861 ps
CPU time	0.79 seconds
Started	Apr 30 03:19:31 PM PDT 24
Finished	Apr 30 03:19:33 PM PDT 24
Peak memory	206740 kb
Host	smart-2535192c-1851-42bd-8c9c-5bc7ee54dc79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271282974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3271282974
Directory	/workspace/0.spi_device_csb_read/latest

Test location	/workspace/coverage/default/0.spi_device_read_buffer_direct.799859299
Short name	T534
Test name
Test status
Simulation time	346981731 ps
CPU time	4.56 seconds
Started	Apr 30 03:19:44 PM PDT 24
Finished	Apr 30 03:19:49 PM PDT 24
Peak memory	222956 kb
Host	smart-9f5a5536-04a8-4167-986f-4cda6504e132
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=799859299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc t.799859299
Directory	/workspace/0.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_all.3842890600
Short name	T417
Test name
Test status
Simulation time	84752216842 ps
CPU time	25.28 seconds
Started	Apr 30 03:19:42 PM PDT 24
Finished	Apr 30 03:20:08 PM PDT 24
Peak memory	216528 kb
Host	smart-75d00e02-4ac0-4183-abe0-5e8d6150c8f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842890600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3842890600
Directory	/workspace/0.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_read_hw_reg.241267518
Short name	T461
Test name
Test status
Simulation time	2173590199 ps
CPU time	8.07 seconds
Started	Apr 30 03:19:44 PM PDT 24
Finished	Apr 30 03:19:53 PM PDT 24
Peak memory	216252 kb
Host	smart-cf3301a8-56ea-4c50-9ab7-dc8b2124927a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241267518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.241267518
Directory	/workspace/0.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_rw.3662046157
Short name	T524
Test name
Test status
Simulation time	248410650 ps
CPU time	2.07 seconds
Started	Apr 30 03:19:42 PM PDT 24
Finished	Apr 30 03:19:45 PM PDT 24
Peak memory	216236 kb
Host	smart-cea73cf6-5536-4cd6-a849-b84fad3a0187
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662046157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3662046157
Directory	/workspace/0.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/0.spi_device_tpm_sts_read.3218021244
Short name	T606
Test name
Test status
Simulation time	455079440 ps
CPU time	0.82 seconds
Started	Apr 30 03:19:45 PM PDT 24
Finished	Apr 30 03:19:46 PM PDT 24
Peak memory	205836 kb
Host	smart-1ad04100-3eb5-4119-be81-dfc4f87df274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218021244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3218021244
Directory	/workspace/0.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/0.spi_device_upload.2944682749
Short name	T268
Test name
Test status
Simulation time	131476919 ps
CPU time	2.56 seconds
Started	Apr 30 03:19:39 PM PDT 24
Finished	Apr 30 03:19:42 PM PDT 24
Peak memory	222660 kb
Host	smart-0c3ce864-b9cf-499d-b11b-2a0e24b14bf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2944682749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2944682749
Directory	/workspace/0.spi_device_upload/latest

Test location	/workspace/coverage/default/1.spi_device_alert_test.3090056680
Short name	T693
Test name
Test status
Simulation time	12092612 ps
CPU time	0.67 seconds
Started	Apr 30 03:19:42 PM PDT 24
Finished	Apr 30 03:19:43 PM PDT 24
Peak memory	205380 kb
Host	smart-a8161b80-a277-45a2-ae11-cda6c3d1a455
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090056680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3 090056680
Directory	/workspace/1.spi_device_alert_test/latest

Test location	/workspace/coverage/default/1.spi_device_csb_read.765417553
Short name	T539
Test name
Test status
Simulation time	12601375 ps
CPU time	0.74 seconds
Started	Apr 30 03:19:41 PM PDT 24
Finished	Apr 30 03:19:43 PM PDT 24
Peak memory	205964 kb
Host	smart-ffe58b85-e1da-4dc7-bd19-65ad73378286
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=765417553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.765417553
Directory	/workspace/1.spi_device_csb_read/latest

Test location	/workspace/coverage/default/1.spi_device_flash_mode.4205645113
Short name	T374
Test name
Test status
Simulation time	22701613708 ps
CPU time	98.5 seconds
Started	Apr 30 03:19:41 PM PDT 24
Finished	Apr 30 03:21:20 PM PDT 24
Peak memory	238932 kb
Host	smart-d43a3078-ec62-4842-844a-7d739768cb7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205645113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4205645113
Directory	/workspace/1.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/1.spi_device_pass_cmd_filtering.3614894615
Short name	T703
Test name
Test status
Simulation time	773977934 ps
CPU time	7.21 seconds
Started	Apr 30 03:19:45 PM PDT 24
Finished	Apr 30 03:19:53 PM PDT 24
Peak memory	224388 kb
Host	smart-570aa144-314e-4780-983a-9becdaede4a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614894615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3614894615
Directory	/workspace/1.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/1.spi_device_read_buffer_direct.760213247
Short name	T724
Test name
Test status
Simulation time	1846406559 ps
CPU time	7.39 seconds
Started	Apr 30 03:19:43 PM PDT 24
Finished	Apr 30 03:19:51 PM PDT 24
Peak memory	221856 kb
Host	smart-5a465927-17db-4a88-8911-898894dbfde8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=760213247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc t.760213247
Directory	/workspace/1.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/1.spi_device_sec_cm.1757003915
Short name	T50
Test name
Test status
Simulation time	246003476 ps
CPU time	1.08 seconds
Started	Apr 30 03:19:44 PM PDT 24
Finished	Apr 30 03:19:46 PM PDT 24
Peak memory	235112 kb
Host	smart-384b908f-8137-42ef-a873-b1bfcdb15d61
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757003915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1757003915
Directory	/workspace/1.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.27393279
Short name	T526
Test name
Test status
Simulation time	8604034770 ps
CPU time	10.39 seconds
Started	Apr 30 03:19:42 PM PDT 24
Finished	Apr 30 03:19:54 PM PDT 24
Peak memory	216376 kb
Host	smart-aa25a8e6-271d-450b-9028-2ac7df4aac42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27393279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.27393279
Directory	/workspace/1.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_rw.1971417789
Short name	T24
Test name
Test status
Simulation time	476609965 ps
CPU time	3.18 seconds
Started	Apr 30 03:19:41 PM PDT 24
Finished	Apr 30 03:19:45 PM PDT 24
Peak memory	216192 kb
Host	smart-3bbf1814-64c5-4a49-903f-e4f97fa3cf9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971417789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1971417789
Directory	/workspace/1.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/1.spi_device_tpm_sts_read.1574760342
Short name	T705
Test name
Test status
Simulation time	24324828 ps
CPU time	0.76 seconds
Started	Apr 30 03:19:45 PM PDT 24
Finished	Apr 30 03:19:47 PM PDT 24
Peak memory	205756 kb
Host	smart-5b4acbef-4a08-4261-81cf-de86ba510a6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574760342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1574760342
Directory	/workspace/1.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/1.spi_device_upload.4056450565
Short name	T57
Test name
Test status
Simulation time	611092903 ps
CPU time	4.49 seconds
Started	Apr 30 03:19:41 PM PDT 24
Finished	Apr 30 03:19:46 PM PDT 24
Peak memory	216240 kb
Host	smart-9e47e9e0-b1a3-4e31-a003-1aa30758a09f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056450565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4056450565
Directory	/workspace/1.spi_device_upload/latest

Test location	/workspace/coverage/default/10.spi_device_alert_test.3065810922
Short name	T612
Test name
Test status
Simulation time	21270646 ps
CPU time	0.71 seconds
Started	Apr 30 03:20:22 PM PDT 24
Finished	Apr 30 03:20:23 PM PDT 24
Peak memory	204816 kb
Host	smart-22972e67-f020-4383-bb5a-5771d1f7c443
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065810922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test. 3065810922
Directory	/workspace/10.spi_device_alert_test/latest

Test location	/workspace/coverage/default/10.spi_device_cfg_cmd.1294999879
Short name	T271
Test name
Test status
Simulation time	137591817 ps
CPU time	4.21 seconds
Started	Apr 30 03:20:20 PM PDT 24
Finished	Apr 30 03:20:25 PM PDT 24
Peak memory	224160 kb
Host	smart-6df8a9ed-fe51-429e-9e8f-69fc0210ce62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294999879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1294999879
Directory	/workspace/10.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/10.spi_device_csb_read.754318927
Short name	T446
Test name
Test status
Simulation time	88805215 ps
CPU time	0.79 seconds
Started	Apr 30 03:20:14 PM PDT 24
Finished	Apr 30 03:20:16 PM PDT 24
Peak memory	206660 kb
Host	smart-d069787f-64c7-4915-b189-3bb9c57f6d2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754318927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.754318927
Directory	/workspace/10.spi_device_csb_read/latest

Test location	/workspace/coverage/default/10.spi_device_flash_mode.2265832480
Short name	T350
Test name
Test status
Simulation time	10023273299 ps
CPU time	127.01 seconds
Started	Apr 30 03:20:18 PM PDT 24
Finished	Apr 30 03:22:26 PM PDT 24
Peak memory	251776 kb
Host	smart-0c454b50-746d-4795-a718-ad13b9d1211b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265832480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2265832480
Directory	/workspace/10.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/10.spi_device_intercept.2152867577
Short name	T7
Test name
Test status
Simulation time	1459760236 ps
CPU time	9.53 seconds
Started	Apr 30 03:20:12 PM PDT 24
Finished	Apr 30 03:20:22 PM PDT 24
Peak memory	219088 kb
Host	smart-48d3a2f8-5733-4704-9d60-5774c3f304a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2152867577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2152867577
Directory	/workspace/10.spi_device_intercept/latest

Test location	/workspace/coverage/default/10.spi_device_mailbox.3260487451
Short name	T53
Test name
Test status
Simulation time	31727944530 ps
CPU time	52.97 seconds
Started	Apr 30 03:20:11 PM PDT 24
Finished	Apr 30 03:21:05 PM PDT 24
Peak memory	235196 kb
Host	smart-63bc8e5f-d946-4f5a-a03b-ac27c79a0cf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260487451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3260487451
Directory	/workspace/10.spi_device_mailbox/latest

Test location	/workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2366077097
Short name	T338
Test name
Test status
Simulation time	8455432474 ps
CPU time	12.48 seconds
Started	Apr 30 03:20:14 PM PDT 24
Finished	Apr 30 03:20:27 PM PDT 24
Peak memory	223212 kb
Host	smart-d366e57d-6f2a-478e-9cfa-c9adbdcfc7f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366077097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa p.2366077097
Directory	/workspace/10.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/10.spi_device_pass_cmd_filtering.513965481
Short name	T656
Test name
Test status
Simulation time	5277613568 ps
CPU time	11.11 seconds
Started	Apr 30 03:20:12 PM PDT 24
Finished	Apr 30 03:20:23 PM PDT 24
Peak memory	224472 kb
Host	smart-b890f5e4-3afb-439b-8e8f-385fec885097
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513965481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.513965481
Directory	/workspace/10.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/10.spi_device_read_buffer_direct.739248703
Short name	T499
Test name
Test status
Simulation time	1703306063 ps
CPU time	17.45 seconds
Started	Apr 30 03:20:22 PM PDT 24
Finished	Apr 30 03:20:40 PM PDT 24
Peak memory	221648 kb
Host	smart-8ff7f39b-959f-4eca-a91e-e984b0fa5e2b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=739248703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire ct.739248703
Directory	/workspace/10.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.478262818
Short name	T436
Test name
Test status
Simulation time	4270273289 ps
CPU time	5.97 seconds
Started	Apr 30 03:20:11 PM PDT 24
Finished	Apr 30 03:20:18 PM PDT 24
Peak memory	216312 kb
Host	smart-1478bb02-eae0-45c9-a485-20fbfd3642d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478262818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.478262818
Directory	/workspace/10.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_rw.92512188
Short name	T419
Test name
Test status
Simulation time	126620291 ps
CPU time	1 seconds
Started	Apr 30 03:20:11 PM PDT 24
Finished	Apr 30 03:20:13 PM PDT 24
Peak memory	207152 kb
Host	smart-241bb0bc-7bea-4c48-9302-d903b6d439d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92512188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.92512188
Directory	/workspace/10.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/10.spi_device_tpm_sts_read.1961673629
Short name	T629
Test name
Test status
Simulation time	40018330 ps
CPU time	0.93 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:14 PM PDT 24
Peak memory	206720 kb
Host	smart-62c77733-3eab-4b63-b842-77ddf0b5796f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1961673629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1961673629
Directory	/workspace/10.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/11.spi_device_alert_test.395647815
Short name	T453
Test name
Test status
Simulation time	95143110 ps
CPU time	0.75 seconds
Started	Apr 30 03:20:25 PM PDT 24
Finished	Apr 30 03:20:28 PM PDT 24
Peak memory	205364 kb
Host	smart-962d8cf2-e43d-4bbd-85ab-363ce9698ebe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395647815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.395647815
Directory	/workspace/11.spi_device_alert_test/latest

Test location	/workspace/coverage/default/11.spi_device_cfg_cmd.1869152217
Short name	T260
Test name
Test status
Simulation time	164050403 ps
CPU time	3.31 seconds
Started	Apr 30 03:20:21 PM PDT 24
Finished	Apr 30 03:20:25 PM PDT 24
Peak memory	224432 kb
Host	smart-af77bf1e-6a9e-4eed-a74c-52891a351e3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869152217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1869152217
Directory	/workspace/11.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/11.spi_device_csb_read.1916602350
Short name	T581
Test name
Test status
Simulation time	21363053 ps
CPU time	0.86 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:25 PM PDT 24
Peak memory	206988 kb
Host	smart-ee84e751-4968-4140-91e8-a7aec49806cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1916602350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1916602350
Directory	/workspace/11.spi_device_csb_read/latest

Test location	/workspace/coverage/default/11.spi_device_flash_mode.1316739973
Short name	T362
Test name
Test status
Simulation time	7585644655 ps
CPU time	29.28 seconds
Started	Apr 30 03:20:25 PM PDT 24
Finished	Apr 30 03:20:56 PM PDT 24
Peak memory	232632 kb
Host	smart-e1075fe1-aab9-4684-81bf-797028ee2bc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316739973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1316739973
Directory	/workspace/11.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/11.spi_device_mailbox.933892359
Short name	T713
Test name
Test status
Simulation time	5579127580 ps
CPU time	11.54 seconds
Started	Apr 30 03:20:24 PM PDT 24
Finished	Apr 30 03:20:37 PM PDT 24
Peak memory	232056 kb
Host	smart-b558ad27-f58d-41bc-9ab2-0ad8d665af71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933892359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.933892359
Directory	/workspace/11.spi_device_mailbox/latest

Test location	/workspace/coverage/default/11.spi_device_pass_cmd_filtering.2984735536
Short name	T275
Test name
Test status
Simulation time	10774443118 ps
CPU time	29.19 seconds
Started	Apr 30 03:20:22 PM PDT 24
Finished	Apr 30 03:20:53 PM PDT 24
Peak memory	224380 kb
Host	smart-0e2f5841-c52f-44f6-9258-9122f14756e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984735536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2984735536
Directory	/workspace/11.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/11.spi_device_read_buffer_direct.812324238
Short name	T531
Test name
Test status
Simulation time	14762638143 ps
CPU time	10.03 seconds
Started	Apr 30 03:20:22 PM PDT 24
Finished	Apr 30 03:20:33 PM PDT 24
Peak memory	220416 kb
Host	smart-c179f9d4-c3f5-4cee-8d80-0a1746ad4167
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=812324238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire ct.812324238
Directory	/workspace/11.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_all.1927128134
Short name	T624
Test name
Test status
Simulation time	4131489694 ps
CPU time	24.1 seconds
Started	Apr 30 03:20:19 PM PDT 24
Finished	Apr 30 03:20:44 PM PDT 24
Peak memory	216284 kb
Host	smart-ceead216-cb44-46b7-9701-42682b1fb21e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927128134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1927128134
Directory	/workspace/11.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2321838148
Short name	T602
Test name
Test status
Simulation time	835236937 ps
CPU time	4.68 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:30 PM PDT 24
Peak memory	216220 kb
Host	smart-cb3d88c3-88cc-475c-911e-3f3028ba3665
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321838148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2321838148
Directory	/workspace/11.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_rw.3885562893
Short name	T412
Test name
Test status
Simulation time	74118466 ps
CPU time	1.14 seconds
Started	Apr 30 03:20:25 PM PDT 24
Finished	Apr 30 03:20:28 PM PDT 24
Peak memory	207872 kb
Host	smart-33e3fe5f-1902-41c5-8fdb-18d083930293
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885562893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3885562893
Directory	/workspace/11.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/11.spi_device_tpm_sts_read.3340254344
Short name	T625
Test name
Test status
Simulation time	152199774 ps
CPU time	0.9 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:25 PM PDT 24
Peak memory	206780 kb
Host	smart-8676ff1e-5b66-4b4a-af32-f5265dd717d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340254344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3340254344
Directory	/workspace/11.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/12.spi_device_alert_test.2167851857
Short name	T663
Test name
Test status
Simulation time	31336415 ps
CPU time	0.77 seconds
Started	Apr 30 03:20:25 PM PDT 24
Finished	Apr 30 03:20:27 PM PDT 24
Peak memory	204836 kb
Host	smart-cd1c971c-b721-4f30-81b7-a6255fc5eea0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167851857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test. 2167851857
Directory	/workspace/12.spi_device_alert_test/latest

Test location	/workspace/coverage/default/12.spi_device_csb_read.2759592616
Short name	T25
Test name
Test status
Simulation time	23961672 ps
CPU time	0.77 seconds
Started	Apr 30 03:20:20 PM PDT 24
Finished	Apr 30 03:20:21 PM PDT 24
Peak memory	206984 kb
Host	smart-6b13cfea-d703-4984-996e-258216715206
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759592616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2759592616
Directory	/workspace/12.spi_device_csb_read/latest

Test location	/workspace/coverage/default/12.spi_device_flash_mode.3051353646
Short name	T349
Test name
Test status
Simulation time	6059359450 ps
CPU time	27.75 seconds
Started	Apr 30 03:20:22 PM PDT 24
Finished	Apr 30 03:20:50 PM PDT 24
Peak memory	250184 kb
Host	smart-b66a7c27-1997-426a-852e-68aa961dbdb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051353646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3051353646
Directory	/workspace/12.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/12.spi_device_mailbox.1185132717
Short name	T464
Test name
Test status
Simulation time	35800279 ps
CPU time	2.42 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:27 PM PDT 24
Peak memory	221560 kb
Host	smart-6954bf8c-5391-4858-84ce-8dd5122f2801
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185132717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1185132717
Directory	/workspace/12.spi_device_mailbox/latest

Test location	/workspace/coverage/default/12.spi_device_pass_cmd_filtering.2055356384
Short name	T240
Test name
Test status
Simulation time	10836864182 ps
CPU time	14.1 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:39 PM PDT 24
Peak memory	236100 kb
Host	smart-fdc70e43-797f-40c0-a578-c919d9c6b699
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055356384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2055356384
Directory	/workspace/12.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/12.spi_device_read_buffer_direct.4281189749
Short name	T565
Test name
Test status
Simulation time	374925468 ps
CPU time	3.75 seconds
Started	Apr 30 03:20:21 PM PDT 24
Finished	Apr 30 03:20:25 PM PDT 24
Peak memory	222840 kb
Host	smart-09f19629-6e33-4144-b4a4-f1cd1c380e03
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4281189749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir ect.4281189749
Directory	/workspace/12.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/12.spi_device_stress_all.3528796072
Short name	T451
Test name
Test status
Simulation time	93710916 ps
CPU time	0.99 seconds
Started	Apr 30 03:20:25 PM PDT 24
Finished	Apr 30 03:20:28 PM PDT 24
Peak memory	207192 kb
Host	smart-bb0859ae-8256-4353-9493-d026d1720b72
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528796072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre ss_all.3528796072
Directory	/workspace/12.spi_device_stress_all/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_all.26256372
Short name	T105
Test name
Test status
Simulation time	1777646410 ps
CPU time	28.76 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:53 PM PDT 24
Peak memory	216536 kb
Host	smart-b9bd320f-1e83-40f0-b5a4-eb4460104e1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26256372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.26256372
Directory	/workspace/12.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.113613727
Short name	T587
Test name
Test status
Simulation time	18689780303 ps
CPU time	28.3 seconds
Started	Apr 30 03:20:24 PM PDT 24
Finished	Apr 30 03:20:55 PM PDT 24
Peak memory	216212 kb
Host	smart-4f86fd6d-1d84-496d-8c04-72618bab3091
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113613727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.113613727
Directory	/workspace/12.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_rw.830550686
Short name	T655
Test name
Test status
Simulation time	60202842 ps
CPU time	1.53 seconds
Started	Apr 30 03:20:24 PM PDT 24
Finished	Apr 30 03:20:28 PM PDT 24
Peak memory	216152 kb
Host	smart-8202db35-dca7-4382-8d49-31f0f688fcce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830550686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.830550686
Directory	/workspace/12.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/12.spi_device_tpm_sts_read.114597785
Short name	T572
Test name
Test status
Simulation time	25140602 ps
CPU time	0.79 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:25 PM PDT 24
Peak memory	205764 kb
Host	smart-c01f3863-49e5-4969-b0c1-73983c2483dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114597785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.114597785
Directory	/workspace/12.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/13.spi_device_alert_test.77413992
Short name	T654
Test name
Test status
Simulation time	27347561 ps
CPU time	0.76 seconds
Started	Apr 30 03:20:25 PM PDT 24
Finished	Apr 30 03:20:27 PM PDT 24
Peak memory	205688 kb
Host	smart-672c4ef5-7b39-42e4-8f34-3a5e17d8be71
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77413992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.77413992
Directory	/workspace/13.spi_device_alert_test/latest

Test location	/workspace/coverage/default/13.spi_device_csb_read.1519358542
Short name	T632
Test name
Test status
Simulation time	42275401 ps
CPU time	0.77 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:26 PM PDT 24
Peak memory	206624 kb
Host	smart-c7b7ccc3-0d2d-4daa-8964-ba88ba434d14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519358542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1519358542
Directory	/workspace/13.spi_device_csb_read/latest

Test location	/workspace/coverage/default/13.spi_device_flash_mode.2100858381
Short name	T370
Test name
Test status
Simulation time	10616795488 ps
CPU time	82.17 seconds
Started	Apr 30 03:20:21 PM PDT 24
Finished	Apr 30 03:21:44 PM PDT 24
Peak memory	240852 kb
Host	smart-7d463111-86fe-4a1a-989f-d928080a01d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100858381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2100858381
Directory	/workspace/13.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/13.spi_device_mailbox.3060643507
Short name	T185
Test name
Test status
Simulation time	645008171 ps
CPU time	5.43 seconds
Started	Apr 30 03:20:24 PM PDT 24
Finished	Apr 30 03:20:31 PM PDT 24
Peak memory	221492 kb
Host	smart-f22a9915-7409-47f0-a4bf-ae7ae5dcffd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060643507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3060643507
Directory	/workspace/13.spi_device_mailbox/latest

Test location	/workspace/coverage/default/13.spi_device_pass_cmd_filtering.3744379141
Short name	T249
Test name
Test status
Simulation time	18068432385 ps
CPU time	13.95 seconds
Started	Apr 30 03:20:24 PM PDT 24
Finished	Apr 30 03:20:40 PM PDT 24
Peak memory	232688 kb
Host	smart-17a68f32-fbde-43e0-bb1a-958f2d748db8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744379141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3744379141
Directory	/workspace/13.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/13.spi_device_read_buffer_direct.3344842611
Short name	T562
Test name
Test status
Simulation time	1367208793 ps
CPU time	7.12 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:32 PM PDT 24
Peak memory	219364 kb
Host	smart-b43e2754-528b-41c4-94ea-8cac27950de3
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3344842611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir ect.3344842611
Directory	/workspace/13.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/13.spi_device_stress_all.897071861
Short name	T165
Test name
Test status
Simulation time	272939645 ps
CPU time	1.24 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:26 PM PDT 24
Peak memory	207176 kb
Host	smart-b73c9fbb-94e6-469a-bd67-b0761b27151a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897071861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres s_all.897071861
Directory	/workspace/13.spi_device_stress_all/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_all.2361609862
Short name	T641
Test name
Test status
Simulation time	4021230943 ps
CPU time	19.78 seconds
Started	Apr 30 03:20:22 PM PDT 24
Finished	Apr 30 03:20:44 PM PDT 24
Peak memory	216364 kb
Host	smart-64c5cacd-dbb2-4665-b97b-4e5682842fa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361609862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2361609862
Directory	/workspace/13.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3930260901
Short name	T561
Test name
Test status
Simulation time	4829720362 ps
CPU time	11.07 seconds
Started	Apr 30 03:20:21 PM PDT 24
Finished	Apr 30 03:20:33 PM PDT 24
Peak memory	216364 kb
Host	smart-74b5f24e-4e3e-4264-91ea-6b3ad6a5a381
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930260901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3930260901
Directory	/workspace/13.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_rw.1076792721
Short name	T423
Test name
Test status
Simulation time	17618594 ps
CPU time	0.78 seconds
Started	Apr 30 03:20:24 PM PDT 24
Finished	Apr 30 03:20:27 PM PDT 24
Peak memory	205804 kb
Host	smart-5ec55e9d-db9d-45f3-bc70-2c4bacd9fbed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1076792721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1076792721
Directory	/workspace/13.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/13.spi_device_tpm_sts_read.3170408188
Short name	T109
Test name
Test status
Simulation time	113341922 ps
CPU time	1 seconds
Started	Apr 30 03:20:21 PM PDT 24
Finished	Apr 30 03:20:23 PM PDT 24
Peak memory	206764 kb
Host	smart-8de23115-9cb4-4da5-bcb8-fcf6ce065135
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170408188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3170408188
Directory	/workspace/13.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/13.spi_device_upload.2716391232
Short name	T297
Test name
Test status
Simulation time	1104127180 ps
CPU time	8.99 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:34 PM PDT 24
Peak memory	235760 kb
Host	smart-d3e76404-4a6b-47e7-bb77-b76e48e4b8e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716391232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2716391232
Directory	/workspace/13.spi_device_upload/latest

Test location	/workspace/coverage/default/14.spi_device_alert_test.2494691592
Short name	T677
Test name
Test status
Simulation time	15770486 ps
CPU time	0.75 seconds
Started	Apr 30 03:20:26 PM PDT 24
Finished	Apr 30 03:20:29 PM PDT 24
Peak memory	205308 kb
Host	smart-b3122b81-28c9-4036-8fb6-8fa9ab1ab596
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494691592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test. 2494691592
Directory	/workspace/14.spi_device_alert_test/latest

Test location	/workspace/coverage/default/14.spi_device_cfg_cmd.3606060090
Short name	T575
Test name
Test status
Simulation time	15386660759 ps
CPU time	20.19 seconds
Started	Apr 30 03:20:27 PM PDT 24
Finished	Apr 30 03:20:48 PM PDT 24
Peak memory	224192 kb
Host	smart-6f9f6e2b-8a8f-489e-9adf-b1107ae0f03a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606060090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3606060090
Directory	/workspace/14.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/14.spi_device_csb_read.1193924891
Short name	T633
Test name
Test status
Simulation time	88244649 ps
CPU time	0.82 seconds
Started	Apr 30 03:20:24 PM PDT 24
Finished	Apr 30 03:20:27 PM PDT 24
Peak memory	206648 kb
Host	smart-6bf0f041-660f-4c03-9ab0-346e48936e6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1193924891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1193924891
Directory	/workspace/14.spi_device_csb_read/latest

Test location	/workspace/coverage/default/14.spi_device_mailbox.868815061
Short name	T615
Test name
Test status
Simulation time	1674415267 ps
CPU time	8.88 seconds
Started	Apr 30 03:20:25 PM PDT 24
Finished	Apr 30 03:20:36 PM PDT 24
Peak memory	223004 kb
Host	smart-c0acfe7c-c208-4183-9735-ab63b7917976
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868815061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.868815061
Directory	/workspace/14.spi_device_mailbox/latest

Test location	/workspace/coverage/default/14.spi_device_read_buffer_direct.3546901638
Short name	T438
Test name
Test status
Simulation time	2941388628 ps
CPU time	14.52 seconds
Started	Apr 30 03:20:26 PM PDT 24
Finished	Apr 30 03:20:42 PM PDT 24
Peak memory	221952 kb
Host	smart-a515eddd-1d97-4e62-ab53-8be0071b6b76
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3546901638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir ect.3546901638
Directory	/workspace/14.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/14.spi_device_stress_all.3076207416
Short name	T358
Test name
Test status
Simulation time	131080851 ps
CPU time	0.9 seconds
Started	Apr 30 03:20:21 PM PDT 24
Finished	Apr 30 03:20:23 PM PDT 24
Peak memory	206912 kb
Host	smart-c42aa7c1-089b-4a94-8b06-4b8620c43c09
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076207416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre ss_all.3076207416
Directory	/workspace/14.spi_device_stress_all/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3177063488
Short name	T508
Test name
Test status
Simulation time	114669748 ps
CPU time	1.52 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:27 PM PDT 24
Peak memory	207744 kb
Host	smart-cdbd0e39-97fc-4f90-9591-73bdbf930686
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177063488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3177063488
Directory	/workspace/14.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_rw.969664755
Short name	T418
Test name
Test status
Simulation time	704494104 ps
CPU time	7.57 seconds
Started	Apr 30 03:20:23 PM PDT 24
Finished	Apr 30 03:20:32 PM PDT 24
Peak memory	216256 kb
Host	smart-d73898a2-a635-440f-a624-68e91257c9ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=969664755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.969664755
Directory	/workspace/14.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/14.spi_device_tpm_sts_read.576001462
Short name	T613
Test name
Test status
Simulation time	136022598 ps
CPU time	0.87 seconds
Started	Apr 30 03:20:24 PM PDT 24
Finished	Apr 30 03:20:27 PM PDT 24
Peak memory	206768 kb
Host	smart-307db99f-6364-411f-8290-4ea8dde1e78a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576001462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.576001462
Directory	/workspace/14.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/14.spi_device_upload.2309191306
Short name	T199
Test name
Test status
Simulation time	832119246 ps
CPU time	6.36 seconds
Started	Apr 30 03:20:27 PM PDT 24
Finished	Apr 30 03:20:35 PM PDT 24
Peak memory	219552 kb
Host	smart-f4536ad3-0cfd-4aa9-b9ef-7857467fb8b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2309191306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2309191306
Directory	/workspace/14.spi_device_upload/latest

Test location	/workspace/coverage/default/15.spi_device_alert_test.2689752634
Short name	T542
Test name
Test status
Simulation time	11337401 ps
CPU time	0.71 seconds
Started	Apr 30 03:20:35 PM PDT 24
Finished	Apr 30 03:20:37 PM PDT 24
Peak memory	205336 kb
Host	smart-b130c6a7-f323-475c-9547-a1e88694e136
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689752634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test. 2689752634
Directory	/workspace/15.spi_device_alert_test/latest

Test location	/workspace/coverage/default/15.spi_device_cfg_cmd.4221489595
Short name	T501
Test name
Test status
Simulation time	780190443 ps
CPU time	5.55 seconds
Started	Apr 30 03:20:31 PM PDT 24
Finished	Apr 30 03:20:37 PM PDT 24
Peak memory	222476 kb
Host	smart-e2f31087-b3a2-4470-8ed0-1e026ab7bd98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4221489595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4221489595
Directory	/workspace/15.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/15.spi_device_csb_read.2660587592
Short name	T468
Test name
Test status
Simulation time	13368707 ps
CPU time	0.75 seconds
Started	Apr 30 03:20:31 PM PDT 24
Finished	Apr 30 03:20:32 PM PDT 24
Peak memory	205636 kb
Host	smart-04f3eca8-3668-474a-b657-ad0059a906e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660587592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2660587592
Directory	/workspace/15.spi_device_csb_read/latest

Test location	/workspace/coverage/default/15.spi_device_pass_cmd_filtering.3157915977
Short name	T295
Test name
Test status
Simulation time	2436532585 ps
CPU time	9.72 seconds
Started	Apr 30 03:20:32 PM PDT 24
Finished	Apr 30 03:20:45 PM PDT 24
Peak memory	222792 kb
Host	smart-0d319986-8ccc-4a19-b341-91e81154711b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157915977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3157915977
Directory	/workspace/15.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/15.spi_device_read_buffer_direct.354027443
Short name	T697
Test name
Test status
Simulation time	9069567554 ps
CPU time	15.7 seconds
Started	Apr 30 03:20:33 PM PDT 24
Finished	Apr 30 03:20:51 PM PDT 24
Peak memory	221560 kb
Host	smart-f4d18007-798a-4976-bbcc-726ca1f21627
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=354027443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire ct.354027443
Directory	/workspace/15.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_all.3986725087
Short name	T390
Test name
Test status
Simulation time	6132235573 ps
CPU time	32.03 seconds
Started	Apr 30 03:20:30 PM PDT 24
Finished	Apr 30 03:21:03 PM PDT 24
Peak memory	216284 kb
Host	smart-41bf55fb-eb00-49c1-babb-5a99d8ec1529
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986725087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3986725087
Directory	/workspace/15.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.96363797
Short name	T510
Test name
Test status
Simulation time	1703482093 ps
CPU time	8.75 seconds
Started	Apr 30 03:20:35 PM PDT 24
Finished	Apr 30 03:20:45 PM PDT 24
Peak memory	216220 kb
Host	smart-f48ca03b-c54f-41e1-bad4-6bed10225067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96363797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.96363797
Directory	/workspace/15.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_rw.1785734764
Short name	T523
Test name
Test status
Simulation time	753294401 ps
CPU time	6.92 seconds
Started	Apr 30 03:20:33 PM PDT 24
Finished	Apr 30 03:20:43 PM PDT 24
Peak memory	216216 kb
Host	smart-df79895f-5270-4457-ac07-b44931b2c159
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785734764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1785734764
Directory	/workspace/15.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/15.spi_device_tpm_sts_read.1819159225
Short name	T695
Test name
Test status
Simulation time	61560031 ps
CPU time	0.84 seconds
Started	Apr 30 03:20:31 PM PDT 24
Finished	Apr 30 03:20:34 PM PDT 24
Peak memory	205788 kb
Host	smart-baf4d9f9-ed9c-4119-b755-f5786c944636
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1819159225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1819159225
Directory	/workspace/15.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/16.spi_device_csb_read.546979169
Short name	T529
Test name
Test status
Simulation time	25138436 ps
CPU time	0.78 seconds
Started	Apr 30 03:20:32 PM PDT 24
Finished	Apr 30 03:20:36 PM PDT 24
Peak memory	206620 kb
Host	smart-3be3e1bf-7cdb-4d11-92f0-ef330956eddc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=546979169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.546979169
Directory	/workspace/16.spi_device_csb_read/latest

Test location	/workspace/coverage/default/16.spi_device_mailbox.759293645
Short name	T192
Test name
Test status
Simulation time	5057785036 ps
CPU time	58.28 seconds
Started	Apr 30 03:20:30 PM PDT 24
Finished	Apr 30 03:21:29 PM PDT 24
Peak memory	230776 kb
Host	smart-e0634039-b890-4bab-a6ea-d75bd395cc00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759293645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.759293645
Directory	/workspace/16.spi_device_mailbox/latest

Test location	/workspace/coverage/default/16.spi_device_pass_cmd_filtering.489709992
Short name	T266
Test name
Test status
Simulation time	1186496120 ps
CPU time	8.59 seconds
Started	Apr 30 03:20:32 PM PDT 24
Finished	Apr 30 03:20:43 PM PDT 24
Peak memory	233348 kb
Host	smart-e01dbe29-1045-4068-b660-596497621453
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489709992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.489709992
Directory	/workspace/16.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/16.spi_device_read_buffer_direct.1869501422
Short name	T127
Test name
Test status
Simulation time	300363479 ps
CPU time	5.72 seconds
Started	Apr 30 03:20:32 PM PDT 24
Finished	Apr 30 03:20:40 PM PDT 24
Peak memory	220328 kb
Host	smart-df805523-4e14-414e-b9d2-1d99d9e1ae37
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1869501422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir ect.1869501422
Directory	/workspace/16.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_all.3127096870
Short name	T411
Test name
Test status
Simulation time	1801981297 ps
CPU time	25.37 seconds
Started	Apr 30 03:20:30 PM PDT 24
Finished	Apr 30 03:20:56 PM PDT 24
Peak memory	219552 kb
Host	smart-fecfffa6-c761-4abe-b49a-5ee69b92c4e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127096870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3127096870
Directory	/workspace/16.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3091938355
Short name	T717
Test name
Test status
Simulation time	1420605922 ps
CPU time	3.28 seconds
Started	Apr 30 03:20:33 PM PDT 24
Finished	Apr 30 03:20:39 PM PDT 24
Peak memory	216168 kb
Host	smart-89a121c4-d1d9-4fe4-a32d-0bda92796630
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091938355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3091938355
Directory	/workspace/16.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_rw.1770582635
Short name	T482
Test name
Test status
Simulation time	81942772 ps
CPU time	1.15 seconds
Started	Apr 30 03:20:30 PM PDT 24
Finished	Apr 30 03:20:32 PM PDT 24
Peak memory	216228 kb
Host	smart-5fd3db40-da87-4ff5-9945-07db55bd525b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770582635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1770582635
Directory	/workspace/16.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/16.spi_device_tpm_sts_read.3025919137
Short name	T580
Test name
Test status
Simulation time	110987003 ps
CPU time	0.94 seconds
Started	Apr 30 03:20:31 PM PDT 24
Finished	Apr 30 03:20:34 PM PDT 24
Peak memory	206784 kb
Host	smart-ce782481-9dd2-4029-bf33-0b7c45856e6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025919137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3025919137
Directory	/workspace/16.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/17.spi_device_alert_test.3447787763
Short name	T636
Test name
Test status
Simulation time	40056329 ps
CPU time	0.76 seconds
Started	Apr 30 03:20:39 PM PDT 24
Finished	Apr 30 03:20:41 PM PDT 24
Peak memory	204860 kb
Host	smart-c8e1531b-4a01-4899-a6d7-5a69de0151cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447787763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test. 3447787763
Directory	/workspace/17.spi_device_alert_test/latest

Test location	/workspace/coverage/default/17.spi_device_cfg_cmd.3332022927
Short name	T454
Test name
Test status
Simulation time	128253245 ps
CPU time	2.59 seconds
Started	Apr 30 03:20:45 PM PDT 24
Finished	Apr 30 03:20:49 PM PDT 24
Peak memory	220772 kb
Host	smart-6265a387-172c-430f-924a-21291d3c5f7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332022927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3332022927
Directory	/workspace/17.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/17.spi_device_csb_read.419181529
Short name	T483
Test name
Test status
Simulation time	45164994 ps
CPU time	0.76 seconds
Started	Apr 30 03:20:31 PM PDT 24
Finished	Apr 30 03:20:32 PM PDT 24
Peak memory	206620 kb
Host	smart-96f8c359-7f29-48e5-832e-0c6203d480ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419181529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.419181529
Directory	/workspace/17.spi_device_csb_read/latest

Test location	/workspace/coverage/default/17.spi_device_flash_mode.945060783
Short name	T481
Test name
Test status
Simulation time	1154567428 ps
CPU time	22.14 seconds
Started	Apr 30 03:20:41 PM PDT 24
Finished	Apr 30 03:21:04 PM PDT 24
Peak memory	249032 kb
Host	smart-e1f7d396-fe8e-4660-8980-93d16ea2843d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945060783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.945060783
Directory	/workspace/17.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/17.spi_device_intercept.2948784031
Short name	T87
Test name
Test status
Simulation time	1304576989 ps
CPU time	13.6 seconds
Started	Apr 30 03:20:42 PM PDT 24
Finished	Apr 30 03:20:57 PM PDT 24
Peak memory	223980 kb
Host	smart-5422fcf3-aa81-4f1a-9c79-8bfb32db3262
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2948784031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2948784031
Directory	/workspace/17.spi_device_intercept/latest

Test location	/workspace/coverage/default/17.spi_device_mailbox.389479529
Short name	T182
Test name
Test status
Simulation time	51755860693 ps
CPU time	104.65 seconds
Started	Apr 30 03:20:39 PM PDT 24
Finished	Apr 30 03:22:25 PM PDT 24
Peak memory	223764 kb
Host	smart-b0bee030-f00e-4441-9613-d76463369e95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389479529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.389479529
Directory	/workspace/17.spi_device_mailbox/latest

Test location	/workspace/coverage/default/17.spi_device_pass_addr_payload_swap.762710230
Short name	T290
Test name
Test status
Simulation time	1971510549 ps
CPU time	4.06 seconds
Started	Apr 30 03:20:39 PM PDT 24
Finished	Apr 30 03:20:44 PM PDT 24
Peak memory	218416 kb
Host	smart-6f6a5c8e-0d0b-4a3b-900a-77b7c1752cd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762710230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap .762710230
Directory	/workspace/17.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/17.spi_device_pass_cmd_filtering.2521010732
Short name	T95
Test name
Test status
Simulation time	566865962 ps
CPU time	3.64 seconds
Started	Apr 30 03:20:42 PM PDT 24
Finished	Apr 30 03:20:46 PM PDT 24
Peak memory	222252 kb
Host	smart-379e4029-a33b-4e24-9823-b62e6a291cde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521010732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2521010732
Directory	/workspace/17.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/17.spi_device_read_buffer_direct.2965263723
Short name	T647
Test name
Test status
Simulation time	374606854 ps
CPU time	4.17 seconds
Started	Apr 30 03:20:43 PM PDT 24
Finished	Apr 30 03:20:48 PM PDT 24
Peak memory	222932 kb
Host	smart-a85662cf-4655-4301-8f80-633f4dea8bda
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2965263723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir ect.2965263723
Directory	/workspace/17.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2681183475
Short name	T77
Test name
Test status
Simulation time	444840737 ps
CPU time	4.05 seconds
Started	Apr 30 03:20:32 PM PDT 24
Finished	Apr 30 03:20:38 PM PDT 24
Peak memory	216088 kb
Host	smart-da3dc5ba-58b9-46d7-96e2-8f03c4cde663
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681183475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2681183475
Directory	/workspace/17.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_rw.4272637761
Short name	T1
Test name
Test status
Simulation time	1466006538 ps
CPU time	4.06 seconds
Started	Apr 30 03:20:31 PM PDT 24
Finished	Apr 30 03:20:36 PM PDT 24
Peak memory	216360 kb
Host	smart-62a17581-757c-40ce-9957-0094aa469c11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272637761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4272637761
Directory	/workspace/17.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/17.spi_device_tpm_sts_read.1438521084
Short name	T475
Test name
Test status
Simulation time	73107244 ps
CPU time	0.85 seconds
Started	Apr 30 03:20:34 PM PDT 24
Finished	Apr 30 03:20:37 PM PDT 24
Peak memory	205772 kb
Host	smart-17e01b74-76e3-4590-a9e4-ab424ba1585e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438521084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1438521084
Directory	/workspace/17.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/18.spi_device_alert_test.2953558489
Short name	T620
Test name
Test status
Simulation time	22277964 ps
CPU time	0.74 seconds
Started	Apr 30 03:20:40 PM PDT 24
Finished	Apr 30 03:20:42 PM PDT 24
Peak memory	205380 kb
Host	smart-be1607ae-df90-4cfb-b830-c9dc2219f56d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953558489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test. 2953558489
Directory	/workspace/18.spi_device_alert_test/latest

Test location	/workspace/coverage/default/18.spi_device_csb_read.2289570477
Short name	T486
Test name
Test status
Simulation time	176307478 ps
CPU time	0.78 seconds
Started	Apr 30 03:20:38 PM PDT 24
Finished	Apr 30 03:20:40 PM PDT 24
Peak memory	206680 kb
Host	smart-157218ba-59ce-4dc5-8de7-13fa0b806cc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289570477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2289570477
Directory	/workspace/18.spi_device_csb_read/latest

Test location	/workspace/coverage/default/18.spi_device_flash_mode.3647339122
Short name	T367
Test name
Test status
Simulation time	5866419517 ps
CPU time	76.04 seconds
Started	Apr 30 03:20:39 PM PDT 24
Finished	Apr 30 03:21:57 PM PDT 24
Peak memory	249116 kb
Host	smart-f24d2c58-2871-4e2a-b681-a0b08fe56118
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647339122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3647339122
Directory	/workspace/18.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/18.spi_device_mailbox.4144263535
Short name	T316
Test name
Test status
Simulation time	4125683042 ps
CPU time	48.83 seconds
Started	Apr 30 03:20:44 PM PDT 24
Finished	Apr 30 03:21:34 PM PDT 24
Peak memory	232488 kb
Host	smart-23a4ab33-27ce-4c7b-b904-b1cde92e5879
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144263535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4144263535
Directory	/workspace/18.spi_device_mailbox/latest

Test location	/workspace/coverage/default/18.spi_device_read_buffer_direct.2685163223
Short name	T573
Test name
Test status
Simulation time	4840281078 ps
CPU time	11.59 seconds
Started	Apr 30 03:20:40 PM PDT 24
Finished	Apr 30 03:20:53 PM PDT 24
Peak memory	219856 kb
Host	smart-d3fe547a-70ed-4d7e-80ed-28d154503f81
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2685163223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir ect.2685163223
Directory	/workspace/18.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_all.946857437
Short name	T698
Test name
Test status
Simulation time	896358316 ps
CPU time	7.77 seconds
Started	Apr 30 03:20:41 PM PDT 24
Finished	Apr 30 03:20:50 PM PDT 24
Peak memory	216316 kb
Host	smart-71ea662a-8111-4ef2-bac2-ee86dd953fe2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946857437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.946857437
Directory	/workspace/18.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1069817081
Short name	T653
Test name
Test status
Simulation time	6602996518 ps
CPU time	4.67 seconds
Started	Apr 30 03:20:44 PM PDT 24
Finished	Apr 30 03:20:50 PM PDT 24
Peak memory	216348 kb
Host	smart-97c3d356-e403-4414-bb46-674773c9109e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069817081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1069817081
Directory	/workspace/18.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_rw.1978243253
Short name	T680
Test name
Test status
Simulation time	385532220 ps
CPU time	1.66 seconds
Started	Apr 30 03:20:42 PM PDT 24
Finished	Apr 30 03:20:44 PM PDT 24
Peak memory	216300 kb
Host	smart-87394b3c-dde0-46ef-b9df-d2515562def4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978243253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1978243253
Directory	/workspace/18.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/18.spi_device_tpm_sts_read.1190094837
Short name	T467
Test name
Test status
Simulation time	20227856 ps
CPU time	0.75 seconds
Started	Apr 30 03:20:39 PM PDT 24
Finished	Apr 30 03:20:41 PM PDT 24
Peak memory	205744 kb
Host	smart-31c10781-1314-40a5-9825-8dabb4b16d22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190094837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1190094837
Directory	/workspace/18.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/19.spi_device_alert_test.4076163296
Short name	T700
Test name
Test status
Simulation time	15279049 ps
CPU time	0.7 seconds
Started	Apr 30 03:20:41 PM PDT 24
Finished	Apr 30 03:20:43 PM PDT 24
Peak memory	204844 kb
Host	smart-32b87895-8f88-4f97-9db5-eac2bf79d06d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076163296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test. 4076163296
Directory	/workspace/19.spi_device_alert_test/latest

Test location	/workspace/coverage/default/19.spi_device_csb_read.2669073847
Short name	T646
Test name
Test status
Simulation time	16848626 ps
CPU time	0.78 seconds
Started	Apr 30 03:20:36 PM PDT 24
Finished	Apr 30 03:20:38 PM PDT 24
Peak memory	206748 kb
Host	smart-686becc9-1557-47c8-8649-d958a87f90bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2669073847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2669073847
Directory	/workspace/19.spi_device_csb_read/latest

Test location	/workspace/coverage/default/19.spi_device_read_buffer_direct.3460915337
Short name	T725
Test name
Test status
Simulation time	198270695 ps
CPU time	4.69 seconds
Started	Apr 30 03:20:42 PM PDT 24
Finished	Apr 30 03:20:48 PM PDT 24
Peak memory	220508 kb
Host	smart-ba907ba1-1d2b-4cc9-8752-4b7678e80324
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3460915337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir ect.3460915337
Directory	/workspace/19.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1829350469
Short name	T578
Test name
Test status
Simulation time	20660009256 ps
CPU time	13.4 seconds
Started	Apr 30 03:20:41 PM PDT 24
Finished	Apr 30 03:20:55 PM PDT 24
Peak memory	216352 kb
Host	smart-05746edb-6e3a-4c6b-8204-0ccf082e7988
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829350469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1829350469
Directory	/workspace/19.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_rw.607378489
Short name	T402
Test name
Test status
Simulation time	717090969 ps
CPU time	4.3 seconds
Started	Apr 30 03:20:38 PM PDT 24
Finished	Apr 30 03:20:44 PM PDT 24
Peak memory	216352 kb
Host	smart-f294de28-d801-4aed-bd8e-984e1f47fca5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607378489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.607378489
Directory	/workspace/19.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/19.spi_device_tpm_sts_read.471289626
Short name	T659
Test name
Test status
Simulation time	121215148 ps
CPU time	1.01 seconds
Started	Apr 30 03:20:39 PM PDT 24
Finished	Apr 30 03:20:41 PM PDT 24
Peak memory	206824 kb
Host	smart-55831af5-53be-4bef-91bd-02c9354bcb12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471289626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.471289626
Directory	/workspace/19.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/19.spi_device_upload.3338322031
Short name	T714
Test name
Test status
Simulation time	10445554475 ps
CPU time	22.63 seconds
Started	Apr 30 03:20:38 PM PDT 24
Finished	Apr 30 03:21:01 PM PDT 24
Peak memory	232768 kb
Host	smart-25484f44-70f6-4225-ab47-b79ddd2a6ab1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338322031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3338322031
Directory	/workspace/19.spi_device_upload/latest

Test location	/workspace/coverage/default/2.spi_device_alert_test.2635407273
Short name	T701
Test name
Test status
Simulation time	11370611 ps
CPU time	0.72 seconds
Started	Apr 30 03:19:43 PM PDT 24
Finished	Apr 30 03:19:45 PM PDT 24
Peak memory	205416 kb
Host	smart-5b76a06e-f827-4cba-a7c9-2790203e890c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635407273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2 635407273
Directory	/workspace/2.spi_device_alert_test/latest

Test location	/workspace/coverage/default/2.spi_device_csb_read.1037852505
Short name	T491
Test name
Test status
Simulation time	74283611 ps
CPU time	0.77 seconds
Started	Apr 30 03:19:41 PM PDT 24
Finished	Apr 30 03:19:43 PM PDT 24
Peak memory	206748 kb
Host	smart-c1784716-6c63-497d-b02b-f5d19941aeec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037852505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1037852505
Directory	/workspace/2.spi_device_csb_read/latest

Test location	/workspace/coverage/default/2.spi_device_mailbox.488238677
Short name	T209
Test name
Test status
Simulation time	643663655 ps
CPU time	8.96 seconds
Started	Apr 30 03:19:50 PM PDT 24
Finished	Apr 30 03:20:00 PM PDT 24
Peak memory	218680 kb
Host	smart-1df60b62-4683-4401-9d63-afca579ec832
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488238677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.488238677
Directory	/workspace/2.spi_device_mailbox/latest

Test location	/workspace/coverage/default/2.spi_device_pass_cmd_filtering.3594944761
Short name	T184
Test name
Test status
Simulation time	51737709 ps
CPU time	2.46 seconds
Started	Apr 30 03:19:43 PM PDT 24
Finished	Apr 30 03:19:46 PM PDT 24
Peak memory	218600 kb
Host	smart-871b6516-9c41-4d03-b22d-5bf000999a37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594944761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3594944761
Directory	/workspace/2.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/2.spi_device_read_buffer_direct.747840706
Short name	T437
Test name
Test status
Simulation time	144032715 ps
CPU time	3.96 seconds
Started	Apr 30 03:19:50 PM PDT 24
Finished	Apr 30 03:19:55 PM PDT 24
Peak memory	220208 kb
Host	smart-b70dc9cc-19e3-4cac-8a94-5eabe668c0f0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=747840706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc t.747840706
Directory	/workspace/2.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/2.spi_device_sec_cm.4281568752
Short name	T48
Test name
Test status
Simulation time	91896799 ps
CPU time	1.2 seconds
Started	Apr 30 03:19:43 PM PDT 24
Finished	Apr 30 03:19:45 PM PDT 24
Peak memory	236120 kb
Host	smart-9b20a291-b84f-474c-a634-0923bfeb6366
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281568752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4281568752
Directory	/workspace/2.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_all.1076113825
Short name	T582
Test name
Test status
Simulation time	4213650784 ps
CPU time	5.41 seconds
Started	Apr 30 03:19:40 PM PDT 24
Finished	Apr 30 03:19:46 PM PDT 24
Peak memory	216268 kb
Host	smart-39af3d76-173a-474c-92f7-d62597e32ddc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1076113825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1076113825
Directory	/workspace/2.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_read_hw_reg.343109592
Short name	T555
Test name
Test status
Simulation time	317152508 ps
CPU time	1.7 seconds
Started	Apr 30 03:19:42 PM PDT 24
Finished	Apr 30 03:19:45 PM PDT 24
Peak memory	207828 kb
Host	smart-67747478-9958-4cad-85d5-84fe23fc7693
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343109592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.343109592
Directory	/workspace/2.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_rw.941226183
Short name	T415
Test name
Test status
Simulation time	41523862 ps
CPU time	0.76 seconds
Started	Apr 30 03:19:42 PM PDT 24
Finished	Apr 30 03:19:43 PM PDT 24
Peak memory	205776 kb
Host	smart-e331022f-1c22-4ee8-9175-08f3dfd32d74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=941226183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.941226183
Directory	/workspace/2.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/2.spi_device_tpm_sts_read.1220342569
Short name	T600
Test name
Test status
Simulation time	121078757 ps
CPU time	0.96 seconds
Started	Apr 30 03:19:44 PM PDT 24
Finished	Apr 30 03:19:46 PM PDT 24
Peak memory	206820 kb
Host	smart-c962c1d1-635f-4499-aaba-7e8773cdc333
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220342569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1220342569
Directory	/workspace/2.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/2.spi_device_upload.1972278559
Short name	T195
Test name
Test status
Simulation time	821958488 ps
CPU time	4.55 seconds
Started	Apr 30 03:19:43 PM PDT 24
Finished	Apr 30 03:19:49 PM PDT 24
Peak memory	234956 kb
Host	smart-dc4ce334-9d52-4b6a-9431-4f8b2829154f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972278559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1972278559
Directory	/workspace/2.spi_device_upload/latest

Test location	/workspace/coverage/default/20.spi_device_alert_test.1216807009
Short name	T699
Test name
Test status
Simulation time	20890566 ps
CPU time	0.7 seconds
Started	Apr 30 03:20:47 PM PDT 24
Finished	Apr 30 03:20:49 PM PDT 24
Peak memory	205420 kb
Host	smart-c010b79a-043c-4b9c-a2b2-5458125528a6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216807009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test. 1216807009
Directory	/workspace/20.spi_device_alert_test/latest

Test location	/workspace/coverage/default/20.spi_device_cfg_cmd.3716407375
Short name	T639
Test name
Test status
Simulation time	7788470269 ps
CPU time	13.75 seconds
Started	Apr 30 03:20:50 PM PDT 24
Finished	Apr 30 03:21:04 PM PDT 24
Peak memory	218788 kb
Host	smart-0708b1ec-db1b-4c49-aeaa-adf22e990e21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716407375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3716407375
Directory	/workspace/20.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/20.spi_device_csb_read.2984784929
Short name	T556
Test name
Test status
Simulation time	29359716 ps
CPU time	0.8 seconds
Started	Apr 30 03:20:44 PM PDT 24
Finished	Apr 30 03:20:46 PM PDT 24
Peak memory	206988 kb
Host	smart-11adb0b2-8893-4cbd-8796-614b2a838839
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984784929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2984784929
Directory	/workspace/20.spi_device_csb_read/latest

Test location	/workspace/coverage/default/20.spi_device_flash_mode.644312575
Short name	T584
Test name
Test status
Simulation time	9187592984 ps
CPU time	108.28 seconds
Started	Apr 30 03:20:49 PM PDT 24
Finished	Apr 30 03:22:38 PM PDT 24
Peak memory	232992 kb
Host	smart-9761fe31-2c9f-437a-b3c5-e1ef64f4754f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=644312575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.644312575
Directory	/workspace/20.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/20.spi_device_intercept.1073725238
Short name	T225
Test name
Test status
Simulation time	1828319743 ps
CPU time	6.63 seconds
Started	Apr 30 03:20:47 PM PDT 24
Finished	Apr 30 03:20:54 PM PDT 24
Peak memory	219056 kb
Host	smart-f06c1e33-57cc-4053-a152-66636c7ac85a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073725238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1073725238
Directory	/workspace/20.spi_device_intercept/latest

Test location	/workspace/coverage/default/20.spi_device_mailbox.2815368245
Short name	T650
Test name
Test status
Simulation time	1132517418 ps
CPU time	10.88 seconds
Started	Apr 30 03:20:53 PM PDT 24
Finished	Apr 30 03:21:04 PM PDT 24
Peak memory	218504 kb
Host	smart-60966406-fd4b-4ec9-8f14-4e90be1f44ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815368245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2815368245
Directory	/workspace/20.spi_device_mailbox/latest

Test location	/workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3739707268
Short name	T326
Test name
Test status
Simulation time	9376003461 ps
CPU time	23.65 seconds
Started	Apr 30 03:20:48 PM PDT 24
Finished	Apr 30 03:21:12 PM PDT 24
Peak memory	222772 kb
Host	smart-9f6e6f81-f721-422b-bf0b-6334853351b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739707268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa p.3739707268
Directory	/workspace/20.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/20.spi_device_pass_cmd_filtering.3017463098
Short name	T217
Test name
Test status
Simulation time	857276705 ps
CPU time	4.04 seconds
Started	Apr 30 03:20:47 PM PDT 24
Finished	Apr 30 03:20:52 PM PDT 24
Peak memory	218896 kb
Host	smart-1c07756c-8885-4987-96eb-e9a7d8887e75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017463098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3017463098
Directory	/workspace/20.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/20.spi_device_stress_all.3463705996
Short name	T36
Test name
Test status
Simulation time	387708984 ps
CPU time	1.03 seconds
Started	Apr 30 03:20:48 PM PDT 24
Finished	Apr 30 03:20:50 PM PDT 24
Peak memory	207128 kb
Host	smart-8536c7d8-7d07-4110-b962-7a3bc5af293a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463705996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre ss_all.3463705996
Directory	/workspace/20.spi_device_stress_all/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_all.3607118514
Short name	T399
Test name
Test status
Simulation time	3916408918 ps
CPU time	29.63 seconds
Started	Apr 30 03:20:46 PM PDT 24
Finished	Apr 30 03:21:16 PM PDT 24
Peak memory	216380 kb
Host	smart-fdc309d9-cc26-450e-b50c-642fd5aba203
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607118514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3607118514
Directory	/workspace/20.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2546676427
Short name	T540
Test name
Test status
Simulation time	649362233 ps
CPU time	4.66 seconds
Started	Apr 30 03:20:49 PM PDT 24
Finished	Apr 30 03:20:55 PM PDT 24
Peak memory	216228 kb
Host	smart-b9871340-9543-4939-b83c-d07826602096
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546676427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2546676427
Directory	/workspace/20.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_rw.378219022
Short name	T421
Test name
Test status
Simulation time	708419937 ps
CPU time	1.56 seconds
Started	Apr 30 03:20:47 PM PDT 24
Finished	Apr 30 03:20:49 PM PDT 24
Peak memory	216148 kb
Host	smart-19de8a27-a780-4d30-b419-5e2bbc74775a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=378219022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.378219022
Directory	/workspace/20.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/20.spi_device_tpm_sts_read.1869275704
Short name	T644
Test name
Test status
Simulation time	92295377 ps
CPU time	0.81 seconds
Started	Apr 30 03:20:46 PM PDT 24
Finished	Apr 30 03:20:48 PM PDT 24
Peak memory	205756 kb
Host	smart-e8d2be2e-04e6-4b96-8d9f-c007a7952d09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869275704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1869275704
Directory	/workspace/20.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/20.spi_device_upload.329709500
Short name	T256
Test name
Test status
Simulation time	27576131993 ps
CPU time	24.6 seconds
Started	Apr 30 03:20:50 PM PDT 24
Finished	Apr 30 03:21:15 PM PDT 24
Peak memory	232656 kb
Host	smart-20b81646-bfb5-428e-bb41-57a984b54d75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329709500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.329709500
Directory	/workspace/20.spi_device_upload/latest

Test location	/workspace/coverage/default/21.spi_device_alert_test.1786598409
Short name	T672
Test name
Test status
Simulation time	63917545 ps
CPU time	0.74 seconds
Started	Apr 30 03:20:55 PM PDT 24
Finished	Apr 30 03:20:57 PM PDT 24
Peak memory	205668 kb
Host	smart-d0250bac-40ee-4770-9f13-a98c2df30ea9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786598409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test. 1786598409
Directory	/workspace/21.spi_device_alert_test/latest

Test location	/workspace/coverage/default/21.spi_device_cfg_cmd.3711918427
Short name	T637
Test name
Test status
Simulation time	3371387127 ps
CPU time	25.27 seconds
Started	Apr 30 03:20:48 PM PDT 24
Finished	Apr 30 03:21:14 PM PDT 24
Peak memory	219068 kb
Host	smart-ec03f974-3b42-44dd-9e6e-f0760d345f7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711918427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3711918427
Directory	/workspace/21.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/21.spi_device_csb_read.2635562374
Short name	T169
Test name
Test status
Simulation time	24037619 ps
CPU time	0.8 seconds
Started	Apr 30 03:20:49 PM PDT 24
Finished	Apr 30 03:20:51 PM PDT 24
Peak memory	205640 kb
Host	smart-61f9a0c6-d75a-497f-a739-885880278c08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635562374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2635562374
Directory	/workspace/21.spi_device_csb_read/latest

Test location	/workspace/coverage/default/21.spi_device_flash_mode.1147517322
Short name	T372
Test name
Test status
Simulation time	919091148 ps
CPU time	19.26 seconds
Started	Apr 30 03:20:57 PM PDT 24
Finished	Apr 30 03:21:17 PM PDT 24
Peak memory	249048 kb
Host	smart-69d13e66-5cfd-40b9-aca7-655cfab29c05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1147517322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1147517322
Directory	/workspace/21.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/21.spi_device_intercept.1843107039
Short name	T479
Test name
Test status
Simulation time	839082796 ps
CPU time	9.43 seconds
Started	Apr 30 03:20:51 PM PDT 24
Finished	Apr 30 03:21:01 PM PDT 24
Peak memory	232432 kb
Host	smart-7054d8d3-2cea-4ef8-9aae-228a920d84d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1843107039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1843107039
Directory	/workspace/21.spi_device_intercept/latest

Test location	/workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4039329556
Short name	T186
Test name
Test status
Simulation time	3377819377 ps
CPU time	9.68 seconds
Started	Apr 30 03:20:50 PM PDT 24
Finished	Apr 30 03:21:01 PM PDT 24
Peak memory	234720 kb
Host	smart-82e6f555-1b2d-4fd3-9426-c75914b72065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4039329556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa p.4039329556
Directory	/workspace/21.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/21.spi_device_pass_cmd_filtering.1820057084
Short name	T214
Test name
Test status
Simulation time	14262231856 ps
CPU time	8.58 seconds
Started	Apr 30 03:20:48 PM PDT 24
Finished	Apr 30 03:20:58 PM PDT 24
Peak memory	218548 kb
Host	smart-b49fde99-bd89-4c4c-969c-b0711d44b86d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820057084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1820057084
Directory	/workspace/21.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/21.spi_device_read_buffer_direct.4158771127
Short name	T658
Test name
Test status
Simulation time	1666577847 ps
CPU time	5.82 seconds
Started	Apr 30 03:20:57 PM PDT 24
Finished	Apr 30 03:21:04 PM PDT 24
Peak memory	220328 kb
Host	smart-76c1b23d-0552-4ffe-9509-ebcbe5c7348a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4158771127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir ect.4158771127
Directory	/workspace/21.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/21.spi_device_stress_all.2632920286
Short name	T511
Test name
Test status
Simulation time	475050371 ps
CPU time	1 seconds
Started	Apr 30 03:20:57 PM PDT 24
Finished	Apr 30 03:20:59 PM PDT 24
Peak memory	206940 kb
Host	smart-508eef54-9e32-4990-9c3f-1085a971ec21
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632920286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre ss_all.2632920286
Directory	/workspace/21.spi_device_stress_all/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_all.1457511984
Short name	T391
Test name
Test status
Simulation time	952575329 ps
CPU time	9.87 seconds
Started	Apr 30 03:20:48 PM PDT 24
Finished	Apr 30 03:20:59 PM PDT 24
Peak memory	216312 kb
Host	smart-285a8dc8-2498-4a70-9a6e-bd19a10abb8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457511984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1457511984
Directory	/workspace/21.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3941927140
Short name	T538
Test name
Test status
Simulation time	12118056066 ps
CPU time	13.31 seconds
Started	Apr 30 03:20:48 PM PDT 24
Finished	Apr 30 03:21:02 PM PDT 24
Peak memory	216288 kb
Host	smart-b5ee08b3-a5a3-40ef-a65b-8713b614e4e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941927140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3941927140
Directory	/workspace/21.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_rw.3341676910
Short name	T686
Test name
Test status
Simulation time	67963375 ps
CPU time	2.51 seconds
Started	Apr 30 03:20:45 PM PDT 24
Finished	Apr 30 03:20:49 PM PDT 24
Peak memory	216552 kb
Host	smart-dc784ba7-d339-42da-b88e-9c4408f20b01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341676910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3341676910
Directory	/workspace/21.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/21.spi_device_tpm_sts_read.4235502440
Short name	T707
Test name
Test status
Simulation time	35770788 ps
CPU time	0.86 seconds
Started	Apr 30 03:20:49 PM PDT 24
Finished	Apr 30 03:20:51 PM PDT 24
Peak memory	205772 kb
Host	smart-13c9f21c-52e1-41b9-926c-0fb4d8c60688
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235502440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4235502440
Directory	/workspace/21.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/22.spi_device_alert_test.1229241185
Short name	T558
Test name
Test status
Simulation time	19912699 ps
CPU time	0.73 seconds
Started	Apr 30 03:20:55 PM PDT 24
Finished	Apr 30 03:20:56 PM PDT 24
Peak memory	205616 kb
Host	smart-3355ac19-c789-4593-907f-689f5d8c51cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229241185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test. 1229241185
Directory	/workspace/22.spi_device_alert_test/latest

Test location	/workspace/coverage/default/22.spi_device_csb_read.3885437388
Short name	T548
Test name
Test status
Simulation time	46121272 ps
CPU time	0.76 seconds
Started	Apr 30 03:20:58 PM PDT 24
Finished	Apr 30 03:20:59 PM PDT 24
Peak memory	205944 kb
Host	smart-e3ddd0d1-5299-41e7-8ee6-db6a94afd0e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885437388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3885437388
Directory	/workspace/22.spi_device_csb_read/latest

Test location	/workspace/coverage/default/22.spi_device_flash_mode.2565863226
Short name	T352
Test name
Test status
Simulation time	2486476744 ps
CPU time	28.41 seconds
Started	Apr 30 03:20:58 PM PDT 24
Finished	Apr 30 03:21:27 PM PDT 24
Peak memory	236764 kb
Host	smart-159185b9-448f-4ce6-a6f2-0421c6c141e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565863226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2565863226
Directory	/workspace/22.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/22.spi_device_intercept.2715652644
Short name	T78
Test name
Test status
Simulation time	95363672 ps
CPU time	2.5 seconds
Started	Apr 30 03:20:54 PM PDT 24
Finished	Apr 30 03:20:57 PM PDT 24
Peak memory	222280 kb
Host	smart-7ce7cc6d-ac7d-4edf-a35b-934c3d2ce8d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715652644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2715652644
Directory	/workspace/22.spi_device_intercept/latest

Test location	/workspace/coverage/default/22.spi_device_mailbox.1475238506
Short name	T286
Test name
Test status
Simulation time	6684962888 ps
CPU time	27.88 seconds
Started	Apr 30 03:20:54 PM PDT 24
Finished	Apr 30 03:21:23 PM PDT 24
Peak memory	232812 kb
Host	smart-e1d3f4ee-4df6-4a0c-b22b-a5def97bb8bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475238506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1475238506
Directory	/workspace/22.spi_device_mailbox/latest

Test location	/workspace/coverage/default/22.spi_device_read_buffer_direct.179046041
Short name	T661
Test name
Test status
Simulation time	1134627185 ps
CPU time	6.34 seconds
Started	Apr 30 03:21:00 PM PDT 24
Finished	Apr 30 03:21:07 PM PDT 24
Peak memory	219188 kb
Host	smart-10450248-df07-4d6a-8f02-5bfdd08f185d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=179046041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire ct.179046041
Directory	/workspace/22.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_all.2045808402
Short name	T651
Test name
Test status
Simulation time	2649139501 ps
CPU time	16.06 seconds
Started	Apr 30 03:21:00 PM PDT 24
Finished	Apr 30 03:21:17 PM PDT 24
Peak memory	219588 kb
Host	smart-f3964b4c-c2dd-4bac-8281-afcb763d1095
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045808402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2045808402
Directory	/workspace/22.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_read_hw_reg.711091737
Short name	T477
Test name
Test status
Simulation time	5295335617 ps
CPU time	20.36 seconds
Started	Apr 30 03:20:56 PM PDT 24
Finished	Apr 30 03:21:18 PM PDT 24
Peak memory	216300 kb
Host	smart-234d75ce-8953-4bbc-ac11-a7593648e2b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711091737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.711091737
Directory	/workspace/22.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_rw.3961425772
Short name	T414
Test name
Test status
Simulation time	82325948 ps
CPU time	2.13 seconds
Started	Apr 30 03:20:58 PM PDT 24
Finished	Apr 30 03:21:01 PM PDT 24
Peak memory	216256 kb
Host	smart-cb4397ee-cf8d-49e6-a962-797502ff7126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961425772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3961425772
Directory	/workspace/22.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/22.spi_device_tpm_sts_read.2519788688
Short name	T16
Test name
Test status
Simulation time	715725918 ps
CPU time	0.9 seconds
Started	Apr 30 03:20:57 PM PDT 24
Finished	Apr 30 03:20:59 PM PDT 24
Peak memory	205768 kb
Host	smart-df2b4042-090a-447a-a34c-ef2eccef4e60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519788688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2519788688
Directory	/workspace/22.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/23.spi_device_alert_test.744803978
Short name	T32
Test name
Test status
Simulation time	16753082 ps
CPU time	0.73 seconds
Started	Apr 30 03:21:08 PM PDT 24
Finished	Apr 30 03:21:10 PM PDT 24
Peak memory	205404 kb
Host	smart-214c6017-c786-47bc-9d72-b74d683952ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744803978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.744803978
Directory	/workspace/23.spi_device_alert_test/latest

Test location	/workspace/coverage/default/23.spi_device_cfg_cmd.3175122862
Short name	T28
Test name
Test status
Simulation time	812389634 ps
CPU time	4.86 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:12 PM PDT 24
Peak memory	218988 kb
Host	smart-557a49f9-0154-4c68-a7b3-94c5274d8043
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3175122862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3175122862
Directory	/workspace/23.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/23.spi_device_csb_read.1767631083
Short name	T433
Test name
Test status
Simulation time	29217411 ps
CPU time	0.8 seconds
Started	Apr 30 03:20:57 PM PDT 24
Finished	Apr 30 03:20:59 PM PDT 24
Peak memory	206984 kb
Host	smart-d2f5c82d-c9aa-4cca-8812-3b5572cdb8b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767631083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1767631083
Directory	/workspace/23.spi_device_csb_read/latest

Test location	/workspace/coverage/default/23.spi_device_flash_mode.2228536235
Short name	T86
Test name
Test status
Simulation time	6078074674 ps
CPU time	13.83 seconds
Started	Apr 30 03:21:11 PM PDT 24
Finished	Apr 30 03:21:26 PM PDT 24
Peak memory	249556 kb
Host	smart-1ab84d12-2a3a-4d13-b482-9a3939abb977
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228536235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2228536235
Directory	/workspace/23.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/23.spi_device_mailbox.2823117210
Short name	T473
Test name
Test status
Simulation time	391656913 ps
CPU time	4.93 seconds
Started	Apr 30 03:20:56 PM PDT 24
Finished	Apr 30 03:21:02 PM PDT 24
Peak memory	218648 kb
Host	smart-e6987fe3-6a54-4c96-bd34-2f0da24ec1e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823117210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2823117210
Directory	/workspace/23.spi_device_mailbox/latest

Test location	/workspace/coverage/default/23.spi_device_read_buffer_direct.1176165453
Short name	T506
Test name
Test status
Simulation time	2843207797 ps
CPU time	11.83 seconds
Started	Apr 30 03:21:03 PM PDT 24
Finished	Apr 30 03:21:16 PM PDT 24
Peak memory	220404 kb
Host	smart-22b12f0a-b2b1-49cc-9d86-8f7bd511749d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1176165453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir ect.1176165453
Directory	/workspace/23.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_all.211862720
Short name	T643
Test name
Test status
Simulation time	2579324602 ps
CPU time	12.48 seconds
Started	Apr 30 03:20:59 PM PDT 24
Finished	Apr 30 03:21:12 PM PDT 24
Peak memory	216336 kb
Host	smart-1718cbad-756b-4a93-a2ce-8e77a160a459
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211862720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.211862720
Directory	/workspace/23.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3215045148
Short name	T444
Test name
Test status
Simulation time	3560478660 ps
CPU time	8.82 seconds
Started	Apr 30 03:20:58 PM PDT 24
Finished	Apr 30 03:21:07 PM PDT 24
Peak memory	216328 kb
Host	smart-7eae3d64-14fc-45d1-b215-c22db4f0e7fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215045148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3215045148
Directory	/workspace/23.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_rw.444718269
Short name	T626
Test name
Test status
Simulation time	115846372 ps
CPU time	1.34 seconds
Started	Apr 30 03:20:56 PM PDT 24
Finished	Apr 30 03:20:58 PM PDT 24
Peak memory	216232 kb
Host	smart-09d9829f-cdd3-49ec-8d0f-2a8f78f4bc46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444718269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.444718269
Directory	/workspace/23.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/23.spi_device_tpm_sts_read.1928365896
Short name	T494
Test name
Test status
Simulation time	46230220 ps
CPU time	0.8 seconds
Started	Apr 30 03:20:56 PM PDT 24
Finished	Apr 30 03:20:58 PM PDT 24
Peak memory	205740 kb
Host	smart-274709cd-3e04-4550-a2c1-15e96faab518
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1928365896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1928365896
Directory	/workspace/23.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/23.spi_device_upload.1964005245
Short name	T608
Test name
Test status
Simulation time	9059142377 ps
CPU time	24.93 seconds
Started	Apr 30 03:20:59 PM PDT 24
Finished	Apr 30 03:21:25 PM PDT 24
Peak memory	224548 kb
Host	smart-cda63181-d6bd-4b48-a2ef-29ba87bbad85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964005245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1964005245
Directory	/workspace/23.spi_device_upload/latest

Test location	/workspace/coverage/default/24.spi_device_alert_test.61812900
Short name	T480
Test name
Test status
Simulation time	14237351 ps
CPU time	0.7 seconds
Started	Apr 30 03:21:05 PM PDT 24
Finished	Apr 30 03:21:06 PM PDT 24
Peak memory	204808 kb
Host	smart-45bd261d-76ad-4e42-8b20-e03546941fc9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61812900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.61812900
Directory	/workspace/24.spi_device_alert_test/latest

Test location	/workspace/coverage/default/24.spi_device_csb_read.2860892927
Short name	T563
Test name
Test status
Simulation time	67832264 ps
CPU time	0.75 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:08 PM PDT 24
Peak memory	206668 kb
Host	smart-a0da4305-8dce-46da-90f8-edb464b49b3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860892927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2860892927
Directory	/workspace/24.spi_device_csb_read/latest

Test location	/workspace/coverage/default/24.spi_device_intercept.1292283881
Short name	T179
Test name
Test status
Simulation time	2033245263 ps
CPU time	8.34 seconds
Started	Apr 30 03:21:07 PM PDT 24
Finished	Apr 30 03:21:17 PM PDT 24
Peak memory	221892 kb
Host	smart-0be4b20d-f320-4945-b46b-fefa1a78a7fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292283881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1292283881
Directory	/workspace/24.spi_device_intercept/latest

Test location	/workspace/coverage/default/24.spi_device_pass_cmd_filtering.924379664
Short name	T386
Test name
Test status
Simulation time	2491614921 ps
CPU time	8.52 seconds
Started	Apr 30 03:21:05 PM PDT 24
Finished	Apr 30 03:21:14 PM PDT 24
Peak memory	232564 kb
Host	smart-2cc422fe-4127-4394-991c-15d777aa58c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=924379664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.924379664
Directory	/workspace/24.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/24.spi_device_read_buffer_direct.2786921228
Short name	T505
Test name
Test status
Simulation time	890694584 ps
CPU time	7.41 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:15 PM PDT 24
Peak memory	222832 kb
Host	smart-f1ba798f-1479-4070-9c17-255ed4a83331
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2786921228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir ect.2786921228
Directory	/workspace/24.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2917258308
Short name	T574
Test name
Test status
Simulation time	579559850 ps
CPU time	2.25 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:09 PM PDT 24
Peak memory	216232 kb
Host	smart-f1abbae9-24f5-41e8-a8ed-4b8b36abf7d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917258308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2917258308
Directory	/workspace/24.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_rw.3703954894
Short name	T516
Test name
Test status
Simulation time	64228616 ps
CPU time	0.87 seconds
Started	Apr 30 03:21:04 PM PDT 24
Finished	Apr 30 03:21:05 PM PDT 24
Peak memory	205860 kb
Host	smart-fd4ac89a-5448-4248-be4c-b82680ec8e00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703954894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3703954894
Directory	/workspace/24.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/24.spi_device_tpm_sts_read.4069165148
Short name	T728
Test name
Test status
Simulation time	528605278 ps
CPU time	0.88 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:08 PM PDT 24
Peak memory	206784 kb
Host	smart-b8676c35-1d1c-43d2-9f69-97ecf2c4b7fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4069165148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4069165148
Directory	/workspace/24.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/24.spi_device_upload.2567926399
Short name	T213
Test name
Test status
Simulation time	910983433 ps
CPU time	4.35 seconds
Started	Apr 30 03:21:07 PM PDT 24
Finished	Apr 30 03:21:13 PM PDT 24
Peak memory	218872 kb
Host	smart-1ff997d0-b2d4-4e63-84e4-b19466911b6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567926399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2567926399
Directory	/workspace/24.spi_device_upload/latest

Test location	/workspace/coverage/default/25.spi_device_alert_test.1388781883
Short name	T474
Test name
Test status
Simulation time	119191673 ps
CPU time	0.72 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:08 PM PDT 24
Peak memory	205388 kb
Host	smart-823e7d7e-cdc5-4c80-9f3e-111cd0e801a2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388781883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test. 1388781883
Directory	/workspace/25.spi_device_alert_test/latest

Test location	/workspace/coverage/default/25.spi_device_csb_read.214234238
Short name	T458
Test name
Test status
Simulation time	51964240 ps
CPU time	0.78 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:08 PM PDT 24
Peak memory	206640 kb
Host	smart-abb11c63-f6e5-4541-9b56-fae825dd53a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=214234238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.214234238
Directory	/workspace/25.spi_device_csb_read/latest

Test location	/workspace/coverage/default/25.spi_device_mailbox.556845558
Short name	T187
Test name
Test status
Simulation time	18090412621 ps
CPU time	102.96 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:22:50 PM PDT 24
Peak memory	223564 kb
Host	smart-4f0e40be-9bd0-4e14-8b91-93cc47dba3bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556845558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.556845558
Directory	/workspace/25.spi_device_mailbox/latest

Test location	/workspace/coverage/default/25.spi_device_pass_cmd_filtering.3151450989
Short name	T247
Test name
Test status
Simulation time	555457624 ps
CPU time	6.18 seconds
Started	Apr 30 03:21:09 PM PDT 24
Finished	Apr 30 03:21:16 PM PDT 24
Peak memory	240020 kb
Host	smart-8985d18f-dd80-4637-865e-4f8b4ef1f5da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3151450989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3151450989
Directory	/workspace/25.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/25.spi_device_read_buffer_direct.1318988479
Short name	T143
Test name
Test status
Simulation time	1034955224 ps
CPU time	4.06 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:11 PM PDT 24
Peak memory	222956 kb
Host	smart-3075c170-f888-447d-a7b4-9d077a0bc8f0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1318988479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir ect.1318988479
Directory	/workspace/25.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/25.spi_device_stress_all.866542579
Short name	T687
Test name
Test status
Simulation time	839717400 ps
CPU time	0.95 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:08 PM PDT 24
Peak memory	207192 kb
Host	smart-ce8ac3f8-dd01-4fc6-a0f3-0e9764385407
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866542579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres s_all.866542579
Directory	/workspace/25.spi_device_stress_all/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2111771802
Short name	T55
Test name
Test status
Simulation time	99076698841 ps
CPU time	15.4 seconds
Started	Apr 30 03:21:07 PM PDT 24
Finished	Apr 30 03:21:24 PM PDT 24
Peak memory	216132 kb
Host	smart-0531bb50-ef9e-42d5-8882-196652e2bcf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111771802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2111771802
Directory	/workspace/25.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_rw.1124683406
Short name	T553
Test name
Test status
Simulation time	136816523 ps
CPU time	2.39 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:09 PM PDT 24
Peak memory	216328 kb
Host	smart-8cb99923-f62a-4429-82c7-0aaac98ab845
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124683406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1124683406
Directory	/workspace/25.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/25.spi_device_tpm_sts_read.211676421
Short name	T635
Test name
Test status
Simulation time	57641632 ps
CPU time	0.86 seconds
Started	Apr 30 03:21:06 PM PDT 24
Finished	Apr 30 03:21:08 PM PDT 24
Peak memory	205772 kb
Host	smart-86624bbc-3a08-45ca-9460-9625865ecdfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211676421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.211676421
Directory	/workspace/25.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/26.spi_device_alert_test.2583978611
Short name	T669
Test name
Test status
Simulation time	105953764 ps
CPU time	0.67 seconds
Started	Apr 30 03:21:15 PM PDT 24
Finished	Apr 30 03:21:17 PM PDT 24
Peak memory	205712 kb
Host	smart-3112a1c6-40c8-4b6a-9f63-7333af28bbb4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583978611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test. 2583978611
Directory	/workspace/26.spi_device_alert_test/latest

Test location	/workspace/coverage/default/26.spi_device_cfg_cmd.2519285345
Short name	T237
Test name
Test status
Simulation time	714120667 ps
CPU time	4.56 seconds
Started	Apr 30 03:21:15 PM PDT 24
Finished	Apr 30 03:21:20 PM PDT 24
Peak memory	223028 kb
Host	smart-d4b00c30-7ac1-40d4-b73b-b325d9f1aa6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519285345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2519285345
Directory	/workspace/26.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/26.spi_device_csb_read.1753559747
Short name	T552
Test name
Test status
Simulation time	30002285 ps
CPU time	0.91 seconds
Started	Apr 30 03:21:08 PM PDT 24
Finished	Apr 30 03:21:10 PM PDT 24
Peak memory	206660 kb
Host	smart-0d262fbd-86cc-4f1d-8985-f1ef91d486bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753559747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1753559747
Directory	/workspace/26.spi_device_csb_read/latest

Test location	/workspace/coverage/default/26.spi_device_flash_mode.89780812
Short name	T385
Test name
Test status
Simulation time	4959713121 ps
CPU time	57.16 seconds
Started	Apr 30 03:21:18 PM PDT 24
Finished	Apr 30 03:22:16 PM PDT 24
Peak memory	240888 kb
Host	smart-8f7f917b-6486-40ca-8716-96a78a32086f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=89780812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.89780812
Directory	/workspace/26.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.113557563
Short name	T336
Test name
Test status
Simulation time	2150639029 ps
CPU time	3.49 seconds
Started	Apr 30 03:21:04 PM PDT 24
Finished	Apr 30 03:21:08 PM PDT 24
Peak memory	218520 kb
Host	smart-660c8955-5a99-4910-82de-5ae474df68e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113557563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap .113557563
Directory	/workspace/26.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/26.spi_device_pass_cmd_filtering.3736974825
Short name	T288
Test name
Test status
Simulation time	37155146007 ps
CPU time	16.22 seconds
Started	Apr 30 03:21:07 PM PDT 24
Finished	Apr 30 03:21:24 PM PDT 24
Peak memory	218636 kb
Host	smart-d94c18a9-b782-43c9-86fa-02aacdf04569
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736974825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3736974825
Directory	/workspace/26.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/26.spi_device_read_buffer_direct.88112977
Short name	T546
Test name
Test status
Simulation time	2981969997 ps
CPU time	14.2 seconds
Started	Apr 30 03:21:18 PM PDT 24
Finished	Apr 30 03:21:33 PM PDT 24
Peak memory	218768 kb
Host	smart-17191ba0-cdda-42b8-bdfe-fcfc64674bbf
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=88112977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direc t.88112977
Directory	/workspace/26.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.471460042
Short name	T710
Test name
Test status
Simulation time	11742227782 ps
CPU time	31.97 seconds
Started	Apr 30 03:21:07 PM PDT 24
Finished	Apr 30 03:21:41 PM PDT 24
Peak memory	216324 kb
Host	smart-81d23713-6e56-4861-8422-eee51eb0b56c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471460042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.471460042
Directory	/workspace/26.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_rw.1306294419
Short name	T681
Test name
Test status
Simulation time	178156210 ps
CPU time	1.26 seconds
Started	Apr 30 03:21:04 PM PDT 24
Finished	Apr 30 03:21:07 PM PDT 24
Peak memory	207752 kb
Host	smart-59956d2c-0e0d-4ed4-b2b0-33858c956482
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306294419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1306294419
Directory	/workspace/26.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/26.spi_device_tpm_sts_read.1955965424
Short name	T59
Test name
Test status
Simulation time	63432811 ps
CPU time	0.84 seconds
Started	Apr 30 03:21:04 PM PDT 24
Finished	Apr 30 03:21:06 PM PDT 24
Peak memory	205760 kb
Host	smart-634dcfd1-7b43-4c6e-818b-b73ebda4bef9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1955965424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1955965424
Directory	/workspace/26.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/27.spi_device_alert_test.3017482268
Short name	T597
Test name
Test status
Simulation time	104057114 ps
CPU time	0.72 seconds
Started	Apr 30 03:21:16 PM PDT 24
Finished	Apr 30 03:21:18 PM PDT 24
Peak memory	204764 kb
Host	smart-9e79e8f6-46b1-497f-93c6-f437de656fe7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017482268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test. 3017482268
Directory	/workspace/27.spi_device_alert_test/latest

Test location	/workspace/coverage/default/27.spi_device_cfg_cmd.2188263701
Short name	T476
Test name
Test status
Simulation time	15545779774 ps
CPU time	35.11 seconds
Started	Apr 30 03:21:18 PM PDT 24
Finished	Apr 30 03:21:54 PM PDT 24
Peak memory	218740 kb
Host	smart-def4629c-2621-4b11-9bae-e29b046a6315
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188263701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2188263701
Directory	/workspace/27.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/27.spi_device_csb_read.3021858637
Short name	T594
Test name
Test status
Simulation time	19406334 ps
CPU time	0.77 seconds
Started	Apr 30 03:21:21 PM PDT 24
Finished	Apr 30 03:21:22 PM PDT 24
Peak memory	206672 kb
Host	smart-3748b86c-36c9-489a-b08b-daa6ca33c83a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021858637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3021858637
Directory	/workspace/27.spi_device_csb_read/latest

Test location	/workspace/coverage/default/27.spi_device_flash_mode.3315877096
Short name	T576
Test name
Test status
Simulation time	2348426952 ps
CPU time	20.84 seconds
Started	Apr 30 03:21:19 PM PDT 24
Finished	Apr 30 03:21:40 PM PDT 24
Peak memory	240468 kb
Host	smart-bfe2b786-e885-4e33-89fa-8cd0daae55ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315877096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3315877096
Directory	/workspace/27.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1945203156
Short name	T332
Test name
Test status
Simulation time	302932065 ps
CPU time	5.64 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:24 PM PDT 24
Peak memory	239764 kb
Host	smart-9492b841-342c-4860-afb6-b574d23a1545
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945203156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa p.1945203156
Directory	/workspace/27.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/27.spi_device_read_buffer_direct.3001466973
Short name	T52
Test name
Test status
Simulation time	382994666 ps
CPU time	5.41 seconds
Started	Apr 30 03:21:14 PM PDT 24
Finished	Apr 30 03:21:20 PM PDT 24
Peak memory	219164 kb
Host	smart-21ccd27e-059b-477b-9700-f62f11e4694e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3001466973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir ect.3001466973
Directory	/workspace/27.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/27.spi_device_stress_all.3248602764
Short name	T163
Test name
Test status
Simulation time	343592974 ps
CPU time	0.95 seconds
Started	Apr 30 03:21:15 PM PDT 24
Finished	Apr 30 03:21:16 PM PDT 24
Peak memory	206996 kb
Host	smart-ca1672a7-a473-4961-a7b8-d2c0d57189c1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248602764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre ss_all.3248602764
Directory	/workspace/27.spi_device_stress_all/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_all.2658551772
Short name	T403
Test name
Test status
Simulation time	6892375304 ps
CPU time	35.05 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:53 PM PDT 24
Peak memory	216364 kb
Host	smart-6031c592-89f6-40e4-a9ff-a55ca7311ea9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658551772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2658551772
Directory	/workspace/27.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2924138017
Short name	T591
Test name
Test status
Simulation time	320792083 ps
CPU time	2.44 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:21 PM PDT 24
Peak memory	216276 kb
Host	smart-c459442a-d958-4021-a9e0-fc9756815267
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924138017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2924138017
Directory	/workspace/27.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_rw.156524869
Short name	T598
Test name
Test status
Simulation time	57914171 ps
CPU time	1.16 seconds
Started	Apr 30 03:21:14 PM PDT 24
Finished	Apr 30 03:21:16 PM PDT 24
Peak memory	216212 kb
Host	smart-05420502-85ef-46b8-b2e8-527ac28a2dbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156524869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.156524869
Directory	/workspace/27.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/27.spi_device_tpm_sts_read.3221562163
Short name	T490
Test name
Test status
Simulation time	120668409 ps
CPU time	1.11 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:19 PM PDT 24
Peak memory	206772 kb
Host	smart-45c2aac5-14e0-4115-b26d-2b2799531e9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221562163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3221562163
Directory	/workspace/27.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/27.spi_device_upload.2919260474
Short name	T263
Test name
Test status
Simulation time	1477695931 ps
CPU time	6.45 seconds
Started	Apr 30 03:21:14 PM PDT 24
Finished	Apr 30 03:21:21 PM PDT 24
Peak memory	223476 kb
Host	smart-ba7d0191-5e61-4ecb-bdbb-78b98b3ad8a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2919260474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2919260474
Directory	/workspace/27.spi_device_upload/latest

Test location	/workspace/coverage/default/28.spi_device_alert_test.1372579004
Short name	T439
Test name
Test status
Simulation time	12832993 ps
CPU time	0.74 seconds
Started	Apr 30 03:21:18 PM PDT 24
Finished	Apr 30 03:21:19 PM PDT 24
Peak memory	205284 kb
Host	smart-ab257817-783b-46ec-9a59-31656a4302f4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372579004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test. 1372579004
Directory	/workspace/28.spi_device_alert_test/latest

Test location	/workspace/coverage/default/28.spi_device_csb_read.3430186399
Short name	T657
Test name
Test status
Simulation time	13312151 ps
CPU time	0.8 seconds
Started	Apr 30 03:21:14 PM PDT 24
Finished	Apr 30 03:21:16 PM PDT 24
Peak memory	207060 kb
Host	smart-3f21d4a3-2d45-4ad3-875d-03ad3dedf1d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430186399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3430186399
Directory	/workspace/28.spi_device_csb_read/latest

Test location	/workspace/coverage/default/28.spi_device_flash_mode.4199055926
Short name	T351
Test name
Test status
Simulation time	7876925756 ps
CPU time	102.98 seconds
Started	Apr 30 03:21:14 PM PDT 24
Finished	Apr 30 03:22:57 PM PDT 24
Peak memory	240804 kb
Host	smart-8399ae40-4db4-4008-bc72-db68e28c9ab6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4199055926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4199055926
Directory	/workspace/28.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/28.spi_device_intercept.411953938
Short name	T311
Test name
Test status
Simulation time	6560681195 ps
CPU time	19.73 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:38 PM PDT 24
Peak memory	218928 kb
Host	smart-8e0f535c-8810-4b04-9600-b7c12f553fd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411953938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.411953938
Directory	/workspace/28.spi_device_intercept/latest

Test location	/workspace/coverage/default/28.spi_device_read_buffer_direct.1335867092
Short name	T520
Test name
Test status
Simulation time	3080623267 ps
CPU time	9.36 seconds
Started	Apr 30 03:21:18 PM PDT 24
Finished	Apr 30 03:21:28 PM PDT 24
Peak memory	223176 kb
Host	smart-b1333542-2eea-45d6-b4b8-23ad15889749
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1335867092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir ect.1335867092
Directory	/workspace/28.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_all.2084057907
Short name	T665
Test name
Test status
Simulation time	19745209131 ps
CPU time	19 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:37 PM PDT 24
Peak memory	216372 kb
Host	smart-641210d4-c483-4b29-bd97-ee8d767a3b3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2084057907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2084057907
Directory	/workspace/28.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_rw.2224613084
Short name	T550
Test name
Test status
Simulation time	59746251 ps
CPU time	2.94 seconds
Started	Apr 30 03:21:16 PM PDT 24
Finished	Apr 30 03:21:20 PM PDT 24
Peak memory	216368 kb
Host	smart-d7ab4552-7e81-499c-b58f-9dd897688821
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224613084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2224613084
Directory	/workspace/28.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/28.spi_device_tpm_sts_read.1206808454
Short name	T586
Test name
Test status
Simulation time	26978255 ps
CPU time	0.78 seconds
Started	Apr 30 03:21:19 PM PDT 24
Finished	Apr 30 03:21:21 PM PDT 24
Peak memory	205800 kb
Host	smart-9b0baf8b-0231-43f0-8095-c476eea26b49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206808454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1206808454
Directory	/workspace/28.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/28.spi_device_upload.3963501928
Short name	T170
Test name
Test status
Simulation time	1128836563 ps
CPU time	8.02 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:26 PM PDT 24
Peak memory	223556 kb
Host	smart-114b07f3-21cc-488f-b370-4dad107eec05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963501928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3963501928
Directory	/workspace/28.spi_device_upload/latest

Test location	/workspace/coverage/default/29.spi_device_alert_test.1151078143
Short name	T489
Test name
Test status
Simulation time	12642962 ps
CPU time	0.69 seconds
Started	Apr 30 03:21:23 PM PDT 24
Finished	Apr 30 03:21:25 PM PDT 24
Peak memory	205624 kb
Host	smart-f18243d5-c59d-4654-bf52-9e5f0a749e43
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151078143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test. 1151078143
Directory	/workspace/29.spi_device_alert_test/latest

Test location	/workspace/coverage/default/29.spi_device_cfg_cmd.855474279
Short name	T628
Test name
Test status
Simulation time	892497290 ps
CPU time	3.55 seconds
Started	Apr 30 03:21:16 PM PDT 24
Finished	Apr 30 03:21:20 PM PDT 24
Peak memory	224548 kb
Host	smart-86eaef83-c93c-4708-99b4-ad25f4af4c9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855474279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.855474279
Directory	/workspace/29.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/29.spi_device_csb_read.731568466
Short name	T460
Test name
Test status
Simulation time	22002290 ps
CPU time	0.85 seconds
Started	Apr 30 03:21:16 PM PDT 24
Finished	Apr 30 03:21:18 PM PDT 24
Peak memory	206644 kb
Host	smart-1d813038-768c-4062-a706-0bec04ca93ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731568466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.731568466
Directory	/workspace/29.spi_device_csb_read/latest

Test location	/workspace/coverage/default/29.spi_device_intercept.1206794382
Short name	T201
Test name
Test status
Simulation time	134954740 ps
CPU time	3.86 seconds
Started	Apr 30 03:21:19 PM PDT 24
Finished	Apr 30 03:21:23 PM PDT 24
Peak memory	222964 kb
Host	smart-76b0be34-ee2b-4f7a-9279-d14efe70af0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206794382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1206794382
Directory	/workspace/29.spi_device_intercept/latest

Test location	/workspace/coverage/default/29.spi_device_mailbox.3898684091
Short name	T243
Test name
Test status
Simulation time	3833937578 ps
CPU time	11.3 seconds
Started	Apr 30 03:21:20 PM PDT 24
Finished	Apr 30 03:21:32 PM PDT 24
Peak memory	237512 kb
Host	smart-cc596d87-d630-4ea7-98ef-2b18631bbab4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898684091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3898684091
Directory	/workspace/29.spi_device_mailbox/latest

Test location	/workspace/coverage/default/29.spi_device_pass_cmd_filtering.3581659561
Short name	T208
Test name
Test status
Simulation time	1712050282 ps
CPU time	8.68 seconds
Started	Apr 30 03:21:17 PM PDT 24
Finished	Apr 30 03:21:27 PM PDT 24
Peak memory	233072 kb
Host	smart-756a933c-ed09-4be2-8086-a0bdadf6dffc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3581659561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3581659561
Directory	/workspace/29.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/29.spi_device_read_buffer_direct.3234217754
Short name	T621
Test name
Test status
Simulation time	1577417275 ps
CPU time	13.33 seconds
Started	Apr 30 03:21:18 PM PDT 24
Finished	Apr 30 03:21:33 PM PDT 24
Peak memory	222800 kb
Host	smart-ef8bd661-8d93-41f8-abe6-28b51ea6ef50
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3234217754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir ect.3234217754
Directory	/workspace/29.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3249374116
Short name	T593
Test name
Test status
Simulation time	6949592100 ps
CPU time	18.51 seconds
Started	Apr 30 03:21:14 PM PDT 24
Finished	Apr 30 03:21:33 PM PDT 24
Peak memory	216352 kb
Host	smart-2034f5d1-ec63-4b47-9d67-7c610181e360
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249374116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3249374116
Directory	/workspace/29.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_rw.3292835263
Short name	T570
Test name
Test status
Simulation time	16649641 ps
CPU time	0.8 seconds
Started	Apr 30 03:21:16 PM PDT 24
Finished	Apr 30 03:21:18 PM PDT 24
Peak memory	205764 kb
Host	smart-77ba27a2-7e89-4969-875a-7561fe86b628
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292835263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3292835263
Directory	/workspace/29.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/29.spi_device_tpm_sts_read.62275623
Short name	T537
Test name
Test status
Simulation time	40294936 ps
CPU time	0.91 seconds
Started	Apr 30 03:21:14 PM PDT 24
Finished	Apr 30 03:21:16 PM PDT 24
Peak memory	206812 kb
Host	smart-ecaef87c-b689-4b73-8fb6-fa30a96196f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62275623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.62275623
Directory	/workspace/29.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/3.spi_device_alert_test.2459151479
Short name	T532
Test name
Test status
Simulation time	50937939 ps
CPU time	0.72 seconds
Started	Apr 30 03:19:50 PM PDT 24
Finished	Apr 30 03:19:51 PM PDT 24
Peak memory	205728 kb
Host	smart-5c5f1a6a-d0b7-4a9f-8a3b-aebb7a17d014
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459151479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2 459151479
Directory	/workspace/3.spi_device_alert_test/latest

Test location	/workspace/coverage/default/3.spi_device_csb_read.3960902660
Short name	T583
Test name
Test status
Simulation time	17186294 ps
CPU time	0.82 seconds
Started	Apr 30 03:19:46 PM PDT 24
Finished	Apr 30 03:19:47 PM PDT 24
Peak memory	205660 kb
Host	smart-92081c04-4c48-4fe7-9777-5ba51f676004
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3960902660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3960902660
Directory	/workspace/3.spi_device_csb_read/latest

Test location	/workspace/coverage/default/3.spi_device_flash_mode.453196627
Short name	T111
Test name
Test status
Simulation time	14555844671 ps
CPU time	42.2 seconds
Started	Apr 30 03:19:51 PM PDT 24
Finished	Apr 30 03:20:35 PM PDT 24
Peak memory	236800 kb
Host	smart-a06dfbc1-d5d2-4b7f-9dd5-7df90ee4c8b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=453196627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.453196627
Directory	/workspace/3.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/3.spi_device_mailbox.1374164644
Short name	T596
Test name
Test status
Simulation time	8880108283 ps
CPU time	28.98 seconds
Started	Apr 30 03:19:59 PM PDT 24
Finished	Apr 30 03:20:29 PM PDT 24
Peak memory	236168 kb
Host	smart-7e732b11-2324-4262-af3a-08c472a5ff0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374164644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1374164644
Directory	/workspace/3.spi_device_mailbox/latest

Test location	/workspace/coverage/default/3.spi_device_pass_cmd_filtering.903556312
Short name	T302
Test name
Test status
Simulation time	6269885951 ps
CPU time	28.9 seconds
Started	Apr 30 03:19:51 PM PDT 24
Finished	Apr 30 03:20:21 PM PDT 24
Peak memory	249076 kb
Host	smart-0f416f5f-f458-4fc1-8eaf-736b43e08fa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903556312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.903556312
Directory	/workspace/3.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/3.spi_device_read_buffer_direct.1680613836
Short name	T504
Test name
Test status
Simulation time	4133265725 ps
CPU time	11.89 seconds
Started	Apr 30 03:19:51 PM PDT 24
Finished	Apr 30 03:20:03 PM PDT 24
Peak memory	221564 kb
Host	smart-15271631-dab4-4a82-ae9d-dd1630cee679
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1680613836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire ct.1680613836
Directory	/workspace/3.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/3.spi_device_sec_cm.3645492821
Short name	T46
Test name
Test status
Simulation time	262466011 ps
CPU time	1.07 seconds
Started	Apr 30 03:19:53 PM PDT 24
Finished	Apr 30 03:19:56 PM PDT 24
Peak memory	235004 kb
Host	smart-9b8637fc-8540-4b67-b802-185a2fc32669
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645492821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3645492821
Directory	/workspace/3.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_all.631102951
Short name	T400
Test name
Test status
Simulation time	12876496882 ps
CPU time	33.62 seconds
Started	Apr 30 03:19:51 PM PDT 24
Finished	Apr 30 03:20:26 PM PDT 24
Peak memory	216700 kb
Host	smart-ed359dd2-ca5b-49fa-b0e2-16c3892ad432
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631102951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.631102951
Directory	/workspace/3.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3492008547
Short name	T568
Test name
Test status
Simulation time	1707072199 ps
CPU time	5.7 seconds
Started	Apr 30 03:19:58 PM PDT 24
Finished	Apr 30 03:20:05 PM PDT 24
Peak memory	216232 kb
Host	smart-d0b845e7-8a71-4088-b309-9ee88c263456
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492008547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3492008547
Directory	/workspace/3.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_rw.2571800069
Short name	T416
Test name
Test status
Simulation time	165479923 ps
CPU time	2.79 seconds
Started	Apr 30 03:19:56 PM PDT 24
Finished	Apr 30 03:19:59 PM PDT 24
Peak memory	216212 kb
Host	smart-306046e7-9734-4c3d-ba83-aea67e318e63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2571800069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2571800069
Directory	/workspace/3.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/3.spi_device_tpm_sts_read.1210452078
Short name	T15
Test name
Test status
Simulation time	209095423 ps
CPU time	1.33 seconds
Started	Apr 30 03:19:50 PM PDT 24
Finished	Apr 30 03:19:53 PM PDT 24
Peak memory	206784 kb
Host	smart-6dbef957-6f9e-401d-9b30-14231b878065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210452078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1210452078
Directory	/workspace/3.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/30.spi_device_alert_test.2449333765
Short name	T512
Test name
Test status
Simulation time	13600627 ps
CPU time	0.7 seconds
Started	Apr 30 03:21:28 PM PDT 24
Finished	Apr 30 03:21:29 PM PDT 24
Peak memory	205312 kb
Host	smart-940525ff-c44a-49a4-88ad-b607ae95dcc3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449333765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test. 2449333765
Directory	/workspace/30.spi_device_alert_test/latest

Test location	/workspace/coverage/default/30.spi_device_cfg_cmd.987451014
Short name	T308
Test name
Test status
Simulation time	203048524 ps
CPU time	2.35 seconds
Started	Apr 30 03:21:22 PM PDT 24
Finished	Apr 30 03:21:26 PM PDT 24
Peak memory	219108 kb
Host	smart-524deb49-2e6f-4ebd-a646-ad727db56b43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987451014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.987451014
Directory	/workspace/30.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/30.spi_device_csb_read.1274030924
Short name	T485
Test name
Test status
Simulation time	70718216 ps
CPU time	0.81 seconds
Started	Apr 30 03:21:29 PM PDT 24
Finished	Apr 30 03:21:30 PM PDT 24
Peak memory	206660 kb
Host	smart-948d8cbb-699e-48dc-b10c-00541b07949e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274030924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1274030924
Directory	/workspace/30.spi_device_csb_read/latest

Test location	/workspace/coverage/default/30.spi_device_flash_mode.222766955
Short name	T371
Test name
Test status
Simulation time	6999862087 ps
CPU time	82.99 seconds
Started	Apr 30 03:21:29 PM PDT 24
Finished	Apr 30 03:22:53 PM PDT 24
Peak memory	249068 kb
Host	smart-36211b21-a858-4863-aaf8-2fa5fe0cb426
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=222766955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.222766955
Directory	/workspace/30.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/30.spi_device_intercept.792040377
Short name	T258
Test name
Test status
Simulation time	2360637933 ps
CPU time	19.57 seconds
Started	Apr 30 03:21:25 PM PDT 24
Finished	Apr 30 03:21:46 PM PDT 24
Peak memory	232652 kb
Host	smart-a1fb0a5a-41a6-4c6e-bc99-8c15c3a48b55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792040377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.792040377
Directory	/workspace/30.spi_device_intercept/latest

Test location	/workspace/coverage/default/30.spi_device_read_buffer_direct.1266915114
Short name	T503
Test name
Test status
Simulation time	5348412459 ps
CPU time	15.13 seconds
Started	Apr 30 03:21:23 PM PDT 24
Finished	Apr 30 03:21:39 PM PDT 24
Peak memory	223020 kb
Host	smart-6efdef5d-78f7-498d-b4d4-a8bd8605fcd9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1266915114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir ect.1266915114
Directory	/workspace/30.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_all.4114562189
Short name	T409
Test name
Test status
Simulation time	16224006294 ps
CPU time	41.88 seconds
Started	Apr 30 03:21:21 PM PDT 24
Finished	Apr 30 03:22:04 PM PDT 24
Peak memory	216404 kb
Host	smart-301843d2-2d21-478e-8af2-b38144f3f3f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114562189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4114562189
Directory	/workspace/30.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3015691880
Short name	T488
Test name
Test status
Simulation time	65635777261 ps
CPU time	21.38 seconds
Started	Apr 30 03:21:22 PM PDT 24
Finished	Apr 30 03:21:44 PM PDT 24
Peak memory	216120 kb
Host	smart-13eaf73a-5eec-4d1b-bf16-c00891183860
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015691880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3015691880
Directory	/workspace/30.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_rw.1596534530
Short name	T14
Test name
Test status
Simulation time	78194108 ps
CPU time	0.91 seconds
Started	Apr 30 03:21:21 PM PDT 24
Finished	Apr 30 03:21:23 PM PDT 24
Peak memory	206796 kb
Host	smart-a099ec1f-86bb-444f-8a44-044ae2bce778
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596534530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1596534530
Directory	/workspace/30.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/30.spi_device_tpm_sts_read.391078963
Short name	T720
Test name
Test status
Simulation time	545069209 ps
CPU time	0.93 seconds
Started	Apr 30 03:21:23 PM PDT 24
Finished	Apr 30 03:21:25 PM PDT 24
Peak memory	205716 kb
Host	smart-c9e431e8-16c3-4ff3-a64e-9baf05d8c91e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391078963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.391078963
Directory	/workspace/30.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/30.spi_device_upload.1846214460
Short name	T702
Test name
Test status
Simulation time	6006247090 ps
CPU time	12.96 seconds
Started	Apr 30 03:21:30 PM PDT 24
Finished	Apr 30 03:21:44 PM PDT 24
Peak memory	223064 kb
Host	smart-645c3dd6-0fae-4e2c-8cb5-ce2eb32ba210
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846214460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1846214460
Directory	/workspace/30.spi_device_upload/latest

Test location	/workspace/coverage/default/31.spi_device_alert_test.1893241706
Short name	T652
Test name
Test status
Simulation time	17941402 ps
CPU time	0.66 seconds
Started	Apr 30 03:21:24 PM PDT 24
Finished	Apr 30 03:21:26 PM PDT 24
Peak memory	205676 kb
Host	smart-5df336fc-3ac2-4716-8945-d616228665db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893241706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test. 1893241706
Directory	/workspace/31.spi_device_alert_test/latest

Test location	/workspace/coverage/default/31.spi_device_csb_read.2949265887
Short name	T549
Test name
Test status
Simulation time	129784788 ps
CPU time	0.74 seconds
Started	Apr 30 03:21:21 PM PDT 24
Finished	Apr 30 03:21:22 PM PDT 24
Peak memory	206684 kb
Host	smart-15094c2f-4ab0-4339-ae56-3adb9059b297
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949265887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2949265887
Directory	/workspace/31.spi_device_csb_read/latest

Test location	/workspace/coverage/default/31.spi_device_flash_mode.2045381741
Short name	T373
Test name
Test status
Simulation time	1617213326 ps
CPU time	23.3 seconds
Started	Apr 30 03:21:23 PM PDT 24
Finished	Apr 30 03:21:48 PM PDT 24
Peak memory	242792 kb
Host	smart-29a58c18-08f6-41ac-bec2-5bcd09378c8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045381741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2045381741
Directory	/workspace/31.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/31.spi_device_intercept.3605023909
Short name	T535
Test name
Test status
Simulation time	586483907 ps
CPU time	3.59 seconds
Started	Apr 30 03:21:27 PM PDT 24
Finished	Apr 30 03:21:31 PM PDT 24
Peak memory	218620 kb
Host	smart-c83fd595-bbac-42b6-b01a-87d4f4720ef1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605023909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3605023909
Directory	/workspace/31.spi_device_intercept/latest

Test location	/workspace/coverage/default/31.spi_device_mailbox.236287761
Short name	T299
Test name
Test status
Simulation time	93410815102 ps
CPU time	205.17 seconds
Started	Apr 30 03:21:22 PM PDT 24
Finished	Apr 30 03:24:48 PM PDT 24
Peak memory	232316 kb
Host	smart-e12b5a1a-f98a-4275-9d2c-82ebada76fbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236287761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.236287761
Directory	/workspace/31.spi_device_mailbox/latest

Test location	/workspace/coverage/default/31.spi_device_pass_cmd_filtering.523243042
Short name	T189
Test name
Test status
Simulation time	1249424330 ps
CPU time	4.35 seconds
Started	Apr 30 03:21:26 PM PDT 24
Finished	Apr 30 03:21:31 PM PDT 24
Peak memory	222808 kb
Host	smart-8d77ac4b-c161-4034-ac52-0f80a963aa5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=523243042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.523243042
Directory	/workspace/31.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/31.spi_device_read_buffer_direct.3232064890
Short name	T429
Test name
Test status
Simulation time	2992980987 ps
CPU time	15.69 seconds
Started	Apr 30 03:21:23 PM PDT 24
Finished	Apr 30 03:21:40 PM PDT 24
Peak memory	220184 kb
Host	smart-399655eb-66fa-4111-88cf-c8a3e44f2795
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3232064890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir ect.3232064890
Directory	/workspace/31.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_all.3076552807
Short name	T393
Test name
Test status
Simulation time	5209271632 ps
CPU time	20 seconds
Started	Apr 30 03:21:28 PM PDT 24
Finished	Apr 30 03:21:48 PM PDT 24
Peak memory	216276 kb
Host	smart-99cc8cb2-98cf-4808-b5bf-03ecae448d01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3076552807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3076552807
Directory	/workspace/31.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1928409705
Short name	T607
Test name
Test status
Simulation time	6377943356 ps
CPU time	9.73 seconds
Started	Apr 30 03:21:25 PM PDT 24
Finished	Apr 30 03:21:36 PM PDT 24
Peak memory	216392 kb
Host	smart-db8dbd82-4abd-45e7-9870-1e20877ce0e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1928409705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1928409705
Directory	/workspace/31.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_rw.2269832804
Short name	T406
Test name
Test status
Simulation time	4791496869 ps
CPU time	6.15 seconds
Started	Apr 30 03:21:25 PM PDT 24
Finished	Apr 30 03:21:32 PM PDT 24
Peak memory	216440 kb
Host	smart-bc0a3d31-9fba-4629-a22e-48b03ffd5c8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2269832804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2269832804
Directory	/workspace/31.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/31.spi_device_tpm_sts_read.2050790056
Short name	T554
Test name
Test status
Simulation time	46450543 ps
CPU time	0.76 seconds
Started	Apr 30 03:21:27 PM PDT 24
Finished	Apr 30 03:21:29 PM PDT 24
Peak memory	205728 kb
Host	smart-f86a7841-5620-4aed-a47e-f73b8482e51e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050790056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2050790056
Directory	/workspace/31.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/31.spi_device_upload.1781936706
Short name	T221
Test name
Test status
Simulation time	37001857 ps
CPU time	2.48 seconds
Started	Apr 30 03:21:24 PM PDT 24
Finished	Apr 30 03:21:28 PM PDT 24
Peak memory	222064 kb
Host	smart-90451794-0fd0-4be4-86ca-d300a2fe606e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781936706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1781936706
Directory	/workspace/31.spi_device_upload/latest

Test location	/workspace/coverage/default/32.spi_device_alert_test.2505193948
Short name	T521
Test name
Test status
Simulation time	94986307 ps
CPU time	0.7 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:21:35 PM PDT 24
Peak memory	205744 kb
Host	smart-801c8753-7fd6-4024-adff-8e6666c62ed4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505193948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test. 2505193948
Directory	/workspace/32.spi_device_alert_test/latest

Test location	/workspace/coverage/default/32.spi_device_cfg_cmd.2368667317
Short name	T577
Test name
Test status
Simulation time	102983560 ps
CPU time	2.69 seconds
Started	Apr 30 03:21:35 PM PDT 24
Finished	Apr 30 03:21:39 PM PDT 24
Peak memory	218780 kb
Host	smart-597cef41-050c-4fa8-94e0-1fc02db3af64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368667317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2368667317
Directory	/workspace/32.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/32.spi_device_csb_read.2221760475
Short name	T428
Test name
Test status
Simulation time	81195096 ps
CPU time	0.8 seconds
Started	Apr 30 03:21:25 PM PDT 24
Finished	Apr 30 03:21:27 PM PDT 24
Peak memory	207040 kb
Host	smart-a74b34ba-c92f-4f1a-a753-c9e2603cc02a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221760475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2221760475
Directory	/workspace/32.spi_device_csb_read/latest

Test location	/workspace/coverage/default/32.spi_device_intercept.1529616777
Short name	T244
Test name
Test status
Simulation time	281041621 ps
CPU time	5.31 seconds
Started	Apr 30 03:21:33 PM PDT 24
Finished	Apr 30 03:21:39 PM PDT 24
Peak memory	218668 kb
Host	smart-3837c790-418a-4d03-b980-0a270196200f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529616777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1529616777
Directory	/workspace/32.spi_device_intercept/latest

Test location	/workspace/coverage/default/32.spi_device_mailbox.2154696903
Short name	T253
Test name
Test status
Simulation time	12389113216 ps
CPU time	30.54 seconds
Started	Apr 30 03:21:35 PM PDT 24
Finished	Apr 30 03:22:06 PM PDT 24
Peak memory	232684 kb
Host	smart-4fb3469f-a892-44c8-8d4e-8557224e3887
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154696903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2154696903
Directory	/workspace/32.spi_device_mailbox/latest

Test location	/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3861563518
Short name	T255
Test name
Test status
Simulation time	642897014 ps
CPU time	5.98 seconds
Started	Apr 30 03:21:33 PM PDT 24
Finished	Apr 30 03:21:40 PM PDT 24
Peak memory	224384 kb
Host	smart-56f2d3e9-9506-4d51-9a6d-f82f3edc26a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861563518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa p.3861563518
Directory	/workspace/32.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/32.spi_device_pass_cmd_filtering.2023567615
Short name	T718
Test name
Test status
Simulation time	1455540182 ps
CPU time	2.6 seconds
Started	Apr 30 03:21:33 PM PDT 24
Finished	Apr 30 03:21:37 PM PDT 24
Peak memory	219628 kb
Host	smart-f5bc2afe-75d1-4472-ad55-512e4f793940
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2023567615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2023567615
Directory	/workspace/32.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/32.spi_device_read_buffer_direct.1545249154
Short name	T609
Test name
Test status
Simulation time	3130319157 ps
CPU time	9.13 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:21:44 PM PDT 24
Peak memory	220608 kb
Host	smart-81cf0c27-c572-4e21-9105-6e6058e6a598
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1545249154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir ect.1545249154
Directory	/workspace/32.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_all.3814325872
Short name	T398
Test name
Test status
Simulation time	14151419338 ps
CPU time	27.86 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:22:03 PM PDT 24
Peak memory	216472 kb
Host	smart-b614e142-753f-4586-b9df-d274f4787f37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3814325872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3814325872
Directory	/workspace/32.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4235879753
Short name	T623
Test name
Test status
Simulation time	34723023461 ps
CPU time	17.76 seconds
Started	Apr 30 03:21:25 PM PDT 24
Finished	Apr 30 03:21:44 PM PDT 24
Peak memory	216188 kb
Host	smart-c0fa03d9-4d4a-4e83-962a-c2c61d7a515e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235879753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4235879753
Directory	/workspace/32.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_rw.2100392101
Short name	T589
Test name
Test status
Simulation time	12933312 ps
CPU time	0.73 seconds
Started	Apr 30 03:21:35 PM PDT 24
Finished	Apr 30 03:21:36 PM PDT 24
Peak memory	205856 kb
Host	smart-68d41f55-a1a1-4988-b539-df635a761163
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100392101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2100392101
Directory	/workspace/32.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/32.spi_device_tpm_sts_read.3333205313
Short name	T440
Test name
Test status
Simulation time	137370519 ps
CPU time	1.05 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:21:36 PM PDT 24
Peak memory	206772 kb
Host	smart-7710f7bf-0810-43ce-b3d2-1f344af339d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333205313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3333205313
Directory	/workspace/32.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/32.spi_device_upload.2709797912
Short name	T365
Test name
Test status
Simulation time	3798016406 ps
CPU time	7.08 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:21:42 PM PDT 24
Peak memory	222520 kb
Host	smart-e3d6c285-2231-4159-9cd1-a151d6b6552c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709797912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2709797912
Directory	/workspace/32.spi_device_upload/latest

Test location	/workspace/coverage/default/33.spi_device_alert_test.1358642183
Short name	T492
Test name
Test status
Simulation time	24977567 ps
CPU time	0.69 seconds
Started	Apr 30 03:21:33 PM PDT 24
Finished	Apr 30 03:21:35 PM PDT 24
Peak memory	204816 kb
Host	smart-98a27980-b85d-416b-a8a0-b0fc7ed6e764
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358642183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test. 1358642183
Directory	/workspace/33.spi_device_alert_test/latest

Test location	/workspace/coverage/default/33.spi_device_csb_read.1336160975
Short name	T171
Test name
Test status
Simulation time	69673665 ps
CPU time	0.75 seconds
Started	Apr 30 03:21:37 PM PDT 24
Finished	Apr 30 03:21:38 PM PDT 24
Peak memory	206936 kb
Host	smart-16546aa7-87f4-447b-b04f-ed6565eb57ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336160975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1336160975
Directory	/workspace/33.spi_device_csb_read/latest

Test location	/workspace/coverage/default/33.spi_device_flash_mode.3741507797
Short name	T342
Test name
Test status
Simulation time	11170362677 ps
CPU time	51.14 seconds
Started	Apr 30 03:21:32 PM PDT 24
Finished	Apr 30 03:22:23 PM PDT 24
Peak memory	250160 kb
Host	smart-04850054-39d1-49eb-81e0-1a49854590a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3741507797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3741507797
Directory	/workspace/33.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/33.spi_device_intercept.1168482734
Short name	T183
Test name
Test status
Simulation time	10743460887 ps
CPU time	26.97 seconds
Started	Apr 30 03:21:33 PM PDT 24
Finished	Apr 30 03:22:01 PM PDT 24
Peak memory	218872 kb
Host	smart-7fe3189c-e939-433f-aa42-715f4ad0bc0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168482734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1168482734
Directory	/workspace/33.spi_device_intercept/latest

Test location	/workspace/coverage/default/33.spi_device_mailbox.3540740633
Short name	T278
Test name
Test status
Simulation time	11597849293 ps
CPU time	40 seconds
Started	Apr 30 03:21:33 PM PDT 24
Finished	Apr 30 03:22:14 PM PDT 24
Peak memory	233728 kb
Host	smart-ee21a24a-95aa-4121-9eaa-86751283dbef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540740633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3540740633
Directory	/workspace/33.spi_device_mailbox/latest

Test location	/workspace/coverage/default/33.spi_device_read_buffer_direct.3930406308
Short name	T664
Test name
Test status
Simulation time	598785544 ps
CPU time	3.75 seconds
Started	Apr 30 03:21:35 PM PDT 24
Finished	Apr 30 03:21:39 PM PDT 24
Peak memory	220016 kb
Host	smart-43f534d5-8db1-48d6-a32e-1ac7a28e5e83
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3930406308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir ect.3930406308
Directory	/workspace/33.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_all.3592818397
Short name	T394
Test name
Test status
Simulation time	11620870214 ps
CPU time	17.41 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:21:53 PM PDT 24
Peak memory	216284 kb
Host	smart-452e0be4-5471-4851-967e-be68adfcf559
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592818397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3592818397
Directory	/workspace/33.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_read_hw_reg.251279083
Short name	T730
Test name
Test status
Simulation time	12234983192 ps
CPU time	18.21 seconds
Started	Apr 30 03:21:32 PM PDT 24
Finished	Apr 30 03:21:50 PM PDT 24
Peak memory	216616 kb
Host	smart-cf26b481-535d-4709-be1c-d76a1d912d58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251279083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.251279083
Directory	/workspace/33.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_rw.3012605240
Short name	T20
Test name
Test status
Simulation time	213784135 ps
CPU time	3.72 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:21:38 PM PDT 24
Peak memory	216236 kb
Host	smart-9e966e5e-2f42-4c68-bfa3-9aa2aff697e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012605240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3012605240
Directory	/workspace/33.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/33.spi_device_tpm_sts_read.3936964794
Short name	T427
Test name
Test status
Simulation time	44194639 ps
CPU time	0.87 seconds
Started	Apr 30 03:21:32 PM PDT 24
Finished	Apr 30 03:21:34 PM PDT 24
Peak memory	206848 kb
Host	smart-9887614f-5059-45b3-a646-68283ba63655
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936964794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3936964794
Directory	/workspace/33.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/34.spi_device_alert_test.1049212444
Short name	T704
Test name
Test status
Simulation time	43889547 ps
CPU time	0.73 seconds
Started	Apr 30 03:21:43 PM PDT 24
Finished	Apr 30 03:21:44 PM PDT 24
Peak memory	205384 kb
Host	smart-6b86bedb-49f9-4d7c-8052-dbaa0a9370cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049212444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test. 1049212444
Directory	/workspace/34.spi_device_alert_test/latest

Test location	/workspace/coverage/default/34.spi_device_csb_read.2263402714
Short name	T567
Test name
Test status
Simulation time	20774879 ps
CPU time	0.77 seconds
Started	Apr 30 03:21:33 PM PDT 24
Finished	Apr 30 03:21:35 PM PDT 24
Peak memory	206656 kb
Host	smart-cd982aa4-9054-43ea-8d26-159cf21e73f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263402714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2263402714
Directory	/workspace/34.spi_device_csb_read/latest

Test location	/workspace/coverage/default/34.spi_device_flash_mode.1891708330
Short name	T368
Test name
Test status
Simulation time	189741610 ps
CPU time	8.26 seconds
Started	Apr 30 03:21:44 PM PDT 24
Finished	Apr 30 03:21:53 PM PDT 24
Peak memory	233772 kb
Host	smart-2e2ee0c7-2510-4e3e-9550-112efce1edc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1891708330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1891708330
Directory	/workspace/34.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/34.spi_device_intercept.3502249931
Short name	T120
Test name
Test status
Simulation time	2912080236 ps
CPU time	17.83 seconds
Started	Apr 30 03:21:45 PM PDT 24
Finished	Apr 30 03:22:03 PM PDT 24
Peak memory	216720 kb
Host	smart-a8214b1a-36a6-4f73-b01a-fadcda2ec624
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502249931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3502249931
Directory	/workspace/34.spi_device_intercept/latest

Test location	/workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2901577955
Short name	T331
Test name
Test status
Simulation time	264151892 ps
CPU time	5.47 seconds
Started	Apr 30 03:21:40 PM PDT 24
Finished	Apr 30 03:21:46 PM PDT 24
Peak memory	223848 kb
Host	smart-698f7240-33c6-46aa-8fc3-ecdd7dce6053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901577955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa p.2901577955
Directory	/workspace/34.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/34.spi_device_pass_cmd_filtering.2953199007
Short name	T277
Test name
Test status
Simulation time	43359125365 ps
CPU time	45.97 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:22:21 PM PDT 24
Peak memory	236636 kb
Host	smart-7f6bb6df-2fb4-457d-88d7-b7af13d086ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2953199007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2953199007
Directory	/workspace/34.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/34.spi_device_read_buffer_direct.4271498532
Short name	T590
Test name
Test status
Simulation time	932334232 ps
CPU time	12.1 seconds
Started	Apr 30 03:21:44 PM PDT 24
Finished	Apr 30 03:21:57 PM PDT 24
Peak memory	222116 kb
Host	smart-cca82d9a-e517-4c67-8d14-ca099c282aed
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4271498532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir ect.4271498532
Directory	/workspace/34.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/34.spi_device_stress_all.3720561111
Short name	T37
Test name
Test status
Simulation time	189787863 ps
CPU time	1 seconds
Started	Apr 30 03:21:46 PM PDT 24
Finished	Apr 30 03:21:48 PM PDT 24
Peak memory	206920 kb
Host	smart-4708a12b-7833-4e71-871e-654ee57ba702
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720561111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre ss_all.3720561111
Directory	/workspace/34.spi_device_stress_all/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_all.778159486
Short name	T676
Test name
Test status
Simulation time	20271350340 ps
CPU time	52 seconds
Started	Apr 30 03:21:37 PM PDT 24
Finished	Apr 30 03:22:30 PM PDT 24
Peak memory	216260 kb
Host	smart-d7f7d004-de09-40aa-819e-b52de90e2af5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=778159486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.778159486
Directory	/workspace/34.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2224072166
Short name	T592
Test name
Test status
Simulation time	3803977366 ps
CPU time	5.22 seconds
Started	Apr 30 03:21:33 PM PDT 24
Finished	Apr 30 03:21:39 PM PDT 24
Peak memory	216332 kb
Host	smart-b09c6c8c-b23d-4c02-af22-889d0fdea56e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224072166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2224072166
Directory	/workspace/34.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_rw.2388974401
Short name	T640
Test name
Test status
Simulation time	91032001 ps
CPU time	1.19 seconds
Started	Apr 30 03:21:34 PM PDT 24
Finished	Apr 30 03:21:36 PM PDT 24
Peak memory	207864 kb
Host	smart-a1eb8c1f-3211-4dad-aa97-acc577284798
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388974401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2388974401
Directory	/workspace/34.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/34.spi_device_tpm_sts_read.3631740743
Short name	T668
Test name
Test status
Simulation time	229552301 ps
CPU time	0.82 seconds
Started	Apr 30 03:21:36 PM PDT 24
Finished	Apr 30 03:21:37 PM PDT 24
Peak memory	205752 kb
Host	smart-b94c21ab-7d4c-40c0-a1d3-879e394dfa2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3631740743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3631740743
Directory	/workspace/34.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/35.spi_device_alert_test.532031575
Short name	T527
Test name
Test status
Simulation time	17010341 ps
CPU time	0.7 seconds
Started	Apr 30 03:21:42 PM PDT 24
Finished	Apr 30 03:21:43 PM PDT 24
Peak memory	204856 kb
Host	smart-b27c225d-93bd-4015-93b7-44dd2049a99f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532031575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.532031575
Directory	/workspace/35.spi_device_alert_test/latest

Test location	/workspace/coverage/default/35.spi_device_csb_read.2663220515
Short name	T456
Test name
Test status
Simulation time	62659337 ps
CPU time	0.84 seconds
Started	Apr 30 03:21:45 PM PDT 24
Finished	Apr 30 03:21:47 PM PDT 24
Peak memory	206668 kb
Host	smart-9efa5938-0002-4f54-ab0d-c46ab0352080
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663220515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2663220515
Directory	/workspace/35.spi_device_csb_read/latest

Test location	/workspace/coverage/default/35.spi_device_flash_mode.3380262404
Short name	T9
Test name
Test status
Simulation time	3985665826 ps
CPU time	54.14 seconds
Started	Apr 30 03:21:41 PM PDT 24
Finished	Apr 30 03:22:36 PM PDT 24
Peak memory	235924 kb
Host	smart-7d709bfe-6bc5-4c3c-9c18-8f6429ed1fdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3380262404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3380262404
Directory	/workspace/35.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/35.spi_device_intercept.826159167
Short name	T207
Test name
Test status
Simulation time	1349684500 ps
CPU time	6.76 seconds
Started	Apr 30 03:21:42 PM PDT 24
Finished	Apr 30 03:21:49 PM PDT 24
Peak memory	218896 kb
Host	smart-b35ae213-790a-4e9b-b387-7d2c149cb4f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826159167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.826159167
Directory	/workspace/35.spi_device_intercept/latest

Test location	/workspace/coverage/default/35.spi_device_mailbox.1019834874
Short name	T121
Test name
Test status
Simulation time	2893511914 ps
CPU time	10.07 seconds
Started	Apr 30 03:21:42 PM PDT 24
Finished	Apr 30 03:21:53 PM PDT 24
Peak memory	236336 kb
Host	smart-ec474353-6291-4633-92cb-a2a87c989065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019834874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1019834874
Directory	/workspace/35.spi_device_mailbox/latest

Test location	/workspace/coverage/default/35.spi_device_read_buffer_direct.276154740
Short name	T547
Test name
Test status
Simulation time	815379107 ps
CPU time	3.73 seconds
Started	Apr 30 03:21:42 PM PDT 24
Finished	Apr 30 03:21:47 PM PDT 24
Peak memory	222424 kb
Host	smart-497542dd-95de-46e6-aeb5-1ccfec83c1d1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=276154740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire ct.276154740
Directory	/workspace/35.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_all.1006805324
Short name	T401
Test name
Test status
Simulation time	8322896446 ps
CPU time	28.71 seconds
Started	Apr 30 03:21:42 PM PDT 24
Finished	Apr 30 03:22:12 PM PDT 24
Peak memory	216232 kb
Host	smart-18f369b3-417b-4c82-94e3-18e1e2389fe8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006805324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1006805324
Directory	/workspace/35.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1616422171
Short name	T541
Test name
Test status
Simulation time	776669508 ps
CPU time	6.22 seconds
Started	Apr 30 03:21:42 PM PDT 24
Finished	Apr 30 03:21:50 PM PDT 24
Peak memory	216216 kb
Host	smart-a8fcc63d-2edb-43ac-a27c-b5188d04707e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616422171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1616422171
Directory	/workspace/35.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_rw.1830467492
Short name	T522
Test name
Test status
Simulation time	44871561 ps
CPU time	1.49 seconds
Started	Apr 30 03:21:42 PM PDT 24
Finished	Apr 30 03:21:45 PM PDT 24
Peak memory	216256 kb
Host	smart-c845fe8d-6712-47d5-96b4-3ae0416ab8c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830467492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1830467492
Directory	/workspace/35.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/35.spi_device_tpm_sts_read.1522242425
Short name	T660
Test name
Test status
Simulation time	69460807 ps
CPU time	0.8 seconds
Started	Apr 30 03:21:40 PM PDT 24
Finished	Apr 30 03:21:41 PM PDT 24
Peak memory	205840 kb
Host	smart-fa76d311-1002-44f6-8f61-6225119c2864
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522242425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1522242425
Directory	/workspace/35.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/35.spi_device_upload.781770500
Short name	T314
Test name
Test status
Simulation time	646966608 ps
CPU time	3.82 seconds
Started	Apr 30 03:21:50 PM PDT 24
Finished	Apr 30 03:21:55 PM PDT 24
Peak memory	223152 kb
Host	smart-83eb632e-1c6a-437b-9647-5428c7eec9e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781770500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.781770500
Directory	/workspace/35.spi_device_upload/latest

Test location	/workspace/coverage/default/36.spi_device_alert_test.3265083695
Short name	T493
Test name
Test status
Simulation time	118227993 ps
CPU time	0.68 seconds
Started	Apr 30 03:21:52 PM PDT 24
Finished	Apr 30 03:21:53 PM PDT 24
Peak memory	205272 kb
Host	smart-24d63c0d-ab2c-4dcc-9369-a9120a8e4a49
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265083695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test. 3265083695
Directory	/workspace/36.spi_device_alert_test/latest

Test location	/workspace/coverage/default/36.spi_device_csb_read.648340359
Short name	T595
Test name
Test status
Simulation time	20696071 ps
CPU time	0.79 seconds
Started	Apr 30 03:21:40 PM PDT 24
Finished	Apr 30 03:21:41 PM PDT 24
Peak memory	206900 kb
Host	smart-2f655c98-1cb9-4aa1-88e4-c68a68020a49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648340359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.648340359
Directory	/workspace/36.spi_device_csb_read/latest

Test location	/workspace/coverage/default/36.spi_device_mailbox.3489020176
Short name	T198
Test name
Test status
Simulation time	29011481236 ps
CPU time	79.23 seconds
Started	Apr 30 03:21:43 PM PDT 24
Finished	Apr 30 03:23:03 PM PDT 24
Peak memory	224436 kb
Host	smart-6e713488-a9c7-4346-ac73-e642374b9a03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489020176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3489020176
Directory	/workspace/36.spi_device_mailbox/latest

Test location	/workspace/coverage/default/36.spi_device_read_buffer_direct.3129793674
Short name	T496
Test name
Test status
Simulation time	6361014085 ps
CPU time	9.5 seconds
Started	Apr 30 03:21:49 PM PDT 24
Finished	Apr 30 03:22:00 PM PDT 24
Peak memory	222976 kb
Host	smart-5106736b-a7a2-4345-881d-c0ea4e41c732
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3129793674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir ect.3129793674
Directory	/workspace/36.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_all.2981694558
Short name	T104
Test name
Test status
Simulation time	51675602118 ps
CPU time	34.38 seconds
Started	Apr 30 03:21:44 PM PDT 24
Finished	Apr 30 03:22:19 PM PDT 24
Peak memory	216440 kb
Host	smart-7d48f97a-ca6d-44b5-91bf-b6fe0eab09b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2981694558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2981694558
Directory	/workspace/36.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1652066327
Short name	T528
Test name
Test status
Simulation time	8076399775 ps
CPU time	6.84 seconds
Started	Apr 30 03:21:45 PM PDT 24
Finished	Apr 30 03:21:53 PM PDT 24
Peak memory	216308 kb
Host	smart-008699df-8217-4449-8432-787368362ddf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652066327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1652066327
Directory	/workspace/36.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_rw.1463939337
Short name	T413
Test name
Test status
Simulation time	827848141 ps
CPU time	7.46 seconds
Started	Apr 30 03:21:42 PM PDT 24
Finished	Apr 30 03:21:51 PM PDT 24
Peak memory	216216 kb
Host	smart-8466aa9a-821d-45b6-8598-91b8b1c6a788
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463939337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1463939337
Directory	/workspace/36.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/36.spi_device_tpm_sts_read.436213432
Short name	T536
Test name
Test status
Simulation time	667191946 ps
CPU time	0.84 seconds
Started	Apr 30 03:21:43 PM PDT 24
Finished	Apr 30 03:21:44 PM PDT 24
Peak memory	205788 kb
Host	smart-740b59de-3338-477c-a9f6-af81565b7226
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436213432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.436213432
Directory	/workspace/36.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/36.spi_device_upload.3103678528
Short name	T84
Test name
Test status
Simulation time	42696468648 ps
CPU time	23.37 seconds
Started	Apr 30 03:21:43 PM PDT 24
Finished	Apr 30 03:22:07 PM PDT 24
Peak memory	240036 kb
Host	smart-69ff904d-4705-466f-82b7-3d4353030a26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103678528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3103678528
Directory	/workspace/36.spi_device_upload/latest

Test location	/workspace/coverage/default/37.spi_device_alert_test.2159467145
Short name	T545
Test name
Test status
Simulation time	20600243 ps
CPU time	0.7 seconds
Started	Apr 30 03:21:51 PM PDT 24
Finished	Apr 30 03:21:52 PM PDT 24
Peak memory	204796 kb
Host	smart-e2151d44-e63a-4e03-ba90-da69824a77bb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159467145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test. 2159467145
Directory	/workspace/37.spi_device_alert_test/latest

Test location	/workspace/coverage/default/37.spi_device_csb_read.2876575710
Short name	T685
Test name
Test status
Simulation time	24396378 ps
CPU time	0.77 seconds
Started	Apr 30 03:21:54 PM PDT 24
Finished	Apr 30 03:21:56 PM PDT 24
Peak memory	206688 kb
Host	smart-bd9092bb-1c53-4db6-8cce-da795b66eaa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2876575710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2876575710
Directory	/workspace/37.spi_device_csb_read/latest

Test location	/workspace/coverage/default/37.spi_device_flash_mode.2665680528
Short name	T369
Test name
Test status
Simulation time	1044421905 ps
CPU time	10.35 seconds
Started	Apr 30 03:21:50 PM PDT 24
Finished	Apr 30 03:22:01 PM PDT 24
Peak memory	232612 kb
Host	smart-939487ae-01dc-4557-9e7b-5a1b26bf207f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665680528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2665680528
Directory	/workspace/37.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/37.spi_device_mailbox.3439269875
Short name	T79
Test name
Test status
Simulation time	12270134052 ps
CPU time	121.32 seconds
Started	Apr 30 03:21:50 PM PDT 24
Finished	Apr 30 03:23:52 PM PDT 24
Peak memory	229516 kb
Host	smart-bb8f9a38-f83a-4991-9ea1-99ddab7d2302
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3439269875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3439269875
Directory	/workspace/37.spi_device_mailbox/latest

Test location	/workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3723110725
Short name	T324
Test name
Test status
Simulation time	2009999215 ps
CPU time	3.89 seconds
Started	Apr 30 03:21:53 PM PDT 24
Finished	Apr 30 03:21:58 PM PDT 24
Peak memory	222900 kb
Host	smart-a82cb923-fce1-4c83-876b-d99b3fa51dbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723110725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa p.3723110725
Directory	/workspace/37.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/37.spi_device_pass_cmd_filtering.2905686447
Short name	T194
Test name
Test status
Simulation time	1301879886 ps
CPU time	6.27 seconds
Started	Apr 30 03:21:52 PM PDT 24
Finished	Apr 30 03:21:59 PM PDT 24
Peak memory	222904 kb
Host	smart-bec491ca-3303-4825-953a-c92144c4dbf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905686447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2905686447
Directory	/workspace/37.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/37.spi_device_read_buffer_direct.2066522768
Short name	T112
Test name
Test status
Simulation time	173315800 ps
CPU time	4.66 seconds
Started	Apr 30 03:21:55 PM PDT 24
Finished	Apr 30 03:22:00 PM PDT 24
Peak memory	221484 kb
Host	smart-f09c45fb-7286-4e4f-9b47-f2fe946a54e6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2066522768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir ect.2066522768
Directory	/workspace/37.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_all.749422661
Short name	T392
Test name
Test status
Simulation time	26824218724 ps
CPU time	40.04 seconds
Started	Apr 30 03:21:52 PM PDT 24
Finished	Apr 30 03:22:33 PM PDT 24
Peak memory	216548 kb
Host	smart-dfe4a6f1-dc9c-4cbb-85b6-6c1b288b7e93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749422661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.749422661
Directory	/workspace/37.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3520479546
Short name	T585
Test name
Test status
Simulation time	694223405 ps
CPU time	3.91 seconds
Started	Apr 30 03:21:51 PM PDT 24
Finished	Apr 30 03:21:56 PM PDT 24
Peak memory	216268 kb
Host	smart-baa83aa8-e1cc-487a-96a4-f2fc378ad52c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520479546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3520479546
Directory	/workspace/37.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_rw.959563829
Short name	T711
Test name
Test status
Simulation time	103774690 ps
CPU time	1.35 seconds
Started	Apr 30 03:21:51 PM PDT 24
Finished	Apr 30 03:21:52 PM PDT 24
Peak memory	216180 kb
Host	smart-66af8d09-ddc6-44df-871a-37d24bad054d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959563829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.959563829
Directory	/workspace/37.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/37.spi_device_tpm_sts_read.3269121422
Short name	T507
Test name
Test status
Simulation time	194548339 ps
CPU time	0.93 seconds
Started	Apr 30 03:21:55 PM PDT 24
Finished	Apr 30 03:21:57 PM PDT 24
Peak memory	206852 kb
Host	smart-d96c9077-162c-4d29-ade9-b8b61cc4d0e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269121422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3269121422
Directory	/workspace/37.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/38.spi_device_alert_test.924743573
Short name	T642
Test name
Test status
Simulation time	113030061 ps
CPU time	0.72 seconds
Started	Apr 30 03:22:00 PM PDT 24
Finished	Apr 30 03:22:02 PM PDT 24
Peak memory	205056 kb
Host	smart-7165d91b-34a5-4010-89ea-fab55859b55a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924743573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.924743573
Directory	/workspace/38.spi_device_alert_test/latest

Test location	/workspace/coverage/default/38.spi_device_csb_read.759493067
Short name	T431
Test name
Test status
Simulation time	27821539 ps
CPU time	0.8 seconds
Started	Apr 30 03:21:54 PM PDT 24
Finished	Apr 30 03:21:55 PM PDT 24
Peak memory	206624 kb
Host	smart-549e5bce-0b05-4a01-8517-c466b88348e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759493067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.759493067
Directory	/workspace/38.spi_device_csb_read/latest

Test location	/workspace/coverage/default/38.spi_device_flash_mode.781485267
Short name	T340
Test name
Test status
Simulation time	185221472 ps
CPU time	6.88 seconds
Started	Apr 30 03:21:51 PM PDT 24
Finished	Apr 30 03:21:59 PM PDT 24
Peak memory	224480 kb
Host	smart-1b51c716-4d20-4c8a-96bb-83880ed34e7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781485267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.781485267
Directory	/workspace/38.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/38.spi_device_intercept.1412118023
Short name	T8
Test name
Test status
Simulation time	281088566 ps
CPU time	2.83 seconds
Started	Apr 30 03:21:52 PM PDT 24
Finished	Apr 30 03:21:56 PM PDT 24
Peak memory	216716 kb
Host	smart-8887bcc5-1267-4ad2-b4d9-8daf30acecb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412118023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1412118023
Directory	/workspace/38.spi_device_intercept/latest

Test location	/workspace/coverage/default/38.spi_device_mailbox.2099728483
Short name	T319
Test name
Test status
Simulation time	2421296961 ps
CPU time	27.16 seconds
Started	Apr 30 03:21:55 PM PDT 24
Finished	Apr 30 03:22:23 PM PDT 24
Peak memory	234648 kb
Host	smart-95caf32d-b899-4212-b79b-0c499f9ec836
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099728483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2099728483
Directory	/workspace/38.spi_device_mailbox/latest

Test location	/workspace/coverage/default/38.spi_device_read_buffer_direct.3098875243
Short name	T81
Test name
Test status
Simulation time	1925571286 ps
CPU time	12.33 seconds
Started	Apr 30 03:22:05 PM PDT 24
Finished	Apr 30 03:22:18 PM PDT 24
Peak memory	221976 kb
Host	smart-450af909-ee79-430e-b288-d448e1a7c5e0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3098875243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir ect.3098875243
Directory	/workspace/38.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_all.2594837636
Short name	T719
Test name
Test status
Simulation time	22952454941 ps
CPU time	27.39 seconds
Started	Apr 30 03:21:51 PM PDT 24
Finished	Apr 30 03:22:19 PM PDT 24
Peak memory	217476 kb
Host	smart-5c11ac4d-ad90-4dd1-b75e-1b2b724f3430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594837636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2594837636
Directory	/workspace/38.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4020287324
Short name	T462
Test name
Test status
Simulation time	4402668818 ps
CPU time	6.87 seconds
Started	Apr 30 03:21:52 PM PDT 24
Finished	Apr 30 03:22:00 PM PDT 24
Peak memory	216284 kb
Host	smart-360f8958-4f84-4998-a1f4-a934c2be56ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020287324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4020287324
Directory	/workspace/38.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_rw.217994969
Short name	T630
Test name
Test status
Simulation time	717555333 ps
CPU time	4.03 seconds
Started	Apr 30 03:21:55 PM PDT 24
Finished	Apr 30 03:22:00 PM PDT 24
Peak memory	216300 kb
Host	smart-27fe9020-7c20-46e3-8168-661be0abdd4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217994969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.217994969
Directory	/workspace/38.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/38.spi_device_tpm_sts_read.1719517338
Short name	T513
Test name
Test status
Simulation time	107385179 ps
CPU time	0.86 seconds
Started	Apr 30 03:21:55 PM PDT 24
Finished	Apr 30 03:21:56 PM PDT 24
Peak memory	205772 kb
Host	smart-4bde4650-88d7-4ab0-9074-2996ba72f41a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719517338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1719517338
Directory	/workspace/38.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/38.spi_device_upload.1033978393
Short name	T257
Test name
Test status
Simulation time	8219481348 ps
CPU time	8.83 seconds
Started	Apr 30 03:21:53 PM PDT 24
Finished	Apr 30 03:22:03 PM PDT 24
Peak memory	222676 kb
Host	smart-2899dab4-a97a-4436-98a0-7dd7f8d3bd8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033978393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1033978393
Directory	/workspace/38.spi_device_upload/latest

Test location	/workspace/coverage/default/39.spi_device_alert_test.3141877203
Short name	T34
Test name
Test status
Simulation time	45639251 ps
CPU time	0.73 seconds
Started	Apr 30 03:22:05 PM PDT 24
Finished	Apr 30 03:22:07 PM PDT 24
Peak memory	204796 kb
Host	smart-2818bd19-4ec6-4046-a76c-8adda5c9a316
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141877203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test. 3141877203
Directory	/workspace/39.spi_device_alert_test/latest

Test location	/workspace/coverage/default/39.spi_device_cfg_cmd.905467127
Short name	T227
Test name
Test status
Simulation time	1444286815 ps
CPU time	5.57 seconds
Started	Apr 30 03:22:02 PM PDT 24
Finished	Apr 30 03:22:09 PM PDT 24
Peak memory	223084 kb
Host	smart-e72ad507-1561-44ac-b14c-b22b025d2b45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905467127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.905467127
Directory	/workspace/39.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/39.spi_device_csb_read.4213567037
Short name	T729
Test name
Test status
Simulation time	34875257 ps
CPU time	0.82 seconds
Started	Apr 30 03:22:05 PM PDT 24
Finished	Apr 30 03:22:07 PM PDT 24
Peak memory	205672 kb
Host	smart-4b764d96-4467-419a-b77c-a57c7874403c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4213567037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4213567037
Directory	/workspace/39.spi_device_csb_read/latest

Test location	/workspace/coverage/default/39.spi_device_flash_mode.560917424
Short name	T363
Test name
Test status
Simulation time	1890638701 ps
CPU time	9.87 seconds
Started	Apr 30 03:21:59 PM PDT 24
Finished	Apr 30 03:22:10 PM PDT 24
Peak memory	232696 kb
Host	smart-4a1ed5af-3557-42c5-a0e1-f94073e2d2d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560917424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.560917424
Directory	/workspace/39.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/39.spi_device_intercept.4218480835
Short name	T366
Test name
Test status
Simulation time	14440775641 ps
CPU time	26.88 seconds
Started	Apr 30 03:21:58 PM PDT 24
Finished	Apr 30 03:22:26 PM PDT 24
Peak memory	219304 kb
Host	smart-6bfd5afa-29d5-4034-89a7-5c36eb66ad0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4218480835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4218480835
Directory	/workspace/39.spi_device_intercept/latest

Test location	/workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3744243005
Short name	T337
Test name
Test status
Simulation time	22377054409 ps
CPU time	15.6 seconds
Started	Apr 30 03:22:00 PM PDT 24
Finished	Apr 30 03:22:16 PM PDT 24
Peak memory	219016 kb
Host	smart-7578957d-510b-48d9-9289-38b0772391c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744243005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa p.3744243005
Directory	/workspace/39.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/39.spi_device_pass_cmd_filtering.1212980124
Short name	T2
Test name
Test status
Simulation time	2352081254 ps
CPU time	8.19 seconds
Started	Apr 30 03:22:03 PM PDT 24
Finished	Apr 30 03:22:12 PM PDT 24
Peak memory	221276 kb
Host	smart-ab5fcc87-3cf1-4751-abef-cbe6a8453b47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212980124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1212980124
Directory	/workspace/39.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/39.spi_device_read_buffer_direct.864635000
Short name	T455
Test name
Test status
Simulation time	148394467 ps
CPU time	3.47 seconds
Started	Apr 30 03:22:03 PM PDT 24
Finished	Apr 30 03:22:07 PM PDT 24
Peak memory	219440 kb
Host	smart-54966ef1-4681-4911-8f5f-e9469a38505b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=864635000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire ct.864635000
Directory	/workspace/39.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/39.spi_device_stress_all.756714725
Short name	T35
Test name
Test status
Simulation time	39313295 ps
CPU time	0.91 seconds
Started	Apr 30 03:22:07 PM PDT 24
Finished	Apr 30 03:22:09 PM PDT 24
Peak memory	207092 kb
Host	smart-5748b4a8-5c77-4bd3-a913-76799e7a9d77
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756714725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres s_all.756714725
Directory	/workspace/39.spi_device_stress_all/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_all.1537399175
Short name	T23
Test name
Test status
Simulation time	7410311280 ps
CPU time	29.14 seconds
Started	Apr 30 03:22:05 PM PDT 24
Finished	Apr 30 03:22:35 PM PDT 24
Peak memory	216376 kb
Host	smart-fa91e9e2-f264-4de4-87e9-9f48174d4886
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537399175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1537399175
Directory	/workspace/39.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1798551002
Short name	T175
Test name
Test status
Simulation time	437200920 ps
CPU time	2.6 seconds
Started	Apr 30 03:22:03 PM PDT 24
Finished	Apr 30 03:22:06 PM PDT 24
Peak memory	216180 kb
Host	smart-dc343e5e-ec9f-43b4-92af-bd2f6ddfb149
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798551002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1798551002
Directory	/workspace/39.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_rw.4292997973
Short name	T683
Test name
Test status
Simulation time	186786686 ps
CPU time	1.62 seconds
Started	Apr 30 03:22:04 PM PDT 24
Finished	Apr 30 03:22:06 PM PDT 24
Peak memory	216244 kb
Host	smart-e49c5577-f7dd-41a6-9adf-9c880238e576
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292997973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4292997973
Directory	/workspace/39.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/39.spi_device_tpm_sts_read.974190751
Short name	T682
Test name
Test status
Simulation time	53941903 ps
CPU time	0.85 seconds
Started	Apr 30 03:22:03 PM PDT 24
Finished	Apr 30 03:22:05 PM PDT 24
Peak memory	205756 kb
Host	smart-470157d7-1443-4bcd-b8dc-edb16cfccd28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974190751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.974190751
Directory	/workspace/39.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/4.spi_device_alert_test.1445935638
Short name	T441
Test name
Test status
Simulation time	41871242 ps
CPU time	0.7 seconds
Started	Apr 30 03:19:50 PM PDT 24
Finished	Apr 30 03:19:52 PM PDT 24
Peak memory	205736 kb
Host	smart-8b14b37e-7a89-42a2-9c33-5289a6e854a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445935638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1 445935638
Directory	/workspace/4.spi_device_alert_test/latest

Test location	/workspace/coverage/default/4.spi_device_cfg_cmd.2254414116
Short name	T197
Test name
Test status
Simulation time	69606098 ps
CPU time	2.16 seconds
Started	Apr 30 03:19:56 PM PDT 24
Finished	Apr 30 03:20:00 PM PDT 24
Peak memory	218840 kb
Host	smart-02870907-8048-4fd2-b650-3318a18afb4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254414116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2254414116
Directory	/workspace/4.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/4.spi_device_csb_read.2669397509
Short name	T619
Test name
Test status
Simulation time	40145240 ps
CPU time	0.81 seconds
Started	Apr 30 03:19:53 PM PDT 24
Finished	Apr 30 03:19:55 PM PDT 24
Peak memory	206664 kb
Host	smart-ff3f03f0-972e-4196-b00a-a72efbd5d063
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2669397509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2669397509
Directory	/workspace/4.spi_device_csb_read/latest

Test location	/workspace/coverage/default/4.spi_device_flash_mode.3034872380
Short name	T113
Test name
Test status
Simulation time	8155875878 ps
CPU time	26.66 seconds
Started	Apr 30 03:19:53 PM PDT 24
Finished	Apr 30 03:20:21 PM PDT 24
Peak memory	257372 kb
Host	smart-0bda3434-ae01-47ce-8315-c09d387dbf9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034872380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3034872380
Directory	/workspace/4.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/4.spi_device_intercept.1689300877
Short name	T605
Test name
Test status
Simulation time	951469435 ps
CPU time	11.55 seconds
Started	Apr 30 03:19:52 PM PDT 24
Finished	Apr 30 03:20:05 PM PDT 24
Peak memory	218564 kb
Host	smart-f1130a83-f721-45ac-a581-0389832dfe5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689300877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1689300877
Directory	/workspace/4.spi_device_intercept/latest

Test location	/workspace/coverage/default/4.spi_device_pass_cmd_filtering.4018063860
Short name	T11
Test name
Test status
Simulation time	411121305 ps
CPU time	3.69 seconds
Started	Apr 30 03:19:54 PM PDT 24
Finished	Apr 30 03:19:59 PM PDT 24
Peak memory	221060 kb
Host	smart-5ffe472e-c99f-4bc7-8567-632c47780d22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018063860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4018063860
Directory	/workspace/4.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/4.spi_device_read_buffer_direct.4286073530
Short name	T610
Test name
Test status
Simulation time	304203739 ps
CPU time	5.14 seconds
Started	Apr 30 03:19:59 PM PDT 24
Finished	Apr 30 03:20:05 PM PDT 24
Peak memory	222944 kb
Host	smart-ed31370d-d1fa-4a1b-a5a6-3287734d27c8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4286073530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire ct.4286073530
Directory	/workspace/4.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/4.spi_device_sec_cm.3766983711
Short name	T47
Test name
Test status
Simulation time	125871158 ps
CPU time	0.94 seconds
Started	Apr 30 03:19:49 PM PDT 24
Finished	Apr 30 03:19:51 PM PDT 24
Peak memory	235016 kb
Host	smart-b13a2acd-b123-4a83-8296-8de4b89a15b0
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766983711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3766983711
Directory	/workspace/4.spi_device_sec_cm/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_all.2603389764
Short name	T691
Test name
Test status
Simulation time	10470812639 ps
CPU time	30.23 seconds
Started	Apr 30 03:19:50 PM PDT 24
Finished	Apr 30 03:20:21 PM PDT 24
Peak memory	218136 kb
Host	smart-43c49fd0-ab38-4c17-b269-1bd46e5ccf40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603389764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2603389764
Directory	/workspace/4.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2393376201
Short name	T110
Test name
Test status
Simulation time	3615922195 ps
CPU time	5.1 seconds
Started	Apr 30 03:20:00 PM PDT 24
Finished	Apr 30 03:20:06 PM PDT 24
Peak memory	216340 kb
Host	smart-b632269c-91bb-4fe9-8518-65b59f5be873
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393376201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2393376201
Directory	/workspace/4.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_rw.1913559757
Short name	T424
Test name
Test status
Simulation time	47249900 ps
CPU time	2.41 seconds
Started	Apr 30 03:19:52 PM PDT 24
Finished	Apr 30 03:19:55 PM PDT 24
Peak memory	216228 kb
Host	smart-9af84301-d7f6-4817-b804-091eb7690ddc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913559757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1913559757
Directory	/workspace/4.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/4.spi_device_tpm_sts_read.61705129
Short name	T638
Test name
Test status
Simulation time	118106669 ps
CPU time	1.01 seconds
Started	Apr 30 03:19:54 PM PDT 24
Finished	Apr 30 03:19:56 PM PDT 24
Peak memory	206248 kb
Host	smart-b15b3dc3-568d-4684-9c1c-ed02cc45b265
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61705129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.61705129
Directory	/workspace/4.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/40.spi_device_alert_test.731988795
Short name	T560
Test name
Test status
Simulation time	52282110 ps
CPU time	0.72 seconds
Started	Apr 30 03:22:05 PM PDT 24
Finished	Apr 30 03:22:06 PM PDT 24
Peak memory	205324 kb
Host	smart-220e7135-8192-46cb-b5df-7f2cd18abbbb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731988795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.731988795
Directory	/workspace/40.spi_device_alert_test/latest

Test location	/workspace/coverage/default/40.spi_device_csb_read.143203612
Short name	T684
Test name
Test status
Simulation time	28570315 ps
CPU time	0.82 seconds
Started	Apr 30 03:22:02 PM PDT 24
Finished	Apr 30 03:22:04 PM PDT 24
Peak memory	207004 kb
Host	smart-a8fc9f6d-f00a-445e-acc8-e5a75f22ea87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143203612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.143203612
Directory	/workspace/40.spi_device_csb_read/latest

Test location	/workspace/coverage/default/40.spi_device_flash_mode.456622318
Short name	T347
Test name
Test status
Simulation time	4198766383 ps
CPU time	22.43 seconds
Started	Apr 30 03:22:07 PM PDT 24
Finished	Apr 30 03:22:30 PM PDT 24
Peak memory	238892 kb
Host	smart-1462e435-8a08-46df-be78-4bc851242c0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456622318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.456622318
Directory	/workspace/40.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/40.spi_device_pass_cmd_filtering.592130566
Short name	T211
Test name
Test status
Simulation time	12334978631 ps
CPU time	10.73 seconds
Started	Apr 30 03:22:03 PM PDT 24
Finished	Apr 30 03:22:15 PM PDT 24
Peak memory	226712 kb
Host	smart-fb45b7ae-75ad-413f-b158-757dde7b70e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592130566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.592130566
Directory	/workspace/40.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/40.spi_device_read_buffer_direct.3483348237
Short name	T487
Test name
Test status
Simulation time	2649221687 ps
CPU time	8.34 seconds
Started	Apr 30 03:22:03 PM PDT 24
Finished	Apr 30 03:22:12 PM PDT 24
Peak memory	218924 kb
Host	smart-d47f6781-dc1d-4904-b4da-ee0e0874cd3b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3483348237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir ect.3483348237
Directory	/workspace/40.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/40.spi_device_stress_all.397718374
Short name	T673
Test name
Test status
Simulation time	73680835 ps
CPU time	0.9 seconds
Started	Apr 30 03:22:01 PM PDT 24
Finished	Apr 30 03:22:03 PM PDT 24
Peak memory	205520 kb
Host	smart-44a3b17c-3efd-4ff2-a232-0973a6110a4e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397718374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres s_all.397718374
Directory	/workspace/40.spi_device_stress_all/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_all.812856774
Short name	T410
Test name
Test status
Simulation time	526898869 ps
CPU time	2.3 seconds
Started	Apr 30 03:22:03 PM PDT 24
Finished	Apr 30 03:22:06 PM PDT 24
Peak memory	216184 kb
Host	smart-2c12470c-f5ff-493f-a7ec-0fecfc3922d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812856774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.812856774
Directory	/workspace/40.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3368348820
Short name	T569
Test name
Test status
Simulation time	5206156644 ps
CPU time	16.18 seconds
Started	Apr 30 03:22:02 PM PDT 24
Finished	Apr 30 03:22:19 PM PDT 24
Peak memory	216376 kb
Host	smart-2ba74adc-07e7-4bb5-b87b-9a8989a835ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368348820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3368348820
Directory	/workspace/40.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_rw.3492977086
Short name	T667
Test name
Test status
Simulation time	1327617946 ps
CPU time	3.7 seconds
Started	Apr 30 03:22:04 PM PDT 24
Finished	Apr 30 03:22:08 PM PDT 24
Peak memory	216164 kb
Host	smart-581cb6a3-701d-4eb9-9881-2b03e64d7337
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492977086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3492977086
Directory	/workspace/40.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/40.spi_device_tpm_sts_read.614449136
Short name	T679
Test name
Test status
Simulation time	125883598 ps
CPU time	0.97 seconds
Started	Apr 30 03:22:02 PM PDT 24
Finished	Apr 30 03:22:04 PM PDT 24
Peak memory	206752 kb
Host	smart-65584b8b-0e51-4553-9b98-3379543b5eb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614449136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.614449136
Directory	/workspace/40.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/41.spi_device_alert_test.688751088
Short name	T484
Test name
Test status
Simulation time	35520224 ps
CPU time	0.69 seconds
Started	Apr 30 03:22:09 PM PDT 24
Finished	Apr 30 03:22:10 PM PDT 24
Peak memory	205680 kb
Host	smart-825a1764-0be1-4e56-a298-516d2c27967c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688751088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.688751088
Directory	/workspace/41.spi_device_alert_test/latest

Test location	/workspace/coverage/default/41.spi_device_csb_read.2197530933
Short name	T450
Test name
Test status
Simulation time	50591578 ps
CPU time	0.79 seconds
Started	Apr 30 03:22:11 PM PDT 24
Finished	Apr 30 03:22:12 PM PDT 24
Peak memory	206716 kb
Host	smart-1cdf9a0b-c9fb-4182-8644-935d9ecbeb8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197530933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2197530933
Directory	/workspace/41.spi_device_csb_read/latest

Test location	/workspace/coverage/default/41.spi_device_intercept.1548409521
Short name	T259
Test name
Test status
Simulation time	71213123 ps
CPU time	3.38 seconds
Started	Apr 30 03:22:16 PM PDT 24
Finished	Apr 30 03:22:20 PM PDT 24
Peak memory	222676 kb
Host	smart-c794eb37-e54e-4f07-bd96-0e7e9c03cf46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548409521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1548409521
Directory	/workspace/41.spi_device_intercept/latest

Test location	/workspace/coverage/default/41.spi_device_pass_cmd_filtering.1420455514
Short name	T293
Test name
Test status
Simulation time	43885361929 ps
CPU time	32.8 seconds
Started	Apr 30 03:22:16 PM PDT 24
Finished	Apr 30 03:22:50 PM PDT 24
Peak memory	222540 kb
Host	smart-3aa42d4c-9166-43e5-972c-960fdb3df072
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420455514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1420455514
Directory	/workspace/41.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/41.spi_device_read_buffer_direct.3729887622
Short name	T726
Test name
Test status
Simulation time	818896299 ps
CPU time	5.63 seconds
Started	Apr 30 03:22:10 PM PDT 24
Finished	Apr 30 03:22:17 PM PDT 24
Peak memory	222984 kb
Host	smart-ee260036-f807-4351-a8b9-f9d30292dc2f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3729887622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir ect.3729887622
Directory	/workspace/41.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_all.3809035965
Short name	T405
Test name
Test status
Simulation time	67346371066 ps
CPU time	28.24 seconds
Started	Apr 30 03:22:17 PM PDT 24
Finished	Apr 30 03:22:46 PM PDT 24
Peak memory	216296 kb
Host	smart-145674bc-c88a-4d2f-9d06-67871f5eb49c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809035965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3809035965
Directory	/workspace/41.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2399771968
Short name	T518
Test name
Test status
Simulation time	40716039041 ps
CPU time	8.71 seconds
Started	Apr 30 03:22:11 PM PDT 24
Finished	Apr 30 03:22:20 PM PDT 24
Peak memory	216316 kb
Host	smart-b7386cd1-c51b-4126-a0e0-f50b9b0a5bc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399771968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2399771968
Directory	/workspace/41.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_rw.4189728304
Short name	T22
Test name
Test status
Simulation time	109415592 ps
CPU time	1.22 seconds
Started	Apr 30 03:22:11 PM PDT 24
Finished	Apr 30 03:22:13 PM PDT 24
Peak memory	216148 kb
Host	smart-be6b319e-d5a0-4cf1-8783-cffd1a415c09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4189728304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4189728304
Directory	/workspace/41.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/41.spi_device_tpm_sts_read.3763891150
Short name	T662
Test name
Test status
Simulation time	66517947 ps
CPU time	0.9 seconds
Started	Apr 30 03:22:12 PM PDT 24
Finished	Apr 30 03:22:13 PM PDT 24
Peak memory	206800 kb
Host	smart-060440e4-a13b-4a3f-a145-0b34503ae2e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763891150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3763891150
Directory	/workspace/41.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/41.spi_device_upload.1204392047
Short name	T312
Test name
Test status
Simulation time	2493142045 ps
CPU time	7.98 seconds
Started	Apr 30 03:22:14 PM PDT 24
Finished	Apr 30 03:22:22 PM PDT 24
Peak memory	227468 kb
Host	smart-c4e7b178-ebf6-43c1-83dd-8ec1f5497873
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204392047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1204392047
Directory	/workspace/41.spi_device_upload/latest

Test location	/workspace/coverage/default/42.spi_device_alert_test.4031796980
Short name	T571
Test name
Test status
Simulation time	31129920 ps
CPU time	0.76 seconds
Started	Apr 30 03:22:14 PM PDT 24
Finished	Apr 30 03:22:15 PM PDT 24
Peak memory	204824 kb
Host	smart-d21b549c-9ae1-47de-ae4e-14f53abfb30d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031796980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test. 4031796980
Directory	/workspace/42.spi_device_alert_test/latest

Test location	/workspace/coverage/default/42.spi_device_cfg_cmd.563711972
Short name	T29
Test name
Test status
Simulation time	111951792 ps
CPU time	2.77 seconds
Started	Apr 30 03:22:12 PM PDT 24
Finished	Apr 30 03:22:16 PM PDT 24
Peak memory	218932 kb
Host	smart-63274ff1-09a0-42a6-97dc-37a893109f70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=563711972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.563711972
Directory	/workspace/42.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/42.spi_device_csb_read.1896516877
Short name	T509
Test name
Test status
Simulation time	46482034 ps
CPU time	0.73 seconds
Started	Apr 30 03:22:15 PM PDT 24
Finished	Apr 30 03:22:17 PM PDT 24
Peak memory	205640 kb
Host	smart-aae68d56-47b3-4b8b-a81e-62bfa847c123
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896516877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1896516877
Directory	/workspace/42.spi_device_csb_read/latest

Test location	/workspace/coverage/default/42.spi_device_intercept.2313549425
Short name	T228
Test name
Test status
Simulation time	3834479980 ps
CPU time	37.14 seconds
Started	Apr 30 03:22:17 PM PDT 24
Finished	Apr 30 03:22:54 PM PDT 24
Peak memory	224452 kb
Host	smart-d5242297-1149-4154-902a-b935ce797f03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313549425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2313549425
Directory	/workspace/42.spi_device_intercept/latest

Test location	/workspace/coverage/default/42.spi_device_mailbox.1561058838
Short name	T92
Test name
Test status
Simulation time	56628067 ps
CPU time	2.38 seconds
Started	Apr 30 03:22:16 PM PDT 24
Finished	Apr 30 03:22:19 PM PDT 24
Peak memory	223044 kb
Host	smart-5c12c9ab-5835-4e66-9ecd-3a22f0bb7bce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561058838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1561058838
Directory	/workspace/42.spi_device_mailbox/latest

Test location	/workspace/coverage/default/42.spi_device_pass_addr_payload_swap.572675670
Short name	T279
Test name
Test status
Simulation time	28153473562 ps
CPU time	7.09 seconds
Started	Apr 30 03:22:12 PM PDT 24
Finished	Apr 30 03:22:20 PM PDT 24
Peak memory	216656 kb
Host	smart-6a2e4f15-c964-4c52-ba06-9100f4e3e1ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572675670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap .572675670
Directory	/workspace/42.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/42.spi_device_pass_cmd_filtering.534468774
Short name	T317
Test name
Test status
Simulation time	976816755 ps
CPU time	3.5 seconds
Started	Apr 30 03:22:13 PM PDT 24
Finished	Apr 30 03:22:17 PM PDT 24
Peak memory	221080 kb
Host	smart-b3397e68-57f8-403c-9128-956e682b6830
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534468774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.534468774
Directory	/workspace/42.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/42.spi_device_read_buffer_direct.2716179866
Short name	T60
Test name
Test status
Simulation time	354494370 ps
CPU time	4.44 seconds
Started	Apr 30 03:22:10 PM PDT 24
Finished	Apr 30 03:22:15 PM PDT 24
Peak memory	218876 kb
Host	smart-03a440b7-ed60-4f76-ae12-f55a90bea539
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2716179866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir ect.2716179866
Directory	/workspace/42.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_all.2181640970
Short name	T396
Test name
Test status
Simulation time	7695501602 ps
CPU time	38.23 seconds
Started	Apr 30 03:22:13 PM PDT 24
Finished	Apr 30 03:22:52 PM PDT 24
Peak memory	216424 kb
Host	smart-ec14bad3-e463-436d-9ffc-eca349cd1c95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181640970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2181640970
Directory	/workspace/42.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2416284642
Short name	T463
Test name
Test status
Simulation time	10923125935 ps
CPU time	17.26 seconds
Started	Apr 30 03:22:09 PM PDT 24
Finished	Apr 30 03:22:27 PM PDT 24
Peak memory	216348 kb
Host	smart-41dc9d06-1539-49b3-8e97-6043a83c0c53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416284642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2416284642
Directory	/workspace/42.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_rw.3983297888
Short name	T649
Test name
Test status
Simulation time	1180441539 ps
CPU time	2.45 seconds
Started	Apr 30 03:22:11 PM PDT 24
Finished	Apr 30 03:22:14 PM PDT 24
Peak memory	216280 kb
Host	smart-8dc3df51-02f0-4183-8712-91a33e1b0de2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3983297888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3983297888
Directory	/workspace/42.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/42.spi_device_tpm_sts_read.3185838387
Short name	T430
Test name
Test status
Simulation time	174727809 ps
CPU time	0.83 seconds
Started	Apr 30 03:22:16 PM PDT 24
Finished	Apr 30 03:22:18 PM PDT 24
Peak memory	205768 kb
Host	smart-8f567e93-77a6-4aab-a167-f18eaf758dbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3185838387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3185838387
Directory	/workspace/42.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/43.spi_device_alert_test.3887852819
Short name	T172
Test name
Test status
Simulation time	16507623 ps
CPU time	0.72 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:22 PM PDT 24
Peak memory	204816 kb
Host	smart-3af9225e-44d7-422f-96d3-33cac8d1f25f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887852819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test. 3887852819
Directory	/workspace/43.spi_device_alert_test/latest

Test location	/workspace/coverage/default/43.spi_device_csb_read.1629267578
Short name	T18
Test name
Test status
Simulation time	50866460 ps
CPU time	0.8 seconds
Started	Apr 30 03:22:09 PM PDT 24
Finished	Apr 30 03:22:10 PM PDT 24
Peak memory	206716 kb
Host	smart-b4e24226-2f0d-418d-bbeb-7b92905c2ccf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629267578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1629267578
Directory	/workspace/43.spi_device_csb_read/latest

Test location	/workspace/coverage/default/43.spi_device_flash_mode.2491059565
Short name	T345
Test name
Test status
Simulation time	13590221287 ps
CPU time	21.77 seconds
Started	Apr 30 03:22:18 PM PDT 24
Finished	Apr 30 03:22:41 PM PDT 24
Peak memory	224540 kb
Host	smart-59074ee0-7090-4b04-b658-c342c9f68b78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491059565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2491059565
Directory	/workspace/43.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/43.spi_device_intercept.2444490779
Short name	T305
Test name
Test status
Simulation time	693776594 ps
CPU time	8.09 seconds
Started	Apr 30 03:22:13 PM PDT 24
Finished	Apr 30 03:22:22 PM PDT 24
Peak memory	223420 kb
Host	smart-e1876968-63c0-41b5-875a-f351462a4b00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444490779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2444490779
Directory	/workspace/43.spi_device_intercept/latest

Test location	/workspace/coverage/default/43.spi_device_mailbox.2919858901
Short name	T588
Test name
Test status
Simulation time	3987670057 ps
CPU time	14.36 seconds
Started	Apr 30 03:22:17 PM PDT 24
Finished	Apr 30 03:22:32 PM PDT 24
Peak memory	218432 kb
Host	smart-49876aae-c44d-4b4d-b5fe-1d2c7da9b233
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2919858901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2919858901
Directory	/workspace/43.spi_device_mailbox/latest

Test location	/workspace/coverage/default/43.spi_device_pass_cmd_filtering.1980747873
Short name	T294
Test name
Test status
Simulation time	792413258 ps
CPU time	3.9 seconds
Started	Apr 30 03:22:14 PM PDT 24
Finished	Apr 30 03:22:18 PM PDT 24
Peak memory	221256 kb
Host	smart-6efeda70-ca49-4b2b-8465-13f7899866ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980747873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1980747873
Directory	/workspace/43.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/43.spi_device_read_buffer_direct.412902126
Short name	T90
Test name
Test status
Simulation time	1379554805 ps
CPU time	3.42 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:24 PM PDT 24
Peak memory	219100 kb
Host	smart-fbbe64c2-5913-4a95-b615-2f62a0988f54
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=412902126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire ct.412902126
Directory	/workspace/43.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_all.3287778342
Short name	T108
Test name
Test status
Simulation time	6256571318 ps
CPU time	31.93 seconds
Started	Apr 30 03:22:13 PM PDT 24
Finished	Apr 30 03:22:46 PM PDT 24
Peak memory	216360 kb
Host	smart-f5bae5b1-55ee-434a-b6b2-d98c6c98600a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287778342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3287778342
Directory	/workspace/43.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2096692304
Short name	T445
Test name
Test status
Simulation time	1705730570 ps
CPU time	8.52 seconds
Started	Apr 30 03:22:13 PM PDT 24
Finished	Apr 30 03:22:22 PM PDT 24
Peak memory	216220 kb
Host	smart-549a2ce9-ba65-4b8a-9ffb-5c9319c2bbbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096692304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2096692304
Directory	/workspace/43.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_rw.3513949459
Short name	T551
Test name
Test status
Simulation time	77391606 ps
CPU time	2.85 seconds
Started	Apr 30 03:22:11 PM PDT 24
Finished	Apr 30 03:22:15 PM PDT 24
Peak memory	216248 kb
Host	smart-17595f03-8b48-4a7a-a599-d65833ee0ba5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513949459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3513949459
Directory	/workspace/43.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/43.spi_device_tpm_sts_read.2018763768
Short name	T459
Test name
Test status
Simulation time	45027404 ps
CPU time	0.81 seconds
Started	Apr 30 03:22:17 PM PDT 24
Finished	Apr 30 03:22:18 PM PDT 24
Peak memory	205772 kb
Host	smart-70cd0142-a0b6-4136-990e-3b01d9593b5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018763768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2018763768
Directory	/workspace/43.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/43.spi_device_upload.3904203653
Short name	T322
Test name
Test status
Simulation time	359623728 ps
CPU time	3.45 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:25 PM PDT 24
Peak memory	223096 kb
Host	smart-dff4ffc5-3913-4fcf-b018-2df1ded0af5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904203653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3904203653
Directory	/workspace/43.spi_device_upload/latest

Test location	/workspace/coverage/default/44.spi_device_alert_test.1458063794
Short name	T622
Test name
Test status
Simulation time	26675651 ps
CPU time	0.71 seconds
Started	Apr 30 03:22:21 PM PDT 24
Finished	Apr 30 03:22:23 PM PDT 24
Peak memory	205468 kb
Host	smart-a55f1f0c-7e17-43de-afe1-b52c90ae33b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458063794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test. 1458063794
Directory	/workspace/44.spi_device_alert_test/latest

Test location	/workspace/coverage/default/44.spi_device_csb_read.3407078602
Short name	T497
Test name
Test status
Simulation time	65808864 ps
CPU time	0.78 seconds
Started	Apr 30 03:22:21 PM PDT 24
Finished	Apr 30 03:22:23 PM PDT 24
Peak memory	206720 kb
Host	smart-7c58b0e8-108c-4fc4-bbdb-399e8ab27ac3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407078602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3407078602
Directory	/workspace/44.spi_device_csb_read/latest

Test location	/workspace/coverage/default/44.spi_device_intercept.3320935450
Short name	T229
Test name
Test status
Simulation time	114835322 ps
CPU time	3.87 seconds
Started	Apr 30 03:22:18 PM PDT 24
Finished	Apr 30 03:22:23 PM PDT 24
Peak memory	219152 kb
Host	smart-bac2b7b2-6c7b-408c-ae2e-1abfbf9c1147
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320935450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3320935450
Directory	/workspace/44.spi_device_intercept/latest

Test location	/workspace/coverage/default/44.spi_device_mailbox.3680472396
Short name	T181
Test name
Test status
Simulation time	570481580 ps
CPU time	11.73 seconds
Started	Apr 30 03:22:18 PM PDT 24
Finished	Apr 30 03:22:31 PM PDT 24
Peak memory	234304 kb
Host	smart-72105673-cb95-4f84-8db2-0facdfb8f7fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680472396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3680472396
Directory	/workspace/44.spi_device_mailbox/latest

Test location	/workspace/coverage/default/44.spi_device_pass_cmd_filtering.2616862745
Short name	T223
Test name
Test status
Simulation time	19888882624 ps
CPU time	13.78 seconds
Started	Apr 30 03:22:17 PM PDT 24
Finished	Apr 30 03:22:32 PM PDT 24
Peak memory	232688 kb
Host	smart-592206fe-6133-4568-a61d-05904ac27889
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616862745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2616862745
Directory	/workspace/44.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/44.spi_device_read_buffer_direct.3706756342
Short name	T670
Test name
Test status
Simulation time	1252336201 ps
CPU time	8.09 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:29 PM PDT 24
Peak memory	221892 kb
Host	smart-363fac53-8831-427e-b44b-b32af77b259f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3706756342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir ect.3706756342
Directory	/workspace/44.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_all.2079281752
Short name	T688
Test name
Test status
Simulation time	2378941460 ps
CPU time	6.85 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:27 PM PDT 24
Peak memory	217620 kb
Host	smart-278b734d-7e2a-4d1c-ace6-a9446b424845
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079281752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2079281752
Directory	/workspace/44.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2757595930
Short name	T457
Test name
Test status
Simulation time	24152820963 ps
CPU time	19.75 seconds
Started	Apr 30 03:22:22 PM PDT 24
Finished	Apr 30 03:22:42 PM PDT 24
Peak memory	216264 kb
Host	smart-46ba4e41-d222-45e4-907c-8946bba48c96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2757595930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2757595930
Directory	/workspace/44.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_rw.3839419359
Short name	T671
Test name
Test status
Simulation time	802976802 ps
CPU time	3.2 seconds
Started	Apr 30 03:22:23 PM PDT 24
Finished	Apr 30 03:22:27 PM PDT 24
Peak memory	216256 kb
Host	smart-26f05dd6-dbe7-400f-959a-a314f47ae03f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839419359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3839419359
Directory	/workspace/44.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/44.spi_device_tpm_sts_read.4253893335
Short name	T174
Test name
Test status
Simulation time	47036694 ps
CPU time	0.82 seconds
Started	Apr 30 03:22:23 PM PDT 24
Finished	Apr 30 03:22:25 PM PDT 24
Peak memory	206756 kb
Host	smart-ede50529-0245-4863-817d-74e329f381b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253893335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4253893335
Directory	/workspace/44.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/44.spi_device_upload.4077129377
Short name	T173
Test name
Test status
Simulation time	6625730984 ps
CPU time	14.08 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:34 PM PDT 24
Peak memory	224128 kb
Host	smart-20881511-a952-40ad-9c61-fb52e81a1d7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077129377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4077129377
Directory	/workspace/44.spi_device_upload/latest

Test location	/workspace/coverage/default/45.spi_device_alert_test.3209746715
Short name	T33
Test name
Test status
Simulation time	40373073 ps
CPU time	0.68 seconds
Started	Apr 30 03:22:25 PM PDT 24
Finished	Apr 30 03:22:26 PM PDT 24
Peak memory	204820 kb
Host	smart-e21d93f0-ce2b-4138-948a-d1af6aebc257
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209746715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test. 3209746715
Directory	/workspace/45.spi_device_alert_test/latest

Test location	/workspace/coverage/default/45.spi_device_csb_read.882980465
Short name	T709
Test name
Test status
Simulation time	39549761 ps
CPU time	0.75 seconds
Started	Apr 30 03:22:21 PM PDT 24
Finished	Apr 30 03:22:23 PM PDT 24
Peak memory	206704 kb
Host	smart-84f38867-d986-435b-a3fa-bb76bab05b7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=882980465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.882980465
Directory	/workspace/45.spi_device_csb_read/latest

Test location	/workspace/coverage/default/45.spi_device_flash_mode.1927344729
Short name	T715
Test name
Test status
Simulation time	8295127570 ps
CPU time	21.63 seconds
Started	Apr 30 03:22:19 PM PDT 24
Finished	Apr 30 03:22:41 PM PDT 24
Peak memory	240688 kb
Host	smart-b44a07d8-4405-4c03-a2a9-4611a4454df1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927344729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1927344729
Directory	/workspace/45.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/45.spi_device_intercept.2318223713
Short name	T242
Test name
Test status
Simulation time	3257510995 ps
CPU time	23.97 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:45 PM PDT 24
Peak memory	218956 kb
Host	smart-372405f8-297b-4cf5-b8ca-ed90398778a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318223713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2318223713
Directory	/workspace/45.spi_device_intercept/latest

Test location	/workspace/coverage/default/45.spi_device_mailbox.2357190639
Short name	T125
Test name
Test status
Simulation time	11874106891 ps
CPU time	26.65 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:48 PM PDT 24
Peak memory	233548 kb
Host	smart-b9a1a902-ee78-4039-8995-4750a00f0126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357190639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2357190639
Directory	/workspace/45.spi_device_mailbox/latest

Test location	/workspace/coverage/default/45.spi_device_pass_cmd_filtering.3541635294
Short name	T689
Test name
Test status
Simulation time	11157263874 ps
CPU time	30.13 seconds
Started	Apr 30 03:22:18 PM PDT 24
Finished	Apr 30 03:22:49 PM PDT 24
Peak memory	216704 kb
Host	smart-da2b212a-f0f7-4e8f-bfaf-f3f634816826
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541635294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3541635294
Directory	/workspace/45.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/45.spi_device_read_buffer_direct.537323951
Short name	T80
Test name
Test status
Simulation time	95757066 ps
CPU time	4.07 seconds
Started	Apr 30 03:22:22 PM PDT 24
Finished	Apr 30 03:22:27 PM PDT 24
Peak memory	222828 kb
Host	smart-f04f5d25-764c-4daf-bd99-6cc624213440
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=537323951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire ct.537323951
Directory	/workspace/45.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/45.spi_device_stress_all.810675811
Short name	T599
Test name
Test status
Simulation time	158485716 ps
CPU time	1.02 seconds
Started	Apr 30 03:22:32 PM PDT 24
Finished	Apr 30 03:22:33 PM PDT 24
Peak memory	206852 kb
Host	smart-34976b35-7156-4c04-aa7c-e4dd5a295fde
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810675811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres s_all.810675811
Directory	/workspace/45.spi_device_stress_all/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_all.3724891745
Short name	T696
Test name
Test status
Simulation time	1603617606 ps
CPU time	15.96 seconds
Started	Apr 30 03:22:21 PM PDT 24
Finished	Apr 30 03:22:38 PM PDT 24
Peak memory	216328 kb
Host	smart-e3aca06a-d0b9-450b-b8f4-e00cb49e5fcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724891745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3724891745
Directory	/workspace/45.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.823381910
Short name	T478
Test name
Test status
Simulation time	1161336675 ps
CPU time	8.61 seconds
Started	Apr 30 03:22:22 PM PDT 24
Finished	Apr 30 03:22:31 PM PDT 24
Peak memory	216260 kb
Host	smart-8ebf45fa-8cb1-486f-99ef-375321ae1d37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=823381910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.823381910
Directory	/workspace/45.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_rw.1291057524
Short name	T13
Test name
Test status
Simulation time	182069547 ps
CPU time	2.6 seconds
Started	Apr 30 03:22:20 PM PDT 24
Finished	Apr 30 03:22:24 PM PDT 24
Peak memory	216336 kb
Host	smart-a932eeac-f074-4251-ad7f-ec44532869cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291057524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1291057524
Directory	/workspace/45.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/45.spi_device_tpm_sts_read.3930297802
Short name	T443
Test name
Test status
Simulation time	201620496 ps
CPU time	0.92 seconds
Started	Apr 30 03:22:22 PM PDT 24
Finished	Apr 30 03:22:23 PM PDT 24
Peak memory	206800 kb
Host	smart-35f4d058-f679-4c56-ad59-0a76be29bb29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930297802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3930297802
Directory	/workspace/45.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/46.spi_device_alert_test.1224082292
Short name	T472
Test name
Test status
Simulation time	12637530 ps
CPU time	0.7 seconds
Started	Apr 30 03:22:27 PM PDT 24
Finished	Apr 30 03:22:28 PM PDT 24
Peak memory	205280 kb
Host	smart-f6962893-01e0-4c27-bc6d-f48713bf5a0b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224082292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test. 1224082292
Directory	/workspace/46.spi_device_alert_test/latest

Test location	/workspace/coverage/default/46.spi_device_cfg_cmd.3006199142
Short name	T470
Test name
Test status
Simulation time	229422090 ps
CPU time	3.12 seconds
Started	Apr 30 03:22:27 PM PDT 24
Finished	Apr 30 03:22:31 PM PDT 24
Peak memory	222360 kb
Host	smart-35c93d6d-24f3-448a-b3e2-8bbf8b38aa36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3006199142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3006199142
Directory	/workspace/46.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/46.spi_device_csb_read.3425501340
Short name	T614
Test name
Test status
Simulation time	21514707 ps
CPU time	0.82 seconds
Started	Apr 30 03:22:28 PM PDT 24
Finished	Apr 30 03:22:30 PM PDT 24
Peak memory	206648 kb
Host	smart-5829b253-13e6-4997-930a-20821220c4a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3425501340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3425501340
Directory	/workspace/46.spi_device_csb_read/latest

Test location	/workspace/coverage/default/46.spi_device_flash_mode.2074848578
Short name	T678
Test name
Test status
Simulation time	31418656481 ps
CPU time	99.09 seconds
Started	Apr 30 03:22:29 PM PDT 24
Finished	Apr 30 03:24:09 PM PDT 24
Peak memory	250440 kb
Host	smart-b51a8e01-0574-43d3-a405-6fc3b63de1aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074848578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2074848578
Directory	/workspace/46.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/46.spi_device_intercept.1423007120
Short name	T364
Test name
Test status
Simulation time	5950060365 ps
CPU time	7.64 seconds
Started	Apr 30 03:22:29 PM PDT 24
Finished	Apr 30 03:22:38 PM PDT 24
Peak memory	218936 kb
Host	smart-56db3980-7380-4b66-9920-b52cb8033be3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423007120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1423007120
Directory	/workspace/46.spi_device_intercept/latest

Test location	/workspace/coverage/default/46.spi_device_mailbox.2436273609
Short name	T361
Test name
Test status
Simulation time	624852515 ps
CPU time	6.3 seconds
Started	Apr 30 03:22:28 PM PDT 24
Finished	Apr 30 03:22:35 PM PDT 24
Peak memory	222916 kb
Host	smart-f19043d9-04cd-40de-88bd-23e96df34c46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436273609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2436273609
Directory	/workspace/46.spi_device_mailbox/latest

Test location	/workspace/coverage/default/46.spi_device_pass_cmd_filtering.2784353206
Short name	T296
Test name
Test status
Simulation time	209247010 ps
CPU time	2.57 seconds
Started	Apr 30 03:22:26 PM PDT 24
Finished	Apr 30 03:22:29 PM PDT 24
Peak memory	218372 kb
Host	smart-332941cb-6172-4892-867a-3e27a84c4f8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2784353206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2784353206
Directory	/workspace/46.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/46.spi_device_read_buffer_direct.194308338
Short name	T579
Test name
Test status
Simulation time	5835832938 ps
CPU time	13.57 seconds
Started	Apr 30 03:22:30 PM PDT 24
Finished	Apr 30 03:22:44 PM PDT 24
Peak memory	219184 kb
Host	smart-c762ed9c-edce-4d56-962a-6c6bba7cf509
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=194308338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire ct.194308338
Directory	/workspace/46.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/46.spi_device_stress_all.793239122
Short name	T164
Test name
Test status
Simulation time	1208495189 ps
CPU time	1.17 seconds
Started	Apr 30 03:22:26 PM PDT 24
Finished	Apr 30 03:22:28 PM PDT 24
Peak memory	207124 kb
Host	smart-f3d0f89e-5f19-4e3f-90d5-60a993df2484
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793239122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres s_all.793239122
Directory	/workspace/46.spi_device_stress_all/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_all.540275589
Short name	T690
Test name
Test status
Simulation time	621419575 ps
CPU time	4.69 seconds
Started	Apr 30 03:22:28 PM PDT 24
Finished	Apr 30 03:22:33 PM PDT 24
Peak memory	219304 kb
Host	smart-19c0f96c-7301-4d7e-8cdd-ba8e5a377c66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540275589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.540275589
Directory	/workspace/46.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3066809277
Short name	T566
Test name
Test status
Simulation time	874799938 ps
CPU time	4.76 seconds
Started	Apr 30 03:22:26 PM PDT 24
Finished	Apr 30 03:22:32 PM PDT 24
Peak memory	216200 kb
Host	smart-31fb7219-c792-4322-ab01-d2fa7160c989
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066809277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3066809277
Directory	/workspace/46.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_rw.3016370598
Short name	T723
Test name
Test status
Simulation time	1338102101 ps
CPU time	9.88 seconds
Started	Apr 30 03:22:28 PM PDT 24
Finished	Apr 30 03:22:39 PM PDT 24
Peak memory	216268 kb
Host	smart-4e67e9cb-cc80-4e04-8010-cab09aa88341
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016370598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3016370598
Directory	/workspace/46.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/46.spi_device_tpm_sts_read.1781408502
Short name	T466
Test name
Test status
Simulation time	139722162 ps
CPU time	1.14 seconds
Started	Apr 30 03:22:27 PM PDT 24
Finished	Apr 30 03:22:29 PM PDT 24
Peak memory	206788 kb
Host	smart-0a2a1c9c-4f00-4787-b6fa-4f397eaf3463
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781408502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1781408502
Directory	/workspace/46.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/47.spi_device_alert_test.125261635
Short name	T544
Test name
Test status
Simulation time	38156006 ps
CPU time	0.7 seconds
Started	Apr 30 03:22:35 PM PDT 24
Finished	Apr 30 03:22:37 PM PDT 24
Peak memory	205340 kb
Host	smart-7587fcef-3cf1-45fe-bdbb-8e7104b9889a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125261635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.125261635
Directory	/workspace/47.spi_device_alert_test/latest

Test location	/workspace/coverage/default/47.spi_device_cfg_cmd.1462552231
Short name	T502
Test name
Test status
Simulation time	597903112 ps
CPU time	8.01 seconds
Started	Apr 30 03:22:37 PM PDT 24
Finished	Apr 30 03:22:45 PM PDT 24
Peak memory	222832 kb
Host	smart-0af0b20b-9884-470a-af20-660a6c23ea67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1462552231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1462552231
Directory	/workspace/47.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/47.spi_device_csb_read.1456790419
Short name	T634
Test name
Test status
Simulation time	59346275 ps
CPU time	0.8 seconds
Started	Apr 30 03:22:28 PM PDT 24
Finished	Apr 30 03:22:30 PM PDT 24
Peak memory	206684 kb
Host	smart-17480225-58a2-4034-836b-987852e843af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456790419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1456790419
Directory	/workspace/47.spi_device_csb_read/latest

Test location	/workspace/coverage/default/47.spi_device_flash_mode.614809284
Short name	T559
Test name
Test status
Simulation time	8973465278 ps
CPU time	18.14 seconds
Started	Apr 30 03:22:35 PM PDT 24
Finished	Apr 30 03:22:54 PM PDT 24
Peak memory	239196 kb
Host	smart-3a3aed0b-b33f-4db1-83c2-ac2c8e2899bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614809284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.614809284
Directory	/workspace/47.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/47.spi_device_intercept.2786498385
Short name	T498
Test name
Test status
Simulation time	3230408386 ps
CPU time	11.6 seconds
Started	Apr 30 03:22:29 PM PDT 24
Finished	Apr 30 03:22:42 PM PDT 24
Peak memory	217352 kb
Host	smart-0b4d37ec-4527-482f-8bf2-7ccea2a962b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786498385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2786498385
Directory	/workspace/47.spi_device_intercept/latest

Test location	/workspace/coverage/default/47.spi_device_mailbox.2816010068
Short name	T356
Test name
Test status
Simulation time	20674385106 ps
CPU time	65.37 seconds
Started	Apr 30 03:22:27 PM PDT 24
Finished	Apr 30 03:23:34 PM PDT 24
Peak memory	219108 kb
Host	smart-3993847d-7dca-4e75-91a9-6674bade6f79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816010068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2816010068
Directory	/workspace/47.spi_device_mailbox/latest

Test location	/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.776706027
Short name	T51
Test name
Test status
Simulation time	917597274 ps
CPU time	9.37 seconds
Started	Apr 30 03:22:25 PM PDT 24
Finished	Apr 30 03:22:35 PM PDT 24
Peak memory	234224 kb
Host	smart-a4d7f9cf-5316-47ef-a5cc-8dc43ef45a1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=776706027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap .776706027
Directory	/workspace/47.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/47.spi_device_read_buffer_direct.3473414907
Short name	T157
Test name
Test status
Simulation time	365699824 ps
CPU time	3.65 seconds
Started	Apr 30 03:22:37 PM PDT 24
Finished	Apr 30 03:22:42 PM PDT 24
Peak memory	223080 kb
Host	smart-b8e8f8b0-cf41-4864-bfaa-be7f0d88e9ed
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3473414907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir ect.3473414907
Directory	/workspace/47.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_all.1626966378
Short name	T694
Test name
Test status
Simulation time	7952305586 ps
CPU time	42.89 seconds
Started	Apr 30 03:22:27 PM PDT 24
Finished	Apr 30 03:23:11 PM PDT 24
Peak memory	216472 kb
Host	smart-5407e679-0cf3-4118-b43d-6767a3cd548f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626966378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1626966378
Directory	/workspace/47.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1454580852
Short name	T76
Test name
Test status
Simulation time	3272033242 ps
CPU time	5.09 seconds
Started	Apr 30 03:22:26 PM PDT 24
Finished	Apr 30 03:22:32 PM PDT 24
Peak memory	216348 kb
Host	smart-92730196-a7d8-4bcf-a1e3-0e5c884b42e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454580852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1454580852
Directory	/workspace/47.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_rw.968174764
Short name	T469
Test name
Test status
Simulation time	614246657 ps
CPU time	1.36 seconds
Started	Apr 30 03:22:29 PM PDT 24
Finished	Apr 30 03:22:31 PM PDT 24
Peak memory	216292 kb
Host	smart-f35708be-e604-4003-84a8-74fcf2550535
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968174764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.968174764
Directory	/workspace/47.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/47.spi_device_tpm_sts_read.304673507
Short name	T82
Test name
Test status
Simulation time	69094407 ps
CPU time	0.81 seconds
Started	Apr 30 03:22:27 PM PDT 24
Finished	Apr 30 03:22:29 PM PDT 24
Peak memory	205808 kb
Host	smart-a752715c-d82f-4c99-9c2a-7ec1c435eeb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304673507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.304673507
Directory	/workspace/47.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/47.spi_device_upload.346865989
Short name	T245
Test name
Test status
Simulation time	8529163868 ps
CPU time	34.9 seconds
Started	Apr 30 03:22:26 PM PDT 24
Finished	Apr 30 03:23:01 PM PDT 24
Peak memory	235780 kb
Host	smart-10906971-6e66-4160-a0e0-e0dc5ee1363f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=346865989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.346865989
Directory	/workspace/47.spi_device_upload/latest

Test location	/workspace/coverage/default/48.spi_device_alert_test.2150395802
Short name	T557
Test name
Test status
Simulation time	14396873 ps
CPU time	0.7 seconds
Started	Apr 30 03:22:34 PM PDT 24
Finished	Apr 30 03:22:36 PM PDT 24
Peak memory	204776 kb
Host	smart-882245e8-3d91-45ae-aaaa-4ae3e816ba11
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150395802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test. 2150395802
Directory	/workspace/48.spi_device_alert_test/latest

Test location	/workspace/coverage/default/48.spi_device_cfg_cmd.1141078859
Short name	T251
Test name
Test status
Simulation time	36779091 ps
CPU time	2.13 seconds
Started	Apr 30 03:22:35 PM PDT 24
Finished	Apr 30 03:22:38 PM PDT 24
Peak memory	218416 kb
Host	smart-bbc6c96a-0835-4e59-b972-d8356982ef19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141078859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1141078859
Directory	/workspace/48.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/48.spi_device_csb_read.3082752140
Short name	T564
Test name
Test status
Simulation time	28912706 ps
CPU time	0.8 seconds
Started	Apr 30 03:22:35 PM PDT 24
Finished	Apr 30 03:22:36 PM PDT 24
Peak memory	206572 kb
Host	smart-4f77b867-23c1-484c-93d2-9c7447d19def
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082752140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3082752140
Directory	/workspace/48.spi_device_csb_read/latest

Test location	/workspace/coverage/default/48.spi_device_intercept.154735499
Short name	T54
Test name
Test status
Simulation time	2662815679 ps
CPU time	19.54 seconds
Started	Apr 30 03:22:34 PM PDT 24
Finished	Apr 30 03:22:54 PM PDT 24
Peak memory	218940 kb
Host	smart-4eef6ec3-ba31-4fee-8cbc-b917dbfbb708
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154735499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.154735499
Directory	/workspace/48.spi_device_intercept/latest

Test location	/workspace/coverage/default/48.spi_device_read_buffer_direct.3803265636
Short name	T89
Test name
Test status
Simulation time	3598854736 ps
CPU time	10.66 seconds
Started	Apr 30 03:22:35 PM PDT 24
Finished	Apr 30 03:22:47 PM PDT 24
Peak memory	221840 kb
Host	smart-c73d58a4-86f4-42e4-83d5-6f512fa46a1f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3803265636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir ect.3803265636
Directory	/workspace/48.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_all.677502487
Short name	T388
Test name
Test status
Simulation time	14359989797 ps
CPU time	18.04 seconds
Started	Apr 30 03:22:36 PM PDT 24
Finished	Apr 30 03:22:55 PM PDT 24
Peak memory	216232 kb
Host	smart-1cae53f3-de42-46da-932d-f4862b3c6e56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677502487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.677502487
Directory	/workspace/48.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2448802369
Short name	T716
Test name
Test status
Simulation time	17698645151 ps
CPU time	24.18 seconds
Started	Apr 30 03:22:39 PM PDT 24
Finished	Apr 30 03:23:03 PM PDT 24
Peak memory	216296 kb
Host	smart-2617611d-dfac-45a3-bdcc-283e44a72ca4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448802369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2448802369
Directory	/workspace/48.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_rw.2904806733
Short name	T648
Test name
Test status
Simulation time	223062333 ps
CPU time	5.13 seconds
Started	Apr 30 03:22:39 PM PDT 24
Finished	Apr 30 03:22:44 PM PDT 24
Peak memory	216216 kb
Host	smart-7ffbf1d0-ba75-46a9-bdac-69364f66167b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904806733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2904806733
Directory	/workspace/48.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/48.spi_device_tpm_sts_read.3020490705
Short name	T604
Test name
Test status
Simulation time	186964320 ps
CPU time	1.22 seconds
Started	Apr 30 03:22:37 PM PDT 24
Finished	Apr 30 03:22:39 PM PDT 24
Peak memory	206796 kb
Host	smart-4cf2cc07-1c08-4479-88b3-999b49918e15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020490705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3020490705
Directory	/workspace/48.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/48.spi_device_upload.778852524
Short name	T261
Test name
Test status
Simulation time	5938199998 ps
CPU time	23.14 seconds
Started	Apr 30 03:22:37 PM PDT 24
Finished	Apr 30 03:23:00 PM PDT 24
Peak memory	224000 kb
Host	smart-613a378a-46ae-447e-a4f2-5d263b012972
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=778852524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.778852524
Directory	/workspace/48.spi_device_upload/latest

Test location	/workspace/coverage/default/49.spi_device_alert_test.1280116942
Short name	T452
Test name
Test status
Simulation time	19492737 ps
CPU time	0.68 seconds
Started	Apr 30 03:22:43 PM PDT 24
Finished	Apr 30 03:22:44 PM PDT 24
Peak memory	204836 kb
Host	smart-d3bec764-c05c-4d6b-91fd-80f6aba10245
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280116942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test. 1280116942
Directory	/workspace/49.spi_device_alert_test/latest

Test location	/workspace/coverage/default/49.spi_device_csb_read.4240418048
Short name	T426
Test name
Test status
Simulation time	33420605 ps
CPU time	0.75 seconds
Started	Apr 30 03:22:36 PM PDT 24
Finished	Apr 30 03:22:38 PM PDT 24
Peak memory	205888 kb
Host	smart-c927be68-45a3-42d8-8c5d-3a0c25b07c17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240418048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4240418048
Directory	/workspace/49.spi_device_csb_read/latest

Test location	/workspace/coverage/default/49.spi_device_intercept.147347525
Short name	T83
Test name
Test status
Simulation time	167109677 ps
CPU time	3.62 seconds
Started	Apr 30 03:22:37 PM PDT 24
Finished	Apr 30 03:22:41 PM PDT 24
Peak memory	223028 kb
Host	smart-c3b75054-94c3-4f93-8a22-17e4663a8181
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147347525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.147347525
Directory	/workspace/49.spi_device_intercept/latest

Test location	/workspace/coverage/default/49.spi_device_mailbox.1655021017
Short name	T239
Test name
Test status
Simulation time	188269213 ps
CPU time	5.59 seconds
Started	Apr 30 03:22:34 PM PDT 24
Finished	Apr 30 03:22:40 PM PDT 24
Peak memory	221900 kb
Host	smart-e6d2da50-072c-4c8d-a864-1ecbcf3d26b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655021017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1655021017
Directory	/workspace/49.spi_device_mailbox/latest

Test location	/workspace/coverage/default/49.spi_device_pass_cmd_filtering.2996536126
Short name	T727
Test name
Test status
Simulation time	6229604928 ps
CPU time	9.14 seconds
Started	Apr 30 03:22:48 PM PDT 24
Finished	Apr 30 03:22:58 PM PDT 24
Peak memory	219124 kb
Host	smart-3cc040a8-b5fc-4e40-adfc-5f27b7665099
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996536126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2996536126
Directory	/workspace/49.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/49.spi_device_read_buffer_direct.1796324442
Short name	T517
Test name
Test status
Simulation time	2306942166 ps
CPU time	8.28 seconds
Started	Apr 30 03:22:44 PM PDT 24
Finished	Apr 30 03:22:53 PM PDT 24
Peak memory	221416 kb
Host	smart-0c592527-af5a-4788-ab07-a0dd81616e2a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1796324442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir ect.1796324442
Directory	/workspace/49.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_all.1485233645
Short name	T397
Test name
Test status
Simulation time	3059723200 ps
CPU time	4.75 seconds
Started	Apr 30 03:22:50 PM PDT 24
Finished	Apr 30 03:22:55 PM PDT 24
Peak memory	216332 kb
Host	smart-bb289be5-c7de-4a6f-a573-15e73358eb47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1485233645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1485233645
Directory	/workspace/49.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_read_hw_reg.525016945
Short name	T525
Test name
Test status
Simulation time	5141737157 ps
CPU time	20.15 seconds
Started	Apr 30 03:22:34 PM PDT 24
Finished	Apr 30 03:22:55 PM PDT 24
Peak memory	216436 kb
Host	smart-4faeb09f-8af4-4751-86df-f45b51a0a25c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525016945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.525016945
Directory	/workspace/49.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_rw.919187483
Short name	T666
Test name
Test status
Simulation time	274655348 ps
CPU time	3.61 seconds
Started	Apr 30 03:22:36 PM PDT 24
Finished	Apr 30 03:22:40 PM PDT 24
Peak memory	216300 kb
Host	smart-e07edade-703b-4b4b-a3fa-2a882fc611fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919187483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.919187483
Directory	/workspace/49.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/49.spi_device_tpm_sts_read.1898851686
Short name	T618
Test name
Test status
Simulation time	53951900 ps
CPU time	0.88 seconds
Started	Apr 30 03:22:34 PM PDT 24
Finished	Apr 30 03:22:36 PM PDT 24
Peak memory	206240 kb
Host	smart-c802fddf-7e1b-47d3-ae2a-47044ec107bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898851686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1898851686
Directory	/workspace/49.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/49.spi_device_upload.3537711476
Short name	T30
Test name
Test status
Simulation time	1223401739 ps
CPU time	6.29 seconds
Started	Apr 30 03:22:50 PM PDT 24
Finished	Apr 30 03:22:57 PM PDT 24
Peak memory	218676 kb
Host	smart-046318b9-cb17-4556-acd5-eb303c4a77bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537711476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3537711476
Directory	/workspace/49.spi_device_upload/latest

Test location	/workspace/coverage/default/5.spi_device_alert_test.2063912550
Short name	T675
Test name
Test status
Simulation time	82408269 ps
CPU time	0.78 seconds
Started	Apr 30 03:20:01 PM PDT 24
Finished	Apr 30 03:20:04 PM PDT 24
Peak memory	204740 kb
Host	smart-c7b31f84-c77a-447e-b598-29afc14c26e2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063912550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2 063912550
Directory	/workspace/5.spi_device_alert_test/latest

Test location	/workspace/coverage/default/5.spi_device_cfg_cmd.4168994150
Short name	T273
Test name
Test status
Simulation time	197293902 ps
CPU time	3.17 seconds
Started	Apr 30 03:20:01 PM PDT 24
Finished	Apr 30 03:20:06 PM PDT 24
Peak memory	222360 kb
Host	smart-ce74103b-c0a2-4921-9f73-dbb9ea9a32b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4168994150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4168994150
Directory	/workspace/5.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/5.spi_device_csb_read.1143068144
Short name	T722
Test name
Test status
Simulation time	67565985 ps
CPU time	0.78 seconds
Started	Apr 30 03:19:51 PM PDT 24
Finished	Apr 30 03:19:53 PM PDT 24
Peak memory	206680 kb
Host	smart-aaaec9cc-5aa7-485e-b090-ad004d2e2f0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143068144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1143068144
Directory	/workspace/5.spi_device_csb_read/latest

Test location	/workspace/coverage/default/5.spi_device_intercept.2762990571
Short name	T219
Test name
Test status
Simulation time	15885486458 ps
CPU time	31.09 seconds
Started	Apr 30 03:20:01 PM PDT 24
Finished	Apr 30 03:20:34 PM PDT 24
Peak memory	218992 kb
Host	smart-4b9e29fc-9bd8-4d89-a1c1-5a0df4bb4eff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762990571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2762990571
Directory	/workspace/5.spi_device_intercept/latest

Test location	/workspace/coverage/default/5.spi_device_pass_cmd_filtering.2913967889
Short name	T252
Test name
Test status
Simulation time	1172794313 ps
CPU time	7.14 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:20:12 PM PDT 24
Peak memory	223272 kb
Host	smart-398da442-002f-4197-8e45-8ab36be2b4a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913967889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2913967889
Directory	/workspace/5.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/5.spi_device_read_buffer_direct.1169935465
Short name	T465
Test name
Test status
Simulation time	116143882 ps
CPU time	3.6 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:20:08 PM PDT 24
Peak memory	219756 kb
Host	smart-ea06cb12-ca9a-45e2-a68e-6bdfcdaefe09
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1169935465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire ct.1169935465
Directory	/workspace/5.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_all.2205531104
Short name	T420
Test name
Test status
Simulation time	1938189302 ps
CPU time	25.02 seconds
Started	Apr 30 03:19:52 PM PDT 24
Finished	Apr 30 03:20:18 PM PDT 24
Peak memory	219356 kb
Host	smart-e0591ba3-7cd3-4286-b4f9-04c992f34c69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205531104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2205531104
Directory	/workspace/5.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1953905166
Short name	T442
Test name
Test status
Simulation time	7409240344 ps
CPU time	9.53 seconds
Started	Apr 30 03:19:53 PM PDT 24
Finished	Apr 30 03:20:04 PM PDT 24
Peak memory	216288 kb
Host	smart-bed5e628-8c92-49ab-90fe-c6ca69742d24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1953905166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1953905166
Directory	/workspace/5.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_rw.4232038152
Short name	T617
Test name
Test status
Simulation time	2295015575 ps
CPU time	2.41 seconds
Started	Apr 30 03:19:51 PM PDT 24
Finished	Apr 30 03:19:55 PM PDT 24
Peak memory	216360 kb
Host	smart-763bdb81-dd2a-4819-b03f-ba3c6a05b119
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4232038152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4232038152
Directory	/workspace/5.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/5.spi_device_tpm_sts_read.2963721754
Short name	T706
Test name
Test status
Simulation time	162243844 ps
CPU time	0.83 seconds
Started	Apr 30 03:19:51 PM PDT 24
Finished	Apr 30 03:19:53 PM PDT 24
Peak memory	205764 kb
Host	smart-a8cae18b-29d1-4618-bdb0-6bbc83b241d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963721754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2963721754
Directory	/workspace/5.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/6.spi_device_alert_test.1863633434
Short name	T449
Test name
Test status
Simulation time	14001957 ps
CPU time	0.73 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:20:05 PM PDT 24
Peak memory	205312 kb
Host	smart-58dbad92-94bc-4b0f-b99b-49f66196f4e6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863633434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1 863633434
Directory	/workspace/6.spi_device_alert_test/latest

Test location	/workspace/coverage/default/6.spi_device_csb_read.2423882295
Short name	T435
Test name
Test status
Simulation time	32721535 ps
CPU time	0.81 seconds
Started	Apr 30 03:20:02 PM PDT 24
Finished	Apr 30 03:20:04 PM PDT 24
Peak memory	206672 kb
Host	smart-51192e04-0cb5-4ab3-b88c-987b4b92e78d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423882295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2423882295
Directory	/workspace/6.spi_device_csb_read/latest

Test location	/workspace/coverage/default/6.spi_device_flash_mode.99410012
Short name	T721
Test name
Test status
Simulation time	16610741333 ps
CPU time	62.57 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:21:07 PM PDT 24
Peak memory	232748 kb
Host	smart-cf0e532f-9ae8-474e-823e-2ca27e34c7e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99410012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.99410012
Directory	/workspace/6.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/6.spi_device_mailbox.1734859757
Short name	T270
Test name
Test status
Simulation time	671378122 ps
CPU time	10.74 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:20:15 PM PDT 24
Peak memory	240692 kb
Host	smart-6e87e7b1-ed63-4b75-b3e3-1c59da8439af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734859757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1734859757
Directory	/workspace/6.spi_device_mailbox/latest

Test location	/workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3599997443
Short name	T215
Test name
Test status
Simulation time	48250470074 ps
CPU time	31.28 seconds
Started	Apr 30 03:20:01 PM PDT 24
Finished	Apr 30 03:20:34 PM PDT 24
Peak memory	233760 kb
Host	smart-e39e5ae3-8883-4322-965b-ef6342595015
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599997443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap .3599997443
Directory	/workspace/6.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/6.spi_device_pass_cmd_filtering.3099004098
Short name	T281
Test name
Test status
Simulation time	147819000643 ps
CPU time	20.28 seconds
Started	Apr 30 03:20:02 PM PDT 24
Finished	Apr 30 03:20:24 PM PDT 24
Peak memory	232776 kb
Host	smart-07135fdd-5829-4ce7-98da-e7ff2eac5613
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3099004098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3099004098
Directory	/workspace/6.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/6.spi_device_read_buffer_direct.4177649874
Short name	T603
Test name
Test status
Simulation time	816323338 ps
CPU time	9.47 seconds
Started	Apr 30 03:20:15 PM PDT 24
Finished	Apr 30 03:20:26 PM PDT 24
Peak memory	221832 kb
Host	smart-6e1eaa38-6a38-452b-96c6-5103393441ee
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4177649874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire ct.4177649874
Directory	/workspace/6.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_all.21002454
Short name	T422
Test name
Test status
Simulation time	14019582462 ps
CPU time	50.4 seconds
Started	Apr 30 03:20:01 PM PDT 24
Finished	Apr 30 03:20:53 PM PDT 24
Peak memory	216280 kb
Host	smart-6b4195d4-b00e-4ec8-b5cb-fef4e37e1fcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21002454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.21002454
Directory	/workspace/6.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.163804060
Short name	T103
Test name
Test status
Simulation time	2910127915 ps
CPU time	9.78 seconds
Started	Apr 30 03:19:59 PM PDT 24
Finished	Apr 30 03:20:10 PM PDT 24
Peak memory	216300 kb
Host	smart-6bf04944-818d-4527-94ac-c042185c2236
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163804060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.163804060
Directory	/workspace/6.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_rw.268218591
Short name	T519
Test name
Test status
Simulation time	12157918 ps
CPU time	0.74 seconds
Started	Apr 30 03:20:15 PM PDT 24
Finished	Apr 30 03:20:17 PM PDT 24
Peak memory	205716 kb
Host	smart-023db728-4ac4-46a8-b280-ccd82d88f3f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=268218591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.268218591
Directory	/workspace/6.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/6.spi_device_tpm_sts_read.2959458348
Short name	T708
Test name
Test status
Simulation time	159485531 ps
CPU time	0.87 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:20:05 PM PDT 24
Peak memory	205776 kb
Host	smart-78f4181f-7659-4552-a513-f367d43ea256
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959458348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2959458348
Directory	/workspace/6.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/6.spi_device_upload.3665981143
Short name	T387
Test name
Test status
Simulation time	46218652882 ps
CPU time	13.92 seconds
Started	Apr 30 03:20:15 PM PDT 24
Finished	Apr 30 03:20:30 PM PDT 24
Peak memory	232684 kb
Host	smart-d61a42ae-1f47-4e60-925e-b2ae2ba146fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3665981143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3665981143
Directory	/workspace/6.spi_device_upload/latest

Test location	/workspace/coverage/default/7.spi_device_alert_test.616186144
Short name	T514
Test name
Test status
Simulation time	22148263 ps
CPU time	0.76 seconds
Started	Apr 30 03:20:14 PM PDT 24
Finished	Apr 30 03:20:15 PM PDT 24
Peak memory	205956 kb
Host	smart-3d62d470-f0a5-44b8-85cf-1b8093b9f98d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616186144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.616186144
Directory	/workspace/7.spi_device_alert_test/latest

Test location	/workspace/coverage/default/7.spi_device_cfg_cmd.3055624808
Short name	T27
Test name
Test status
Simulation time	119708241 ps
CPU time	2.43 seconds
Started	Apr 30 03:20:12 PM PDT 24
Finished	Apr 30 03:20:16 PM PDT 24
Peak memory	222500 kb
Host	smart-ab6396ff-83e5-4678-a55b-a2bf635c0b2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055624808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3055624808
Directory	/workspace/7.spi_device_cfg_cmd/latest

Test location	/workspace/coverage/default/7.spi_device_csb_read.3422381741
Short name	T611
Test name
Test status
Simulation time	17865809 ps
CPU time	0.75 seconds
Started	Apr 30 03:20:01 PM PDT 24
Finished	Apr 30 03:20:03 PM PDT 24
Peak memory	205972 kb
Host	smart-a5d77b6d-3132-4138-9f84-d1094e0c74e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422381741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3422381741
Directory	/workspace/7.spi_device_csb_read/latest

Test location	/workspace/coverage/default/7.spi_device_flash_mode.870135447
Short name	T627
Test name
Test status
Simulation time	9780669141 ps
CPU time	115.2 seconds
Started	Apr 30 03:20:17 PM PDT 24
Finished	Apr 30 03:22:13 PM PDT 24
Peak memory	240228 kb
Host	smart-72bbc8cc-6500-4595-b381-16eead06d60f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870135447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.870135447
Directory	/workspace/7.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/7.spi_device_mailbox.2716962533
Short name	T126
Test name
Test status
Simulation time	26683892453 ps
CPU time	60.49 seconds
Started	Apr 30 03:20:01 PM PDT 24
Finished	Apr 30 03:21:03 PM PDT 24
Peak memory	224064 kb
Host	smart-2d81d06a-9ef9-46e9-b9c4-3568253f95ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716962533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2716962533
Directory	/workspace/7.spi_device_mailbox/latest

Test location	/workspace/coverage/default/7.spi_device_pass_cmd_filtering.30670363
Short name	T310
Test name
Test status
Simulation time	53528493989 ps
CPU time	20.64 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:20:25 PM PDT 24
Peak memory	223360 kb
Host	smart-bd7f8892-6fa3-4dce-b35d-fecff6cf506e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30670363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.30670363
Directory	/workspace/7.spi_device_pass_cmd_filtering/latest

Test location	/workspace/coverage/default/7.spi_device_read_buffer_direct.2522326968
Short name	T674
Test name
Test status
Simulation time	611817912 ps
CPU time	3.85 seconds
Started	Apr 30 03:20:15 PM PDT 24
Finished	Apr 30 03:20:20 PM PDT 24
Peak memory	219080 kb
Host	smart-ec4b971e-44f6-4059-9ff4-fbf77b250614
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2522326968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire ct.2522326968
Directory	/workspace/7.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_all.1486469817
Short name	T408
Test name
Test status
Simulation time	107588321223 ps
CPU time	52.8 seconds
Started	Apr 30 03:20:03 PM PDT 24
Finished	Apr 30 03:20:57 PM PDT 24
Peak memory	216376 kb
Host	smart-038ea9bb-f321-4207-ade2-e2f376873ffa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486469817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1486469817
Directory	/workspace/7.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1849204830
Short name	T631
Test name
Test status
Simulation time	59518594418 ps
CPU time	18.87 seconds
Started	Apr 30 03:20:00 PM PDT 24
Finished	Apr 30 03:20:20 PM PDT 24
Peak memory	216256 kb
Host	smart-7d71a23b-35e2-47a4-b382-a2a57f918941
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849204830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1849204830
Directory	/workspace/7.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_rw.713740259
Short name	T530
Test name
Test status
Simulation time	649483923 ps
CPU time	8.28 seconds
Started	Apr 30 03:20:15 PM PDT 24
Finished	Apr 30 03:20:25 PM PDT 24
Peak memory	216164 kb
Host	smart-31eb5aa4-f06f-4fc0-83e6-1d6c03f64d69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713740259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.713740259
Directory	/workspace/7.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/7.spi_device_tpm_sts_read.504066544
Short name	T533
Test name
Test status
Simulation time	41518258 ps
CPU time	0.83 seconds
Started	Apr 30 03:20:01 PM PDT 24
Finished	Apr 30 03:20:03 PM PDT 24
Peak memory	205756 kb
Host	smart-1ba060fe-5745-4467-aea5-0bdcc0c96dc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504066544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.504066544
Directory	/workspace/7.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/7.spi_device_upload.548851541
Short name	T235
Test name
Test status
Simulation time	499911924 ps
CPU time	2.53 seconds
Started	Apr 30 03:20:09 PM PDT 24
Finished	Apr 30 03:20:12 PM PDT 24
Peak memory	220240 kb
Host	smart-f47bf0dd-6815-45fc-bcb4-b2cf2b1b3f8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548851541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.548851541
Directory	/workspace/7.spi_device_upload/latest

Test location	/workspace/coverage/default/8.spi_device_alert_test.1532826398
Short name	T56
Test name
Test status
Simulation time	45953627 ps
CPU time	0.74 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:15 PM PDT 24
Peak memory	205712 kb
Host	smart-21d7a5a9-0cc8-4e4d-8345-8c971eb5a788
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532826398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1 532826398
Directory	/workspace/8.spi_device_alert_test/latest

Test location	/workspace/coverage/default/8.spi_device_csb_read.1892775275
Short name	T471
Test name
Test status
Simulation time	14444660 ps
CPU time	0.81 seconds
Started	Apr 30 03:20:14 PM PDT 24
Finished	Apr 30 03:20:16 PM PDT 24
Peak memory	206648 kb
Host	smart-e32488bd-d20b-45dd-b22c-dcffe633ef2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892775275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1892775275
Directory	/workspace/8.spi_device_csb_read/latest

Test location	/workspace/coverage/default/8.spi_device_flash_mode.226906017
Short name	T384
Test name
Test status
Simulation time	36384368457 ps
CPU time	103.38 seconds
Started	Apr 30 03:20:10 PM PDT 24
Finished	Apr 30 03:21:54 PM PDT 24
Peak memory	249100 kb
Host	smart-39c91abb-64e4-4d69-bbc8-cc5948829ca2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226906017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.226906017
Directory	/workspace/8.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/8.spi_device_intercept.2185082390
Short name	T178
Test name
Test status
Simulation time	360372616 ps
CPU time	5.33 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:19 PM PDT 24
Peak memory	218640 kb
Host	smart-9e8b9f74-e4dc-48f1-bc0b-c00c2c442b7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2185082390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2185082390
Directory	/workspace/8.spi_device_intercept/latest

Test location	/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4187177055
Short name	T335
Test name
Test status
Simulation time	4261712382 ps
CPU time	6.74 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:20 PM PDT 24
Peak memory	223108 kb
Host	smart-154562eb-b795-4cf6-8bc3-d0dbb94864ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187177055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap .4187177055
Directory	/workspace/8.spi_device_pass_addr_payload_swap/latest

Test location	/workspace/coverage/default/8.spi_device_read_buffer_direct.4107204745
Short name	T692
Test name
Test status
Simulation time	172265316 ps
CPU time	4.89 seconds
Started	Apr 30 03:20:15 PM PDT 24
Finished	Apr 30 03:20:20 PM PDT 24
Peak memory	218864 kb
Host	smart-c90a0e80-c089-4fdd-ae2d-7feea07a15d0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4107204745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire ct.4107204745
Directory	/workspace/8.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_all.2893596294
Short name	T21
Test name
Test status
Simulation time	3121273921 ps
CPU time	9.03 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:23 PM PDT 24
Peak memory	216324 kb
Host	smart-462af0ec-9a96-4169-8145-60d3976b525a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893596294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2893596294
Directory	/workspace/8.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2795703760
Short name	T500
Test name
Test status
Simulation time	7729439822 ps
CPU time	26.36 seconds
Started	Apr 30 03:20:14 PM PDT 24
Finished	Apr 30 03:20:41 PM PDT 24
Peak memory	216276 kb
Host	smart-5982c55e-85bf-4cd5-ac24-9b91fa836289
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795703760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2795703760
Directory	/workspace/8.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_rw.3611269902
Short name	T712
Test name
Test status
Simulation time	183940902 ps
CPU time	6.84 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:21 PM PDT 24
Peak memory	216376 kb
Host	smart-1c786416-14e7-469f-8010-445c23e4a10f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611269902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3611269902
Directory	/workspace/8.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/8.spi_device_tpm_sts_read.3677396124
Short name	T616
Test name
Test status
Simulation time	149582849 ps
CPU time	0.81 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:14 PM PDT 24
Peak memory	205732 kb
Host	smart-e4895ee8-d5de-423b-8f3e-7d0bfb6c1ddc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3677396124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3677396124
Directory	/workspace/8.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/8.spi_device_upload.816732088
Short name	T300
Test name
Test status
Simulation time	830704050 ps
CPU time	7.21 seconds
Started	Apr 30 03:20:16 PM PDT 24
Finished	Apr 30 03:20:24 PM PDT 24
Peak memory	218656 kb
Host	smart-f949e178-68ed-43c4-8777-7b7d3226b11f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816732088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.816732088
Directory	/workspace/8.spi_device_upload/latest

Test location	/workspace/coverage/default/9.spi_device_alert_test.2282742974
Short name	T447
Test name
Test status
Simulation time	50626334 ps
CPU time	0.7 seconds
Started	Apr 30 03:20:12 PM PDT 24
Finished	Apr 30 03:20:13 PM PDT 24
Peak memory	204776 kb
Host	smart-31e0a307-bd3f-40a0-85bb-3dbe92f8c10a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282742974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2 282742974
Directory	/workspace/9.spi_device_alert_test/latest

Test location	/workspace/coverage/default/9.spi_device_csb_read.1470496493
Short name	T434
Test name
Test status
Simulation time	18642594 ps
CPU time	0.82 seconds
Started	Apr 30 03:20:15 PM PDT 24
Finished	Apr 30 03:20:17 PM PDT 24
Peak memory	206724 kb
Host	smart-6decb9f6-09a6-4602-ab89-754e469cc0b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470496493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1470496493
Directory	/workspace/9.spi_device_csb_read/latest

Test location	/workspace/coverage/default/9.spi_device_flash_mode.1566331122
Short name	T344
Test name
Test status
Simulation time	3744161709 ps
CPU time	59.54 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:21:14 PM PDT 24
Peak memory	232752 kb
Host	smart-9f68ac6f-30de-455a-ad96-76f6c1797d55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566331122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1566331122
Directory	/workspace/9.spi_device_flash_mode/latest

Test location	/workspace/coverage/default/9.spi_device_intercept.2910918971
Short name	T543
Test name
Test status
Simulation time	74441864 ps
CPU time	2.44 seconds
Started	Apr 30 03:20:11 PM PDT 24
Finished	Apr 30 03:20:15 PM PDT 24
Peak memory	218644 kb
Host	smart-dd950e4b-cda2-49b7-aa0e-525499587979
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910918971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2910918971
Directory	/workspace/9.spi_device_intercept/latest

Test location	/workspace/coverage/default/9.spi_device_read_buffer_direct.3086190139
Short name	T142
Test name
Test status
Simulation time	1038475666 ps
CPU time	7.29 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:21 PM PDT 24
Peak memory	222760 kb
Host	smart-a3e0a264-7a5c-413d-9a4f-06d81d824d05
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3086190139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire ct.3086190139
Directory	/workspace/9.spi_device_read_buffer_direct/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_all.1624681122
Short name	T101
Test name
Test status
Simulation time	2525277063 ps
CPU time	16.36 seconds
Started	Apr 30 03:20:16 PM PDT 24
Finished	Apr 30 03:20:34 PM PDT 24
Peak memory	216396 kb
Host	smart-5ba0fd99-8764-429e-b1f3-192c2b8994e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624681122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1624681122
Directory	/workspace/9.spi_device_tpm_all/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3762388140
Short name	T515
Test name
Test status
Simulation time	300797200 ps
CPU time	2.42 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:17 PM PDT 24
Peak memory	216256 kb
Host	smart-3c5e0d84-acf7-4caf-be0a-3935f1dfd804
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3762388140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3762388140
Directory	/workspace/9.spi_device_tpm_read_hw_reg/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_rw.2272405664
Short name	T601
Test name
Test status
Simulation time	810407710 ps
CPU time	18.63 seconds
Started	Apr 30 03:20:11 PM PDT 24
Finished	Apr 30 03:20:31 PM PDT 24
Peak memory	216368 kb
Host	smart-a10ad82c-3cc8-44d3-8c76-3f1e33b2e170
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272405664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2272405664
Directory	/workspace/9.spi_device_tpm_rw/latest

Test location	/workspace/coverage/default/9.spi_device_tpm_sts_read.1949377283
Short name	T645
Test name
Test status
Simulation time	141405727 ps
CPU time	0.93 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:15 PM PDT 24
Peak memory	206820 kb
Host	smart-45ec0042-9bc9-4a6a-97fb-275000f30acf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949377283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1949377283
Directory	/workspace/9.spi_device_tpm_sts_read/latest

Test location	/workspace/coverage/default/9.spi_device_upload.2520038651
Short name	T206
Test name
Test status
Simulation time	488701794 ps
CPU time	3.63 seconds
Started	Apr 30 03:20:13 PM PDT 24
Finished	Apr 30 03:20:17 PM PDT 24
Peak memory	222232 kb
Host	smart-fbd61b52-bbaa-4f4a-b6c3-5f1272497d23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520038651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2520038651
Directory	/workspace/9.spi_device_upload/latest