Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	305202	1			T1	1		T3	938		T4	1
all_values[1]	305202	1			T1	1		T3	938		T4	1
all_values[2]	305202	1			T1	1		T3	938		T4	1
all_values[3]	305202	1			T1	1		T3	938		T4	1
all_values[4]	305202	1			T1	1		T3	938		T4	1
all_values[5]	305202	1			T1	1		T3	938		T4	1
all_values[6]	305202	1			T1	1		T3	938		T4	1
all_values[7]	305202	1			T1	1		T3	938		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2439499

1

T1

8

T3

7504

T4

8

auto[1]

2117

1

T20

15

T44

21

T41

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2439755

1

T1

8

T3

7502

T4

8

auto[1]

1861

1

T3

2

T12

15

T19

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	304854	1			T1	1		T3	938		T4	1
all_values[0]	auto[0]	auto[1]	100	1			T20	3		T41	1		T42	4
all_values[0]	auto[1]	auto[0]	159	1			T20	1		T44	3		T41	8
all_values[0]	auto[1]	auto[1]	89	1			T41	3		T42	1		T43	4
all_values[1]	auto[0]	auto[0]	304816	1			T1	1		T3	938		T4	1
all_values[1]	auto[0]	auto[1]	118	1			T44	1		T41	1		T42	7
all_values[1]	auto[1]	auto[0]	167	1			T20	2		T44	4		T41	11
all_values[1]	auto[1]	auto[1]	101	1			T42	2		T43	6		T366	4
all_values[2]	auto[0]	auto[0]	304835	1			T1	1		T3	938		T4	1
all_values[2]	auto[0]	auto[1]	98	1			T20	2		T41	4		T42	3
all_values[2]	auto[1]	auto[0]	165	1			T20	1		T44	2		T41	1
all_values[2]	auto[1]	auto[1]	104	1			T41	5		T42	2		T366	1
all_values[3]	auto[0]	auto[0]	304806	1			T1	1		T3	938		T4	1
all_values[3]	auto[0]	auto[1]	125	1			T20	2		T41	1		T42	2
all_values[3]	auto[1]	auto[0]	165	1			T20	1		T44	4		T41	8
all_values[3]	auto[1]	auto[1]	106	1			T44	1		T41	3		T42	4
all_values[4]	auto[0]	auto[0]	304831	1			T1	1		T3	938		T4	1
all_values[4]	auto[0]	auto[1]	117	1			T44	1		T41	1		T42	4
all_values[4]	auto[1]	auto[0]	166	1			T20	2		T44	3		T41	1
all_values[4]	auto[1]	auto[1]	88	1			T20	3		T44	1		T41	3
all_values[5]	auto[0]	auto[0]	304624	1			T1	1		T3	936		T4	1
all_values[5]	auto[0]	auto[1]	328	1			T3	2		T12	15		T19	5
all_values[5]	auto[1]	auto[0]	169	1			T42	7		T43	11		T164	3
all_values[5]	auto[1]	auto[1]	81	1			T20	1		T44	1		T41	2
all_values[6]	auto[0]	auto[0]	304829	1			T1	1		T3	938		T4	1
all_values[6]	auto[0]	auto[1]	89	1			T20	1		T44	2		T41	5
all_values[6]	auto[1]	auto[0]	175	1			T41	3		T42	8		T43	4
all_values[6]	auto[1]	auto[1]	109	1			T41	5		T42	3		T43	2
all_values[7]	auto[0]	auto[0]	304833	1			T1	1		T3	938		T4	1
all_values[7]	auto[0]	auto[1]	96	1			T20	1		T44	2		T41	4
all_values[7]	auto[1]	auto[0]	161	1			T20	1		T41	4		T42	2
all_values[7]	auto[1]	auto[1]	112	1			T20	3		T44	2		T41	5