Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	27	57	67.86

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	25	23	47.92	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1082	1			T1	12		T4	8		T6	4
auto[SpiFlashAddrCfg]	819	1			T4	14		T9	4		T11	8
auto[SpiFlashAddr3b]	1054	1			T4	2		T5	2		T9	10
auto[SpiFlashAddr4b]	899	1			T1	2		T4	2		T6	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2965

1

T1

14

T4

26

T6

10

auto[1]

889

1

T5

2

T70

10

T67

18

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1962

1

T1

12

T4

12

T6

4

auto[1]

1892

1

T1

2

T4

14

T5

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1492	1			T1	12		T4	14		T6	10
values[1]	97	1			T9	2		T11	2		T83	6
values[2]	189	1			T9	2		T97	6		T83	10
values[3]	189	1			T67	4		T83	4		T47	4
values[4]	191	1			T47	4		T58	4		T26	2
values[5]	144	1			T4	2		T10	2		T74	2
values[6]	173	1			T4	4		T11	4		T67	6
values[7]	191	1			T9	4		T11	4		T70	2
values[8]	1188	1			T1	2		T4	6		T5	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3350

1

T1

14

T4

26

T5

2

auto[1]

504

1

T89

8

T90

14

T154

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3712

1

T1

14

T4

26

T5

2

write

142

1

T11

4

T67

2

T69

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1817

1

T1

12

T4

12

T5

2

valids[0x1]

2037

1

T1

2

T4

14

T6

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	176	1			T6	4		T97	2		T47	2
internal_process_ops[0x5a]	162	1			T46	6		T47	2		T26	2
internal_process_ops[0x05]	206	1			T4	4		T67	2		T26	2
internal_process_ops[0x35]	156	1			T4	4		T46	8		T47	2
internal_process_ops[0x15]	165	1			T6	6		T8	2		T26	6
internal_process_ops[0x03]	251	1			T97	2		T53	2		T26	2
internal_process_ops[0x0b]	269	1			T4	6		T46	2		T74	4
internal_process_ops[0x3b]	265	1			T4	2		T9	4		T11	4
internal_process_ops[0x6b]	287	1			T5	2		T70	2		T46	2
internal_process_ops[0xbb]	237	1			T9	2		T11	2		T83	6
internal_process_ops[0xeb]	279	1			T10	2		T74	2		T49	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3790

1

T1

14

T4

26

T5

2

auto[1]

64

1

T67

2

T68

4

T71

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3854

1

T1

14

T4

26

T5

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	25	23	47.92	25
Automatically Generated Cross Bins	48	25	23	47.92	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	[auto[SpiFlashAddrDisabled]]	[auto[1]]	*	--	--	2
[auto[1]]	[write]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	*	*	--	--	12

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[read]	[auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[write]	[auto[SpiFlashAddrDisabled]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

840

1

T1

12

T4

8

T6

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

208

1

T67

2

T98

2

T68

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

452

1

T4

14

T9

4

T11

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

184

1

T70

4

T67

10

T83

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

608

1

T4

2

T9

10

T10

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

248

1

T5

2

T70

6

T83

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

490

1

T1

2

T4

2

T6

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

180

1

T67

4

T83

4

T98

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

16

1

T69

2

T201

4

T297

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

6

1

T77

2

T82

4

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

12

1

T11

4

T239

2

T298

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

24

1

T67

2

T71

2

T81

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

26

1

T75

2

T266

2

T234

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

8

1

T68

4

T77

2

T80

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

22

1

T190

4

T176

2

T299

8

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

26

1

T76

2

T78

4

T79

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9

1

T94

9

-

-

-

-

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

1

1

T94

1

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

147

1

T89

3

T90

14

T154

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

160

1

T89

5

T91

2

T155

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

4

1

T94

4

-

-

-

-

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

181

1

T91

6

T155

4

T156

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

2

1

T300

2

-

-

-

-

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	334	1			T1	12		T6	6		T11	2
auto[0]	values[0]	valids[0x1]	1110	1			T4	14		T6	4		T8	2
auto[0]	values[1]	valids[0x1]	84	1			T9	2		T11	2		T83	6
auto[0]	values[2]	valids[0x0]	108	1			T9	2		T97	6		T83	10
auto[0]	values[2]	valids[0x1]	36	1			T284	2		T175	2		T239	2
auto[0]	values[3]	valids[0x0]	84	1			T67	4		T47	4		T281	4
auto[0]	values[3]	valids[0x1]	72	1			T83	4		T69	2		T281	4
auto[0]	values[4]	valids[0x0]	92	1			T47	4		T58	4		T92	2
auto[0]	values[4]	valids[0x1]	52	1			T26	2		T86	4		T276	2
auto[0]	values[5]	valids[0x0]	92	1			T4	2		T10	2		T74	2
auto[0]	values[5]	valids[0x1]	22	1			T283	6		T301	2		T297	2
auto[0]	values[6]	valids[0x0]	72	1			T4	4		T11	4		T67	6
auto[0]	values[6]	valids[0x1]	46	1			T26	4		T281	2		T266	4
auto[0]	values[7]	valids[0x0]	86	1			T9	4		T70	2		T46	2
auto[0]	values[7]	valids[0x1]	58	1			T11	4		T26	2		T101	4
auto[0]	values[8]	valids[0x0]	602	1			T4	6		T5	2		T10	2
auto[0]	values[8]	valids[0x1]	400	1			T1	2		T9	2		T46	8
auto[1]	values[0]	valids[0x0]	1	1			T94	1		-	-		-	-
auto[1]	values[0]	valids[0x1]	47	1			T89	5		T90	5		T155	4
auto[1]	values[1]	valids[0x1]	13	1			T302	3		T94	1		T303	3
auto[1]	values[2]	valids[0x0]	41	1			T154	5		T302	4		T304	1
auto[1]	values[2]	valids[0x1]	4	1			T305	4		-	-		-	-
auto[1]	values[3]	valids[0x0]	28	1			T157	6		T303	6		T306	8
auto[1]	values[3]	valids[0x1]	5	1			T307	4		T302	1		-	-
auto[1]	values[4]	valids[0x0]	35	1			T308	3		T309	7		T304	3
auto[1]	values[4]	valids[0x1]	12	1			T155	5		T310	2		T311	5
auto[1]	values[5]	valids[0x0]	28	1			T90	7		T156	4		T312	9
auto[1]	values[5]	valids[0x1]	2	1			T313	2		-	-		-	-
auto[1]	values[6]	valids[0x0]	44	1			T91	6		T155	4		T157	2
auto[1]	values[6]	valids[0x1]	11	1			T111	2		T314	4		T315	5
auto[1]	values[7]	valids[0x0]	38	1			T157	4		T307	4		T316	5
auto[1]	values[7]	valids[0x1]	9	1			T113	5		T317	4		-	-
auto[1]	values[8]	valids[0x0]	132	1			T89	3		T90	2		T154	1
auto[1]	values[8]	valids[0x1]	54	1			T91	2		T318	7		T111	5