Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1881383 1 T1 333 T4 1 T5 1


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1719501 1 T1 333 T4 1 T5 1
auto[1] 161882 1 T46 1826 T26 6928 T27 9792


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 449524 1 T1 31 T4 1 T5 1
auto[524288:1048575] 217110 1 T1 55 T6 12 T46 200
auto[1048576:1572863] 206270 1 T1 9 T6 7376 T46 26
auto[1572864:2097151] 212909 1 T1 57 T6 4680 T8 20
auto[2097152:2621439] 197465 1 T1 3 T6 16 T46 965
auto[2621440:3145727] 181764 1 T1 50 T6 2143 T46 107
auto[3145728:3670015] 198909 1 T1 46 T6 12868 T46 449
auto[3670016:4194303] 217432 1 T1 82 T6 5669 T46 164


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 176370 1 T1 147 T4 1 T5 1
auto[1] 1705013 1 T1 186 T6 37535 T8 25


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1881383 1 T1 333 T4 1 T5 1


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 330161 1 T1 31 T4 1 T5 1
auto[0] auto[0] auto[0:524287] auto[1] 119363 1 T46 333 T26 6928 T27 9792
auto[0] auto[0] auto[524288:1048575] auto[0] 208927 1 T1 55 T6 12 T46 199
auto[0] auto[0] auto[524288:1048575] auto[1] 8183 1 T46 1 T177 4 T120 1796
auto[0] auto[0] auto[1048576:1572863] auto[0] 201910 1 T1 9 T6 7376 T46 26
auto[0] auto[0] auto[1048576:1572863] auto[1] 4360 1 T120 3615 T178 1 T96 7
auto[0] auto[0] auto[1572864:2097151] auto[0] 208134 1 T1 57 T6 4680 T8 20
auto[0] auto[0] auto[1572864:2097151] auto[1] 4775 1 T46 598 T177 4 T96 2935
auto[0] auto[0] auto[2097152:2621439] auto[0] 191272 1 T1 3 T6 16 T46 450
auto[0] auto[0] auto[2097152:2621439] auto[1] 6193 1 T46 515 T120 507 T179 11
auto[0] auto[0] auto[2621440:3145727] auto[0] 174271 1 T1 50 T6 2143 T46 107
auto[0] auto[0] auto[2621440:3145727] auto[1] 7493 1 T120 1328 T121 8 T179 55
auto[0] auto[0] auto[3145728:3670015] auto[0] 193496 1 T1 46 T6 12868 T46 136
auto[0] auto[0] auto[3145728:3670015] auto[1] 5413 1 T46 313 T178 1 T180 3235
auto[0] auto[0] auto[3670016:4194303] auto[0] 211330 1 T1 82 T6 5669 T46 98
auto[0] auto[0] auto[3670016:4194303] auto[1] 6102 1 T46 66 T120 5 T121 3


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 176370 1 T1 147 T4 1 T5 1
auto[0] auto[0] auto[1] 1705013 1 T1 186 T6 37535 T8 25

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