Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.82	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	28	100	78.12

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	28	100	78.12	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2466

1

T1

14

T4

26

T6

10

auto[1]

884

1

T5

2

T70

10

T67

18

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	610	1			T4	26		T11	18		T74	10
values[1]	428	1			T83	32		T122	34		T276	26
values[2]	408	1			T5	2		T9	14		T46	18
values[3]	430	1			T53	12		T26	32		T48	14
values[4]	312	1			T10	4		T70	10		T99	16
values[5]	584	1			T8	2		T58	26		T92	8
values[6]	318	1			T1	14		T98	16		T24	6
values[7]	260	1			T6	10		T97	34		T69	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	500	1			T5	2		T6	10		T70	10
values[1]	406	1			T83	32		T47	18		T69	6
values[2]	360	1			T74	10		T67	18		T124	4
values[3]	426	1			T58	26		T98	16		T281	32
values[4]	442	1			T4	26		T10	4		T46	18
values[5]	360	1			T11	18		T92	8		T68	28
values[6]	510	1			T1	14		T8	2		T97	34
values[7]	346	1			T9	14		T53	12		T183	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	28	100	78.12	28

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[4]]	[values[7]]	0	1	1
[auto[0]]	[values[7]]	[values[2]]	0	1	1
[auto[1]]	[values[0]]	[values[5]]	0	1	1
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[2]]	0	1	1
[auto[1]]	[values[1]]	[values[4]]	0	1	1
[auto[1]]	[values[1]]	[values[6]]	0	1	1
[auto[1]]	[values[2]]	[values[1]]	0	1	1
[auto[1]]	[values[3]]	[values[2]]	0	1	1
[auto[1]]	[values[3]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[4]]	[values[1]]	0	1	1
[auto[1]]	[values[4]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[5]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[6]]	[values[2]]	0	1	1
[auto[1]]	[values[6]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	118	1			T49	2		T190	14		T87	16
auto[0]	values[0]	values[1]	56	1			T47	18		T28	14		T234	12
auto[0]	values[0]	values[2]	22	1			T74	10		T319	12		-	-
auto[0]	values[0]	values[3]	20	1			T25	20		-	-		-	-
auto[0]	values[0]	values[4]	36	1			T4	26		T251	10		-	-
auto[0]	values[0]	values[5]	42	1			T11	18		T203	22		T233	2
auto[0]	values[0]	values[6]	50	1			T320	20		T204	26		T250	4
auto[0]	values[0]	values[7]	40	1			T201	24		T321	4		T322	12
auto[0]	values[1]	values[0]	20	1			T263	20		-	-		-	-
auto[0]	values[1]	values[1]	42	1			T276	26		T323	16		-	-
auto[0]	values[1]	values[2]	42	1			T208	20		T242	22		-	-
auto[0]	values[1]	values[3]	6	1			T275	2		T324	4		-	-
auto[0]	values[1]	values[4]	98	1			T122	34		T229	18		T236	4
auto[0]	values[1]	values[5]	32	1			T180	4		T267	8		T256	10
auto[0]	values[1]	values[6]	16	1			T325	4		T326	12		-	-
auto[0]	values[1]	values[7]	20	1			T237	6		T206	4		T327	10
auto[0]	values[2]	values[0]	52	1			T266	28		T176	24		-	-
auto[0]	values[2]	values[1]	42	1			T252	8		T260	6		T328	6
auto[0]	values[2]	values[2]	42	1			T329	10		T271	8		T264	24
auto[0]	values[2]	values[3]	22	1			T330	22		-	-		-	-
auto[0]	values[2]	values[4]	44	1			T46	18		T177	6		T179	4
auto[0]	values[2]	values[5]	20	1			T246	4		T186	16		-	-
auto[0]	values[2]	values[6]	16	1			T331	16		-	-		-	-
auto[0]	values[2]	values[7]	42	1			T9	14		T332	20		T278	8
auto[0]	values[3]	values[0]	34	1			T181	8		T95	6		T333	6
auto[0]	values[3]	values[1]	14	1			T196	4		T220	2		T334	8
auto[0]	values[3]	values[2]	24	1			T120	22		T227	2		-	-
auto[0]	values[3]	values[3]	14	1			T298	8		T335	6		-	-
auto[0]	values[3]	values[4]	52	1			T192	32		T218	16		T336	4
auto[0]	values[3]	values[5]	72	1			T182	14		T337	18		T338	20
auto[0]	values[3]	values[6]	58	1			T26	32		T48	14		T202	12
auto[0]	values[3]	values[7]	44	1			T53	12		T183	2		T214	4
auto[0]	values[4]	values[0]	38	1			T339	20		T265	18		-	-
auto[0]	values[4]	values[1]	16	1			T99	16		-	-		-	-
auto[0]	values[4]	values[2]	54	1			T254	8		T239	14		T247	14
auto[0]	values[4]	values[3]	22	1			T340	22		-	-		-	-
auto[0]	values[4]	values[4]	28	1			T10	4		T262	14		T341	8
auto[0]	values[4]	values[5]	46	1			T29	2		T230	14		T249	8
auto[0]	values[4]	values[6]	24	1			T96	24		-	-		-	-
auto[0]	values[5]	values[0]	30	1			T178	10		T299	20		-	-
auto[0]	values[5]	values[1]	18	1			T235	2		T342	8		T343	8
auto[0]	values[5]	values[2]	48	1			T124	4		T101	18		T175	26
auto[0]	values[5]	values[3]	146	1			T58	26		T281	32		T279	20
auto[0]	values[5]	values[4]	80	1			T261	10		T344	2		T345	34
auto[0]	values[5]	values[5]	16	1			T92	8		T217	2		T185	6
auto[0]	values[5]	values[6]	164	1			T8	2		T27	18		T121	8
auto[0]	values[5]	values[7]	30	1			T346	14		T347	4		T348	12
auto[0]	values[6]	values[0]	58	1			T191	10		T207	22		T349	26
auto[0]	values[6]	values[1]	20	1			T273	14		T173	4		T285	2
auto[0]	values[6]	values[2]	24	1			T350	24		-	-		-	-
auto[0]	values[6]	values[3]	30	1			T241	14		T212	16		-	-
auto[0]	values[6]	values[4]	4	1			T351	4		-	-		-	-
auto[0]	values[6]	values[5]	18	1			T24	6		T200	2		T352	10
auto[0]	values[6]	values[6]	54	1			T1	14		T257	12		T353	18
auto[0]	values[6]	values[7]	28	1			T268	22		T197	6		-	-
auto[0]	values[7]	values[0]	36	1			T6	10		T255	6		T216	10
auto[0]	values[7]	values[1]	42	1			T69	6		T75	22		T284	4
auto[0]	values[7]	values[3]	8	1			T86	4		T210	4		-	-
auto[0]	values[7]	values[4]	10	1			T205	6		T221	4		-	-
auto[0]	values[7]	values[5]	6	1			T354	6		-	-		-	-
auto[0]	values[7]	values[6]	64	1			T97	34		T232	22		T199	4
auto[0]	values[7]	values[7]	52	1			T100	4		T355	10		T356	2
auto[1]	values[0]	values[0]	34	1			T253	24		T294	10		-	-
auto[1]	values[0]	values[1]	28	1			T72	28		-	-		-	-
auto[1]	values[0]	values[2]	58	1			T211	32		T290	26		-	-
auto[1]	values[0]	values[3]	46	1			T219	2		T292	28		T296	16
auto[1]	values[0]	values[4]	26	1			T357	26		-	-		-	-
auto[1]	values[0]	values[6]	10	1			T272	10		-	-		-	-
auto[1]	values[0]	values[7]	24	1			T188	24		-	-		-	-
auto[1]	values[1]	values[1]	86	1			T83	32		T209	24		T358	30
auto[1]	values[1]	values[3]	34	1			T291	34		-	-		-	-
auto[1]	values[1]	values[5]	6	1			T359	6		-	-		-	-
auto[1]	values[1]	values[7]	26	1			T231	26		-	-		-	-
auto[1]	values[2]	values[0]	40	1			T5	2		T82	38		-	-
auto[1]	values[2]	values[2]	18	1			T67	18		-	-		-	-
auto[1]	values[2]	values[3]	2	1			T189	2		-	-		-	-
auto[1]	values[2]	values[4]	8	1			T71	8		-	-		-	-
auto[1]	values[2]	values[5]	28	1			T81	18		T360	10		-	-
auto[1]	values[2]	values[6]	4	1			T80	4		-	-		-	-
auto[1]	values[2]	values[7]	28	1			T78	28		-	-		-	-
auto[1]	values[3]	values[0]	28	1			T193	28		-	-		-	-
auto[1]	values[3]	values[1]	10	1			T187	10		-	-		-	-
auto[1]	values[3]	values[3]	36	1			T295	36		-	-		-	-
auto[1]	values[3]	values[4]	32	1			T225	6		T226	26		-	-
auto[1]	values[3]	values[7]	12	1			T77	12		-	-		-	-
auto[1]	values[4]	values[0]	10	1			T70	10		-	-		-	-
auto[1]	values[4]	values[2]	26	1			T282	26		-	-		-	-
auto[1]	values[4]	values[5]	4	1			T169	4		-	-		-	-
auto[1]	values[4]	values[6]	44	1			T223	18		T361	26		-	-
auto[1]	values[5]	values[5]	52	1			T68	28		T79	24		-	-
auto[1]	values[6]	values[0]	2	1			T301	2		-	-		-	-
auto[1]	values[6]	values[1]	32	1			T362	32		-	-		-	-
auto[1]	values[6]	values[3]	16	1			T98	16		-	-		-	-
auto[1]	values[6]	values[4]	20	1			T280	20		-	-		-	-
auto[1]	values[6]	values[5]	12	1			T76	12		-	-		-	-
auto[1]	values[7]	values[2]	2	1			T259	2		-	-		-	-
auto[1]	values[7]	values[3]	24	1			T293	24		-	-		-	-
auto[1]	values[7]	values[4]	4	1			T363	4		-	-		-	-
auto[1]	values[7]	values[5]	6	1			T195	6		-	-		-	-
auto[1]	values[7]	values[6]	6	1			T286	6		-	-		-	-