Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.52	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	4	56	93.33

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	4	56	93.33	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	138	1			T49	2		T47	12		T48	4
auto[ReadAddrCrossIntoMailbox]	32	1			T53	2		T86	2		T232	6
auto[ReadAddrCrossOutOfMailbox]	30	1			T53	2		T284	2		T232	4
auto[ReadAddrCrossAllMailbox]	44	1			T53	6		T232	6		T191	4
auto[ReadAddrOutsideMailbox]	814	1			T4	8		T5	2		T9	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

529

1

T4

4

T5

1

T9

3

auto[1]

529

1

T4

4

T5

1

T9

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	162	1			T97	2		T53	2		T26	2
read_ops[0x0b]	212	1			T4	6		T46	2		T74	4
read_ops[0x3b]	190	1			T4	2		T9	4		T11	4
read_ops[0x6b]	176	1			T5	2		T70	2		T46	2
read_ops[0xbb]	148	1			T9	2		T11	2		T83	6
read_ops[0xeb]	170	1			T10	2		T74	2		T49	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x03]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2
[read_ops[0xeb]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T183	1		T232	1		T355	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T183	1		T232	1		T355	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T232	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T232	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T53	1		T232	1		T364	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T53	1		T232	1		T364	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	65	1			T97	1		T26	1		T69	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	65	1			T97	1		T26	1		T69	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T47	2		T273	2		T353	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T47	2		T273	2		T353	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T86	1		T261	1		T365	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T86	1		T261	1		T365	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T365	2		T269	1		T216	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T365	2		T269	1		T216	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T191	1		T257	2		T261	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T191	1		T257	2		T261	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	75	1			T4	3		T46	1		T74	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	75	1			T4	3		T46	1		T74	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T47	2		T273	1		T261	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T47	2		T273	1		T261	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T236	1		T354	1		T269	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T236	1		T354	1		T269	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T232	1		T257	1		T261	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T232	1		T257	1		T261	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T232	1		T354	1		T365	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T232	1		T354	1		T365	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	76	1			T4	1		T9	2		T11	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	76	1			T4	1		T9	2		T11	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T178	2		T273	2		T353	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T178	2		T273	2		T353	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T232	1		T364	2		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T232	1		T364	2		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	6	1			T232	1		T255	1		T212	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	6	1			T232	1		T255	1		T212	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T232	1		T250	1		T255	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T232	1		T250	1		T255	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	65	1			T5	1		T70	1		T46	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	65	1			T5	1		T70	1		T46	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T47	2		T178	2		T214	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T47	2		T178	2		T214	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T53	1		T257	1		T216	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T53	1		T257	1		T216	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T53	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T53	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T53	2		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T53	2		-	-		-	-
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	61	1			T9	1		T11	1		T83	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T9	1		T11	1		T83	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T49	1		T48	2		T177	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T49	1		T48	2		T177	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T284	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T284	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T191	1		T222	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T191	1		T222	1		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	65	1			T10	1		T74	1		T58	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	65	1			T10	1		T74	1		T58	5