Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	305202	1			T1	1		T3	938		T4	1
all_pins[1]	305202	1			T1	1		T3	938		T4	1
all_pins[2]	305202	1			T1	1		T3	938		T4	1
all_pins[3]	305202	1			T1	1		T3	938		T4	1
all_pins[4]	305202	1			T1	1		T3	938		T4	1
all_pins[5]	305202	1			T1	1		T3	938		T4	1
all_pins[6]	305202	1			T1	1		T3	938		T4	1
all_pins[7]	305202	1			T1	1		T3	938		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2440826	1			T1	8		T3	7504		T4	8
values[0x1]	790	1			T20	7		T44	5		T41	26
transitions[0x0=>0x1]	616	1			T20	6		T44	3		T41	19
transitions[0x1=>0x0]	635	1			T20	6		T44	4		T41	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	305113	1			T1	1		T3	938		T4	1
all_pins[0]	values[0x1]	89	1			T41	3		T42	1		T43	4
all_pins[0]	transitions[0x0=>0x1]	70	1			T41	3		T42	1		T43	3
all_pins[0]	transitions[0x1=>0x0]	82	1			T42	2		T43	5		T366	2
all_pins[1]	values[0x0]	305101	1			T1	1		T3	938		T4	1
all_pins[1]	values[0x1]	101	1			T42	2		T43	6		T366	4
all_pins[1]	transitions[0x0=>0x1]	83	1			T42	2		T43	6		T366	3
all_pins[1]	transitions[0x1=>0x0]	86	1			T41	5		T42	2		T368	2
all_pins[2]	values[0x0]	305098	1			T1	1		T3	938		T4	1
all_pins[2]	values[0x1]	104	1			T41	5		T42	2		T366	1
all_pins[2]	transitions[0x0=>0x1]	75	1			T41	4		T42	2		T366	1
all_pins[2]	transitions[0x1=>0x0]	77	1			T44	1		T41	2		T42	4
all_pins[3]	values[0x0]	305096	1			T1	1		T3	938		T4	1
all_pins[3]	values[0x1]	106	1			T44	1		T41	3		T42	4
all_pins[3]	transitions[0x0=>0x1]	88	1			T41	2		T42	4		T43	2
all_pins[3]	transitions[0x1=>0x0]	70	1			T20	3		T41	2		T42	6
all_pins[4]	values[0x0]	305114	1			T1	1		T3	938		T4	1
all_pins[4]	values[0x1]	88	1			T20	3		T44	1		T41	3
all_pins[4]	transitions[0x0=>0x1]	78	1			T20	2		T44	1		T41	2
all_pins[4]	transitions[0x1=>0x0]	71	1			T44	1		T41	1		T43	7
all_pins[5]	values[0x0]	305121	1			T1	1		T3	938		T4	1
all_pins[5]	values[0x1]	81	1			T20	1		T44	1		T41	2
all_pins[5]	transitions[0x0=>0x1]	58	1			T20	1		T44	1		T41	1
all_pins[5]	transitions[0x1=>0x0]	86	1			T41	4		T42	3		T43	1
all_pins[6]	values[0x0]	305093	1			T1	1		T3	938		T4	1
all_pins[6]	values[0x1]	109	1			T41	5		T42	3		T43	2
all_pins[6]	transitions[0x0=>0x1]	84	1			T41	3		T42	2		T43	1
all_pins[6]	transitions[0x1=>0x0]	87	1			T20	3		T44	2		T41	3
all_pins[7]	values[0x0]	305090	1			T1	1		T3	938		T4	1
all_pins[7]	values[0x1]	112	1			T20	3		T44	2		T41	5
all_pins[7]	transitions[0x0=>0x1]	80	1			T20	3		T44	1		T41	4
all_pins[7]	transitions[0x1=>0x0]	76	1			T41	2		T42	1		T43	2