Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.75	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	50	78	60.94

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	50	78	60.94	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	508	1			T69	6		T99	16		T120	22
values[1]	498	1			T74	10		T26	32		T98	16
values[2]	392	1			T1	14		T4	26		T9	14
values[3]	426	1			T5	2		T6	10		T8	2
values[4]	480	1			T11	18		T97	34		T27	18
values[5]	358	1			T10	4		T67	18		T75	22
values[6]	362	1			T47	18		T92	8		T181	8
values[7]	326	1			T46	18		T49	2		T124	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	542	1			T1	14		T83	32		T47	18
values[1]	394	1			T8	2		T46	18		T26	32
values[2]	606	1			T70	10		T74	10		T49	2
values[3]	294	1			T5	2		T6	10		T68	28
values[4]	354	1			T9	14		T10	4		T53	12
values[5]	308	1			T11	18		T182	14		T100	4
values[6]	416	1			T183	2		T99	16		T122	34
values[7]	436	1			T4	26		T97	34		T67	18

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3286

1

T1

14

T4

26

T5

2

auto[1]

64

1

T67

2

T68

4

T71

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	50	78	60.94	50

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[3]]	0	1	1
[auto[0]]	[values[1]]	[values[5]]	0	1	1
[auto[0]]	[values[6]]	[values[6]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[0]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[2]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[2]]	[values[5]]	0	1	1
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[4]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[5]]	[values[1]]	0	1	1
[auto[1]]	[values[5]]	[values[3] , values[4] , values[5]]	--	--	3
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2] , values[3] , values[4]]	--	--	3
[auto[1]]	[values[6]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	42	1			T184	20		T185	6		T186	16
auto[0]	values[0]	values[1]	34	1			T187	10		T188	22		T189	2
auto[0]	values[0]	values[2]	154	1			T120	22		T190	14		T191	10
auto[0]	values[0]	values[4]	54	1			T79	22		T192	32		-	-
auto[0]	values[0]	values[5]	44	1			T193	28		T194	16		-	-
auto[0]	values[0]	values[6]	96	1			T99	16		T195	6		T73	34
auto[0]	values[0]	values[7]	76	1			T69	6		T196	4		T197	6
auto[0]	values[1]	values[0]	66	1			T98	16		T173	4		T198	34
auto[0]	values[1]	values[1]	112	1			T26	32		T199	4		T200	2
auto[0]	values[1]	values[2]	108	1			T74	10		T178	10		T201	24
auto[0]	values[1]	values[3]	34	1			T202	12		T203	22		-	-
auto[0]	values[1]	values[4]	46	1			T204	26		T205	6		T206	4
auto[0]	values[1]	values[6]	76	1			T122	34		T207	22		T208	20
auto[0]	values[1]	values[7]	56	1			T177	6		T209	24		T210	4
auto[0]	values[2]	values[0]	136	1			T1	14		T211	32		T212	16
auto[0]	values[2]	values[1]	10	1			T213	10		-	-		-	-
auto[0]	values[2]	values[2]	34	1			T214	4		T215	20		T216	10
auto[0]	values[2]	values[3]	18	1			T217	2		T218	16		-	-
auto[0]	values[2]	values[4]	64	1			T9	14		T219	2		T220	2
auto[0]	values[2]	values[5]	22	1			T182	14		T179	4		T221	4
auto[0]	values[2]	values[6]	28	1			T222	14		T81	14		-	-
auto[0]	values[2]	values[7]	60	1			T4	26		T223	18		T224	12
auto[0]	values[3]	values[0]	96	1			T83	32		T225	6		T169	4
auto[0]	values[3]	values[1]	8	1			T8	2		T71	6		-	-
auto[0]	values[3]	values[2]	72	1			T70	10		T226	26		T72	28
auto[0]	values[3]	values[3]	38	1			T5	2		T6	10		T227	2
auto[0]	values[3]	values[4]	56	1			T53	12		T58	26		T228	14
auto[0]	values[3]	values[5]	58	1			T229	18		T230	14		T231	26
auto[0]	values[3]	values[6]	24	1			T232	22		T233	2		-	-
auto[0]	values[3]	values[7]	70	1			T234	12		T235	2		T236	4
auto[0]	values[4]	values[0]	72	1			T24	6		T237	6		T238	32
auto[0]	values[4]	values[1]	40	1			T239	14		T240	2		T241	14
auto[0]	values[4]	values[2]	58	1			T242	22		T243	2		T244	20
auto[0]	values[4]	values[3]	74	1			T68	24		T245	2		T175	26
auto[0]	values[4]	values[4]	24	1			T246	4		T247	14		T248	6
auto[0]	values[4]	values[5]	72	1			T11	18		T249	8		T250	4
auto[0]	values[4]	values[6]	84	1			T251	10		T252	8		T25	20
auto[0]	values[4]	values[7]	52	1			T97	34		T27	18		-	-
auto[0]	values[5]	values[0]	34	1			T76	10		T253	24		-	-
auto[0]	values[5]	values[1]	14	1			T254	8		T255	6		-	-
auto[0]	values[5]	values[2]	58	1			T176	24		T78	24		T256	10
auto[0]	values[5]	values[3]	62	1			T75	22		T257	12		T258	12
auto[0]	values[5]	values[4]	6	1			T10	4		T259	2		-	-
auto[0]	values[5]	values[5]	30	1			T260	6		T261	10		T262	14
auto[0]	values[5]	values[6]	92	1			T263	20		T264	24		T265	18
auto[0]	values[5]	values[7]	52	1			T67	16		T266	28		T267	8
auto[0]	values[6]	values[0]	64	1			T47	18		T92	8		T181	8
auto[0]	values[6]	values[1]	50	1			T268	22		T269	14		T270	10
auto[0]	values[6]	values[2]	18	1			T271	8		T272	10		-	-
auto[0]	values[6]	values[3]	60	1			T273	14		T274	12		T275	2
auto[0]	values[6]	values[4]	58	1			T276	26		T277	8		T278	8
auto[0]	values[6]	values[5]	62	1			T100	4		T101	18		T96	24
auto[0]	values[6]	values[7]	40	1			T279	20		T280	20		-	-
auto[0]	values[7]	values[0]	20	1			T48	14		T95	6		-	-
auto[0]	values[7]	values[1]	110	1			T46	18		T124	4		T281	32
auto[0]	values[7]	values[2]	98	1			T49	2		T282	26		T283	38
auto[0]	values[7]	values[3]	4	1			T180	4		-	-		-	-
auto[0]	values[7]	values[4]	38	1			T284	4		T28	14		T29	2
auto[0]	values[7]	values[5]	16	1			T121	8		T285	2		T286	6
auto[0]	values[7]	values[6]	10	1			T183	2		T86	4		T287	4
auto[0]	values[7]	values[7]	22	1			T288	12		T289	10		-	-
auto[1]	values[0]	values[1]	2	1			T188	2		-	-		-	-
auto[1]	values[0]	values[4]	2	1			T79	2		-	-		-	-
auto[1]	values[0]	values[7]	4	1			T82	4		-	-		-	-
auto[1]	values[2]	values[0]	10	1			T290	8		T291	2		-	-
auto[1]	values[2]	values[4]	6	1			T292	6		-	-		-	-
auto[1]	values[2]	values[6]	4	1			T81	4		-	-		-	-
auto[1]	values[3]	values[1]	2	1			T71	2		-	-		-	-
auto[1]	values[3]	values[7]	2	1			T80	2		-	-		-	-
auto[1]	values[4]	values[3]	4	1			T68	4		-	-		-	-
auto[1]	values[5]	values[0]	2	1			T76	2		-	-		-	-
auto[1]	values[5]	values[2]	4	1			T78	4		-	-		-	-
auto[1]	values[5]	values[6]	2	1			T293	2		-	-		-	-
auto[1]	values[5]	values[7]	2	1			T67	2		-	-		-	-
auto[1]	values[6]	values[1]	6	1			T294	6		-	-		-	-
auto[1]	values[6]	values[5]	4	1			T77	4		-	-		-	-
auto[1]	values[7]	values[1]	6	1			T295	6		-	-		-	-
auto[1]	values[7]	values[2]	2	1			T296	2		-	-		-	-