Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1424

1

T3

2

T12

1

T13

12

auto[1]

1474

1

T13

16

T14

5

T15

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630

1

T3

2

T12

1

T13

28

auto[1]

2268

1

T14

11

T15

1

T16

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2648

1

T3

1

T12

1

T13

23

auto[1]

250

1

T3

1

T13

5

T17

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	569	1			T13	4		T14	2		T16	4
valid[1]	600	1			T3	1		T13	4		T14	2
valid[2]	563	1			T13	11		T14	5		T16	4
valid[3]	587	1			T3	1		T12	1		T13	4
valid[4]	579	1			T13	5		T14	1		T15	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	28	1			T61	2		T63	2		T403	1
auto[0]	auto[0]	valid[0]	auto[1]	218	1			T14	1		T16	3		T108	1
auto[0]	auto[0]	valid[1]	auto[0]	43	1			T3	1		T13	3		T59	1
auto[0]	auto[0]	valid[1]	auto[1]	251	1			T14	2		T16	1		T17	1
auto[0]	auto[0]	valid[2]	auto[0]	37	1			T13	5		T18	1		T59	1
auto[0]	auto[0]	valid[2]	auto[1]	224	1			T14	3		T16	2		T21	1
auto[0]	auto[0]	valid[3]	auto[0]	33	1			T12	1		T13	1		T84	1
auto[0]	auto[0]	valid[3]	auto[1]	223	1			T16	2		T17	2		T108	1
auto[0]	auto[0]	valid[4]	auto[0]	41	1			T13	1		T17	2		T59	1
auto[0]	auto[0]	valid[4]	auto[1]	189	1			T16	2		T21	1		T108	1
auto[0]	auto[1]	valid[0]	auto[0]	46	1			T13	2		T17	2		T18	1
auto[0]	auto[1]	valid[0]	auto[1]	225	1			T14	1		T16	1		T108	4
auto[0]	auto[1]	valid[1]	auto[0]	34	1			T13	1		T17	1		T59	2
auto[0]	auto[1]	valid[1]	auto[1]	217	1			T16	1		T21	1		T108	3
auto[0]	auto[1]	valid[2]	auto[0]	45	1			T13	6		T59	1		T61	1
auto[0]	auto[1]	valid[2]	auto[1]	220	1			T14	2		T16	2		T21	1
auto[0]	auto[1]	valid[3]	auto[0]	27	1			T13	1		T17	1		T18	1
auto[0]	auto[1]	valid[3]	auto[1]	244	1			T14	1		T16	2		T108	3
auto[0]	auto[1]	valid[4]	auto[0]	46	1			T13	3		T17	1		T59	1
auto[0]	auto[1]	valid[4]	auto[1]	257	1			T14	1		T15	1		T16	2
auto[1]	auto[0]	valid[0]	auto[0]	26	1			T61	1		T63	1		T65	1
auto[1]	auto[0]	valid[1]	auto[0]	33	1			T17	1		T19	1		T59	2
auto[1]	auto[0]	valid[2]	auto[0]	19	1			T17	1		T401	1		T399	2
auto[1]	auto[0]	valid[3]	auto[0]	35	1			T3	1		T13	2		T17	1
auto[1]	auto[0]	valid[4]	auto[0]	24	1			T59	3		T63	1		T65	1
auto[1]	auto[1]	valid[0]	auto[0]	26	1			T13	2		T84	1		T65	1
auto[1]	auto[1]	valid[1]	auto[0]	22	1			T17	1		T59	2		T65	2
auto[1]	auto[1]	valid[2]	auto[0]	18	1			T17	1		T59	1		T61	1
auto[1]	auto[1]	valid[3]	auto[0]	25	1			T59	1		T84	1		T63	1
auto[1]	auto[1]	valid[4]	auto[0]	22	1			T13	1		T59	1		T65	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal