Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17202

1

T3

15

T12

20

T13

558

auto[1]

20966

1

T14

11

T15

1

T16

201

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31640

1

T3

6

T12

11

T13

385

auto[1]

6528

1

T3

9

T12

9

T13

173

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19889	1			T3	9		T12	7		T13	285
others[1]	3148	1			T3	3		T12	3		T13	45
others[2]	3225	1			T12	1		T13	51		T16	21
others[3]	3615	1			T3	2		T12	2		T13	55
interest[1]	2134	1			T3	1		T12	2		T13	31
interest[4]	13163	1			T3	4		T12	7		T13	172
interest[64]	6157	1			T12	5		T13	91		T16	31

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5485	1			T3	4		T12	4		T13	199
auto[0]	auto[0]	others[1]	893	1			T12	2		T13	28		T17	21
auto[0]	auto[0]	others[2]	900	1			T13	35		T17	18		T18	7
auto[0]	auto[0]	others[3]	1034	1			T3	2		T13	37		T17	14
auto[0]	auto[0]	interest[1]	635	1			T12	1		T13	22		T17	17
auto[0]	auto[0]	interest[4]	3551	1			T3	2		T12	4		T13	119
auto[0]	auto[0]	interest[64]	1727	1			T12	4		T13	64		T17	47
auto[0]	auto[1]	others[0]	10998	1			T14	11		T15	1		T16	101
auto[0]	auto[1]	others[1]	1731	1			T16	18		T17	1		T59	8
auto[0]	auto[1]	others[2]	1760	1			T16	21		T17	13		T59	5
auto[0]	auto[1]	others[3]	1937	1			T16	20		T17	3		T59	3
auto[0]	auto[1]	interest[1]	1134	1			T16	10		T17	4		T59	3
auto[0]	auto[1]	interest[4]	7394	1			T14	11		T15	1		T16	65
auto[0]	auto[1]	interest[64]	3406	1			T16	31		T17	11		T59	17
auto[1]	auto[0]	others[0]	3406	1			T3	5		T12	3		T13	86
auto[1]	auto[0]	others[1]	524	1			T3	3		T12	1		T13	17
auto[1]	auto[0]	others[2]	565	1			T12	1		T13	16		T17	9
auto[1]	auto[0]	others[3]	644	1			T12	2		T13	18		T17	23
auto[1]	auto[0]	interest[1]	365	1			T3	1		T12	1		T13	9
auto[1]	auto[0]	interest[4]	2218	1			T3	2		T12	3		T13	53
auto[1]	auto[0]	interest[64]	1024	1			T12	1		T13	27		T17	29

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal