Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	447	1			T20	4		T44	4		T41	11
all_values[1]	447	1			T20	4		T44	4		T41	11
all_values[2]	447	1			T20	4		T44	4		T41	11
all_values[3]	447	1			T20	4		T44	4		T41	11
all_values[4]	447	1			T20	4		T44	4		T41	11
all_values[5]	447	1			T20	4		T44	4		T41	11
all_values[6]	447	1			T20	4		T44	4		T41	11
all_values[7]	447	1			T20	4		T44	4		T41	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1889

1

T20

19

T44

20

T41

43

auto[1]

1687

1

T20

13

T44

12

T41

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1494

1

T20

14

T44

16

T41

30

auto[1]

2082

1

T20

18

T44

16

T41

58

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2068

1

T20

20

T44

20

T41

52

auto[1]

1508

1

T20

12

T44

12

T41

36

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	114	1			T44	3		T41	2		T42	3
all_values[0]	auto[0]	auto[0]	auto[1]	33	1			T20	1		T43	2		T366	2
all_values[0]	auto[0]	auto[1]	auto[0]	73	1			T20	1		T44	1		T41	2
all_values[0]	auto[0]	auto[1]	auto[1]	36	1			T41	3		T43	1		T164	2
all_values[0]	auto[1]	auto[0]	auto[1]	103	1			T20	2		T41	1		T42	4
all_values[0]	auto[1]	auto[1]	auto[1]	88	1			T41	3		T42	3		T43	5
all_values[1]	auto[0]	auto[0]	auto[0]	96	1			T20	2		T44	1		T41	4
all_values[1]	auto[0]	auto[0]	auto[1]	48	1			T42	4		T43	2		T367	4
all_values[1]	auto[0]	auto[1]	auto[0]	72	1			T20	1		T44	1		T41	5
all_values[1]	auto[0]	auto[1]	auto[1]	34	1			T42	1		T43	3		T366	1
all_values[1]	auto[1]	auto[0]	auto[1]	92	1			T44	2		T42	4		T43	4
all_values[1]	auto[1]	auto[1]	auto[1]	105	1			T20	1		T41	2		T42	2
all_values[2]	auto[0]	auto[0]	auto[0]	98	1			T20	1		T44	2		T41	1
all_values[2]	auto[0]	auto[0]	auto[1]	39	1			T20	1		T41	2		T42	1
all_values[2]	auto[0]	auto[1]	auto[0]	84	1			T20	1		T44	1		T42	2
all_values[2]	auto[0]	auto[1]	auto[1]	42	1			T41	2		T42	2		T43	1
all_values[2]	auto[1]	auto[0]	auto[1]	95	1			T20	1		T41	3		T42	1
all_values[2]	auto[1]	auto[1]	auto[1]	89	1			T44	1		T41	3		T42	3
all_values[3]	auto[0]	auto[0]	auto[0]	84	1			T20	1		T41	3		T42	2
all_values[3]	auto[0]	auto[0]	auto[1]	34	1			T20	1		T43	2		T368	2
all_values[3]	auto[0]	auto[1]	auto[0]	78	1			T20	1		T44	2		T41	2
all_values[3]	auto[0]	auto[1]	auto[1]	45	1			T41	2		T42	1		T43	1
all_values[3]	auto[1]	auto[0]	auto[1]	117	1			T20	1		T44	1		T41	1
all_values[3]	auto[1]	auto[1]	auto[1]	89	1			T44	1		T41	3		T42	3
all_values[4]	auto[0]	auto[0]	auto[0]	85	1			T41	4		T42	2		T43	5
all_values[4]	auto[0]	auto[0]	auto[1]	44	1			T42	2		T43	1		T164	1
all_values[4]	auto[0]	auto[1]	auto[0]	79	1			T44	1		T41	2		T42	1
all_values[4]	auto[0]	auto[1]	auto[1]	35	1			T20	1		T41	2		T42	2
all_values[4]	auto[1]	auto[0]	auto[1]	115	1			T44	3		T41	1		T42	4
all_values[4]	auto[1]	auto[1]	auto[1]	89	1			T20	3		T41	2		T42	3
all_values[5]	auto[0]	auto[0]	auto[0]	151	1			T20	3		T44	2		T41	5
all_values[5]	auto[0]	auto[1]	auto[0]	117	1			T44	1		T42	3		T43	6
all_values[5]	auto[1]	auto[0]	auto[1]	99	1			T41	4		T42	4		T43	3
all_values[5]	auto[1]	auto[1]	auto[1]	80	1			T20	1		T44	1		T41	2
all_values[6]	auto[0]	auto[0]	auto[0]	95	1			T20	3		T44	1		T42	5
all_values[6]	auto[0]	auto[0]	auto[1]	42	1			T44	1		T41	3		T42	1
all_values[6]	auto[0]	auto[1]	auto[0]	91	1			T42	3		T43	5		T366	2
all_values[6]	auto[0]	auto[1]	auto[1]	54	1			T41	2		T42	1		T366	2
all_values[6]	auto[1]	auto[0]	auto[1]	77	1			T20	1		T44	2		T41	4
all_values[6]	auto[1]	auto[1]	auto[1]	88	1			T41	2		T42	3		T43	2
all_values[7]	auto[0]	auto[0]	auto[0]	92	1			T42	4		T43	4		T164	1
all_values[7]	auto[0]	auto[0]	auto[1]	45	1			T44	1		T41	3		T42	2
all_values[7]	auto[0]	auto[1]	auto[0]	85	1			T42	1		T43	4		T164	3
all_values[7]	auto[0]	auto[1]	auto[1]	43	1			T20	2		T44	2		T41	3
all_values[7]	auto[1]	auto[0]	auto[1]	91	1			T20	1		T44	1		T41	2
all_values[7]	auto[1]	auto[1]	auto[1]	91	1			T20	1		T41	3		T42	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal