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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.17 97.51 92.83 98.61 80.85 95.90 90.94 88.58


Total test records in report: 838
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T764 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2890534391 May 02 02:19:12 PM PDT 24 May 02 02:19:14 PM PDT 24 37386623 ps
T765 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.462768611 May 02 02:18:51 PM PDT 24 May 02 02:19:06 PM PDT 24 2435953661 ps
T766 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.868173691 May 02 02:19:13 PM PDT 24 May 02 02:19:17 PM PDT 24 48099018 ps
T384 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1072587934 May 02 02:19:17 PM PDT 24 May 02 02:19:31 PM PDT 24 2144502161 ps
T149 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3247665669 May 02 02:19:03 PM PDT 24 May 02 02:19:08 PM PDT 24 67896559 ps
T767 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2805069813 May 02 02:18:57 PM PDT 24 May 02 02:19:03 PM PDT 24 277664545 ps
T768 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1441041695 May 02 02:18:48 PM PDT 24 May 02 02:19:05 PM PDT 24 634946506 ps
T769 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2687856558 May 02 02:18:39 PM PDT 24 May 02 02:18:42 PM PDT 24 14079195 ps
T770 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1075206322 May 02 02:19:01 PM PDT 24 May 02 02:19:21 PM PDT 24 6015777468 ps
T771 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1482092837 May 02 02:19:27 PM PDT 24 May 02 02:19:32 PM PDT 24 15658341 ps
T103 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1326647436 May 02 02:19:00 PM PDT 24 May 02 02:19:05 PM PDT 24 19616990 ps
T772 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3377881578 May 02 02:19:05 PM PDT 24 May 02 02:19:10 PM PDT 24 205662521 ps
T773 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.121766078 May 02 02:19:24 PM PDT 24 May 02 02:19:31 PM PDT 24 198207486 ps
T774 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.921157443 May 02 02:19:00 PM PDT 24 May 02 02:19:06 PM PDT 24 154360558 ps
T386 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3458557489 May 02 02:19:08 PM PDT 24 May 02 02:19:23 PM PDT 24 852500995 ps
T775 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2146229409 May 02 02:18:50 PM PDT 24 May 02 02:18:56 PM PDT 24 64628222 ps
T776 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2851006792 May 02 02:19:04 PM PDT 24 May 02 02:19:09 PM PDT 24 149062417 ps
T777 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2899277775 May 02 02:19:26 PM PDT 24 May 02 02:19:32 PM PDT 24 29600855 ps
T778 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2508343774 May 02 02:19:29 PM PDT 24 May 02 02:19:34 PM PDT 24 54881453 ps
T779 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4222924647 May 02 02:19:13 PM PDT 24 May 02 02:19:18 PM PDT 24 534230510 ps
T780 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2294749184 May 02 02:18:48 PM PDT 24 May 02 02:18:53 PM PDT 24 322240770 ps
T781 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1321771570 May 02 02:19:01 PM PDT 24 May 02 02:19:05 PM PDT 24 17564303 ps
T782 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3213566697 May 02 02:18:50 PM PDT 24 May 02 02:18:52 PM PDT 24 16750425 ps
T783 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.708105663 May 02 02:19:23 PM PDT 24 May 02 02:19:28 PM PDT 24 136005130 ps
T784 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2499263410 May 02 02:19:23 PM PDT 24 May 02 02:19:27 PM PDT 24 11426204 ps
T104 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4149077913 May 02 02:18:59 PM PDT 24 May 02 02:19:04 PM PDT 24 17241072 ps
T785 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.526286255 May 02 02:19:30 PM PDT 24 May 02 02:19:35 PM PDT 24 16354430 ps
T786 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.389185121 May 02 02:19:07 PM PDT 24 May 02 02:19:11 PM PDT 24 73842192 ps
T388 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.227517462 May 02 02:19:06 PM PDT 24 May 02 02:19:25 PM PDT 24 1451217868 ps
T787 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1263756535 May 02 02:19:29 PM PDT 24 May 02 02:19:34 PM PDT 24 78997192 ps
T788 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1019687007 May 02 02:18:57 PM PDT 24 May 02 02:19:02 PM PDT 24 368901312 ps
T789 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.390785859 May 02 02:18:50 PM PDT 24 May 02 02:18:54 PM PDT 24 395619183 ps
T790 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.652785536 May 02 02:19:01 PM PDT 24 May 02 02:19:07 PM PDT 24 158166382 ps
T791 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.398069201 May 02 02:19:00 PM PDT 24 May 02 02:19:08 PM PDT 24 603153110 ps
T792 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.278134766 May 02 02:19:13 PM PDT 24 May 02 02:19:16 PM PDT 24 12107502 ps
T793 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.869465280 May 02 02:18:59 PM PDT 24 May 02 02:19:03 PM PDT 24 29062310 ps
T794 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3685028660 May 02 02:19:07 PM PDT 24 May 02 02:19:14 PM PDT 24 131919117 ps
T795 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2117423797 May 02 02:19:21 PM PDT 24 May 02 02:19:24 PM PDT 24 32088200 ps
T387 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2311091723 May 02 02:19:06 PM PDT 24 May 02 02:19:15 PM PDT 24 425702980 ps
T796 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2899310476 May 02 02:19:13 PM PDT 24 May 02 02:19:16 PM PDT 24 30528002 ps
T797 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1678308518 May 02 02:19:25 PM PDT 24 May 02 02:19:30 PM PDT 24 60205889 ps
T798 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1222660107 May 02 02:19:08 PM PDT 24 May 02 02:19:12 PM PDT 24 283859479 ps
T799 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.224252401 May 02 02:18:49 PM PDT 24 May 02 02:18:52 PM PDT 24 12889826 ps
T800 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.847327841 May 02 02:19:14 PM PDT 24 May 02 02:19:19 PM PDT 24 189053794 ps
T801 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1220874197 May 02 02:18:48 PM PDT 24 May 02 02:18:54 PM PDT 24 162013939 ps
T133 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2854891273 May 02 02:19:15 PM PDT 24 May 02 02:19:19 PM PDT 24 155936680 ps
T802 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3141781646 May 02 02:18:55 PM PDT 24 May 02 02:18:58 PM PDT 24 132385878 ps
T803 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2433777946 May 02 02:18:58 PM PDT 24 May 02 02:19:02 PM PDT 24 12330635 ps
T804 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1663945910 May 02 02:19:24 PM PDT 24 May 02 02:19:28 PM PDT 24 51381069 ps
T805 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2725207138 May 02 02:19:29 PM PDT 24 May 02 02:19:34 PM PDT 24 31166258 ps
T806 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3025134711 May 02 02:19:28 PM PDT 24 May 02 02:19:33 PM PDT 24 14385942 ps
T807 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1559308275 May 02 02:19:29 PM PDT 24 May 02 02:19:33 PM PDT 24 43406874 ps
T808 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3078829177 May 02 02:19:01 PM PDT 24 May 02 02:19:17 PM PDT 24 721460940 ps
T809 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2832948389 May 02 02:18:49 PM PDT 24 May 02 02:18:54 PM PDT 24 300284550 ps
T810 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3973781521 May 02 02:18:57 PM PDT 24 May 02 02:19:02 PM PDT 24 107364976 ps
T811 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.430188085 May 02 02:19:08 PM PDT 24 May 02 02:19:14 PM PDT 24 900557505 ps
T105 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3372378967 May 02 02:18:49 PM PDT 24 May 02 02:18:52 PM PDT 24 65623869 ps
T381 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2556135153 May 02 02:18:48 PM PDT 24 May 02 02:18:54 PM PDT 24 597155288 ps
T812 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2386270966 May 02 02:18:42 PM PDT 24 May 02 02:18:47 PM PDT 24 242200755 ps
T390 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2907803619 May 02 02:18:46 PM PDT 24 May 02 02:19:08 PM PDT 24 816498704 ps
T813 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1276568110 May 02 02:18:57 PM PDT 24 May 02 02:19:02 PM PDT 24 20248382 ps
T814 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1490983458 May 02 02:19:06 PM PDT 24 May 02 02:19:11 PM PDT 24 76136818 ps
T815 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.928810601 May 02 02:19:06 PM PDT 24 May 02 02:19:23 PM PDT 24 622932336 ps
T816 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1676008240 May 02 02:19:24 PM PDT 24 May 02 02:19:28 PM PDT 24 39673270 ps
T817 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4157772739 May 02 02:19:02 PM PDT 24 May 02 02:19:13 PM PDT 24 113439197 ps
T818 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3410289057 May 02 02:18:40 PM PDT 24 May 02 02:18:42 PM PDT 24 104537212 ps
T819 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.890916661 May 02 02:19:05 PM PDT 24 May 02 02:19:08 PM PDT 24 37325702 ps
T391 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2136219562 May 02 02:18:57 PM PDT 24 May 02 02:19:18 PM PDT 24 1142021291 ps
T820 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1317637496 May 02 02:19:06 PM PDT 24 May 02 02:19:09 PM PDT 24 23477202 ps
T821 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4091171877 May 02 02:19:22 PM PDT 24 May 02 02:19:25 PM PDT 24 25903280 ps
T822 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1189738069 May 02 02:19:06 PM PDT 24 May 02 02:19:10 PM PDT 24 29839135 ps
T823 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1314095483 May 02 02:19:07 PM PDT 24 May 02 02:19:13 PM PDT 24 137995993 ps
T824 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2716232928 May 02 02:19:24 PM PDT 24 May 02 02:19:28 PM PDT 24 28344890 ps
T825 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2662645628 May 02 02:19:06 PM PDT 24 May 02 02:19:11 PM PDT 24 110522142 ps
T826 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4049105716 May 02 02:19:22 PM PDT 24 May 02 02:19:28 PM PDT 24 626168908 ps
T827 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3347519541 May 02 02:19:05 PM PDT 24 May 02 02:19:09 PM PDT 24 65321632 ps
T828 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2314140412 May 02 02:19:08 PM PDT 24 May 02 02:19:14 PM PDT 24 141650385 ps
T829 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3307778698 May 02 02:19:08 PM PDT 24 May 02 02:19:12 PM PDT 24 24772799 ps
T131 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2071458491 May 02 02:19:01 PM PDT 24 May 02 02:19:25 PM PDT 24 1171284021 ps
T830 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1221604023 May 02 02:19:29 PM PDT 24 May 02 02:19:34 PM PDT 24 11090098 ps
T831 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1089598420 May 02 02:19:24 PM PDT 24 May 02 02:19:28 PM PDT 24 25083196 ps
T832 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2002439831 May 02 02:19:12 PM PDT 24 May 02 02:19:16 PM PDT 24 132483523 ps
T833 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3330772219 May 02 02:19:00 PM PDT 24 May 02 02:19:07 PM PDT 24 132247209 ps
T834 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1446996226 May 02 02:19:04 PM PDT 24 May 02 02:19:29 PM PDT 24 1594007874 ps
T835 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2401034539 May 02 02:19:13 PM PDT 24 May 02 02:19:18 PM PDT 24 209129846 ps
T836 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1764627122 May 02 02:19:11 PM PDT 24 May 02 02:19:37 PM PDT 24 1137226782 ps
T837 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1411635894 May 02 02:19:21 PM PDT 24 May 02 02:19:25 PM PDT 24 95301393 ps
T838 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2843484964 May 02 02:18:51 PM PDT 24 May 02 02:18:53 PM PDT 24 16412609 ps

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2263810719
Short name T4
Test name
Test status
Simulation time 5110502553 ps
CPU time 12.27 seconds
Started May 02 02:09:43 PM PDT 24
Finished May 02 02:09:57 PM PDT 24
Peak memory 224536 kb
Host smart-65de5312-e280-41d6-a90d-5fdd72ce643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263810719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2263810719
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3698553299
Short name T17
Test name
Test status
Simulation time 4442479862 ps
CPU time 30.57 seconds
Started May 02 02:10:03 PM PDT 24
Finished May 02 02:10:36 PM PDT 24
Peak memory 216624 kb
Host smart-1d69fd2f-6a9d-4305-a982-cb5b39ea6931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698553299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3698553299
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2710569497
Short name T47
Test name
Test status
Simulation time 807165069 ps
CPU time 13 seconds
Started May 02 02:07:58 PM PDT 24
Finished May 02 02:08:12 PM PDT 24
Peak memory 232220 kb
Host smart-1e6c26bf-ee33-46eb-85b6-e65836f1e05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710569497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2710569497
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_upload.2929456121
Short name T27
Test name
Test status
Simulation time 2020660647 ps
CPU time 8.46 seconds
Started May 02 02:10:20 PM PDT 24
Finished May 02 02:10:29 PM PDT 24
Peak memory 219844 kb
Host smart-2953820e-20a7-40b1-8038-cb6dc9d30758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929456121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2929456121
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1339194376
Short name T115
Test name
Test status
Simulation time 1346163043 ps
CPU time 15.57 seconds
Started May 02 02:19:03 PM PDT 24
Finished May 02 02:19:21 PM PDT 24
Peak memory 215120 kb
Host smart-f8165027-03a0-42a0-8ca6-95b655f4d380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339194376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1339194376
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4287479632
Short name T13
Test name
Test status
Simulation time 24572607432 ps
CPU time 39.38 seconds
Started May 02 02:09:19 PM PDT 24
Finished May 02 02:10:00 PM PDT 24
Peak memory 216384 kb
Host smart-4a4d3d55-0a6c-48eb-9486-6704a7fdabed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287479632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4287479632
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.272844576
Short name T43
Test name
Test status
Simulation time 57827176 ps
CPU time 1.21 seconds
Started May 02 02:10:03 PM PDT 24
Finished May 02 02:10:07 PM PDT 24
Peak memory 207040 kb
Host smart-585a42f0-3ba2-4082-a60f-690cc4aab3c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272844576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.272844576
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1825099282
Short name T95
Test name
Test status
Simulation time 33290305613 ps
CPU time 78.47 seconds
Started May 02 02:09:34 PM PDT 24
Finished May 02 02:10:53 PM PDT 24
Peak memory 221384 kb
Host smart-3f79d4bd-d97d-4ba1-b499-e7b987496229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825099282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1825099282
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1500266689
Short name T68
Test name
Test status
Simulation time 119022134258 ps
CPU time 27.8 seconds
Started May 02 02:11:07 PM PDT 24
Finished May 02 02:11:36 PM PDT 24
Peak memory 223860 kb
Host smart-220a17df-cb81-49d0-a0a2-ed45179d3bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500266689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1500266689
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2753332944
Short name T1
Test name
Test status
Simulation time 848479572 ps
CPU time 4.13 seconds
Started May 02 02:08:57 PM PDT 24
Finished May 02 02:09:02 PM PDT 24
Peak memory 218456 kb
Host smart-6a2d3aff-82bd-4d5d-b901-2fceb1437827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753332944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2753332944
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1751838428
Short name T394
Test name
Test status
Simulation time 2610542575 ps
CPU time 31.46 seconds
Started May 02 02:10:57 PM PDT 24
Finished May 02 02:11:29 PM PDT 24
Peak memory 216364 kb
Host smart-0367d885-52ee-4724-8633-6b64e3f9fed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751838428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1751838428
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2332512852
Short name T45
Test name
Test status
Simulation time 108708567 ps
CPU time 0.73 seconds
Started May 02 02:06:24 PM PDT 24
Finished May 02 02:06:26 PM PDT 24
Peak memory 216172 kb
Host smart-4167b8a5-13de-4ea4-a8cf-b7ef5c406cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332512852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2332512852
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.457031954
Short name T89
Test name
Test status
Simulation time 5971181331 ps
CPU time 76.77 seconds
Started May 02 02:10:12 PM PDT 24
Finished May 02 02:11:30 PM PDT 24
Peak memory 235324 kb
Host smart-bbe5735a-9ffe-4f2d-98b0-05798951f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457031954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.457031954
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.392270080
Short name T409
Test name
Test status
Simulation time 5065233095 ps
CPU time 39.44 seconds
Started May 02 02:10:12 PM PDT 24
Finished May 02 02:10:52 PM PDT 24
Peak memory 220964 kb
Host smart-c87c9ece-5b7c-4424-a67e-3b1f9e14c7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392270080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.392270080
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2468666050
Short name T281
Test name
Test status
Simulation time 1644628292 ps
CPU time 6.83 seconds
Started May 02 02:11:35 PM PDT 24
Finished May 02 02:11:43 PM PDT 24
Peak memory 216744 kb
Host smart-0d6190e2-b940-4954-ae8e-8b5cadc888b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468666050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2468666050
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1812458452
Short name T119
Test name
Test status
Simulation time 74758338 ps
CPU time 4.8 seconds
Started May 02 02:19:05 PM PDT 24
Finished May 02 02:19:12 PM PDT 24
Peak memory 215164 kb
Host smart-d8a0940b-5290-446c-be9c-7002f1fafd80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812458452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1812458452
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1780628654
Short name T33
Test name
Test status
Simulation time 398925381 ps
CPU time 1.01 seconds
Started May 02 02:06:52 PM PDT 24
Finished May 02 02:06:54 PM PDT 24
Peak memory 235152 kb
Host smart-b5da9127-10d5-4e86-9e61-62b36178d14c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780628654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1780628654
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.204975787
Short name T232
Test name
Test status
Simulation time 6114157370 ps
CPU time 56.36 seconds
Started May 02 02:12:04 PM PDT 24
Finished May 02 02:13:02 PM PDT 24
Peak memory 230876 kb
Host smart-f7440177-04a7-43e5-ad05-09f1e9104dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204975787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.204975787
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4210437899
Short name T63
Test name
Test status
Simulation time 17728675804 ps
CPU time 41.78 seconds
Started May 02 02:06:56 PM PDT 24
Finished May 02 02:07:39 PM PDT 24
Peak memory 216360 kb
Host smart-09d95a5d-dc11-4460-84db-8374e7179c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210437899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4210437899
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.730527242
Short name T188
Test name
Test status
Simulation time 22914383891 ps
CPU time 32.13 seconds
Started May 02 02:07:56 PM PDT 24
Finished May 02 02:08:30 PM PDT 24
Peak memory 223924 kb
Host smart-6f2ef740-2949-4edb-a078-df3871345586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730527242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.730527242
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2087230576
Short name T282
Test name
Test status
Simulation time 2319838440 ps
CPU time 6.97 seconds
Started May 02 02:06:41 PM PDT 24
Finished May 02 02:06:49 PM PDT 24
Peak memory 223696 kb
Host smart-a248533c-17a3-4a8f-853d-040854468056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087230576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2087230576
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2063793463
Short name T141
Test name
Test status
Simulation time 122461554 ps
CPU time 1.98 seconds
Started May 02 02:18:58 PM PDT 24
Finished May 02 02:19:04 PM PDT 24
Peak memory 215100 kb
Host smart-33449dff-22c8-426d-a4e8-fd87d74bd321
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063793463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
063793463
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3984787547
Short name T97
Test name
Test status
Simulation time 810231012 ps
CPU time 7.42 seconds
Started May 02 02:08:11 PM PDT 24
Finished May 02 02:08:20 PM PDT 24
Peak memory 223504 kb
Host smart-13f32002-b5a0-44ad-83ac-6462505b9aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984787547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3984787547
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_upload.410245914
Short name T345
Test name
Test status
Simulation time 2456568721 ps
CPU time 6.97 seconds
Started May 02 02:08:44 PM PDT 24
Finished May 02 02:08:53 PM PDT 24
Peak memory 224736 kb
Host smart-a5c11142-3e76-4a33-9ece-8b0fd469910b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410245914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.410245914
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2311587743
Short name T349
Test name
Test status
Simulation time 18861968160 ps
CPU time 12.55 seconds
Started May 02 02:11:18 PM PDT 24
Finished May 02 02:11:33 PM PDT 24
Peak memory 232712 kb
Host smart-e6de1ba0-e651-45a4-9b6d-7eab62004802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311587743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2311587743
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2032795703
Short name T238
Test name
Test status
Simulation time 8671692022 ps
CPU time 23.29 seconds
Started May 02 02:08:54 PM PDT 24
Finished May 02 02:09:19 PM PDT 24
Peak memory 224512 kb
Host smart-b3979af0-de3b-4692-9678-5ceb6ab7abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032795703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2032795703
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4282234750
Short name T82
Test name
Test status
Simulation time 2835837373 ps
CPU time 6.25 seconds
Started May 02 02:07:30 PM PDT 24
Finished May 02 02:07:38 PM PDT 24
Peak memory 219836 kb
Host smart-6cbee6b4-091d-4900-817b-a5ed0a6da32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282234750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4282234750
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_upload.1299927264
Short name T9
Test name
Test status
Simulation time 1601062469 ps
CPU time 6.33 seconds
Started May 02 02:06:33 PM PDT 24
Finished May 02 02:06:41 PM PDT 24
Peak memory 222076 kb
Host smart-018e33e2-dc05-40aa-a0f1-0e31f482207e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299927264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1299927264
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.306416606
Short name T96
Test name
Test status
Simulation time 1409858276 ps
CPU time 28.45 seconds
Started May 02 02:07:13 PM PDT 24
Finished May 02 02:07:42 PM PDT 24
Peak memory 233724 kb
Host smart-5a6ca09d-adeb-4482-9d82-a600adebdd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306416606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.306416606
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2577099281
Short name T157
Test name
Test status
Simulation time 1835580827 ps
CPU time 30.5 seconds
Started May 02 02:07:06 PM PDT 24
Finished May 02 02:07:38 PM PDT 24
Peak memory 232836 kb
Host smart-7145443b-40d7-43ab-9a93-efa76d6be63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577099281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2577099281
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2523073407
Short name T299
Test name
Test status
Simulation time 27401235068 ps
CPU time 21.04 seconds
Started May 02 02:07:12 PM PDT 24
Finished May 02 02:07:34 PM PDT 24
Peak memory 232712 kb
Host smart-9289e278-3029-4498-b2cf-adaff1500a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523073407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2523073407
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3911751834
Short name T290
Test name
Test status
Simulation time 9715801977 ps
CPU time 12.28 seconds
Started May 02 02:08:10 PM PDT 24
Finished May 02 02:08:24 PM PDT 24
Peak memory 236680 kb
Host smart-66f803fa-c9ca-4704-b7e0-8fc2116c3429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911751834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3911751834
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1932686120
Short name T403
Test name
Test status
Simulation time 8043241965 ps
CPU time 33.95 seconds
Started May 02 02:06:48 PM PDT 24
Finished May 02 02:07:23 PM PDT 24
Peak memory 216268 kb
Host smart-9aa6f9a9-d2f4-442d-97b5-9198382627c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932686120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1932686120
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2553759884
Short name T191
Test name
Test status
Simulation time 25103795689 ps
CPU time 98.61 seconds
Started May 02 02:10:59 PM PDT 24
Finished May 02 02:12:39 PM PDT 24
Peak memory 237132 kb
Host smart-6c62a01c-20ce-418d-974f-1d979b6b5417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553759884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2553759884
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3411741361
Short name T216
Test name
Test status
Simulation time 12464073537 ps
CPU time 70.85 seconds
Started May 02 02:08:05 PM PDT 24
Finished May 02 02:09:17 PM PDT 24
Peak memory 224448 kb
Host smart-e48d2628-61f2-43fb-b47b-18373ac429d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411741361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3411741361
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.711644042
Short name T350
Test name
Test status
Simulation time 2773598004 ps
CPU time 9.03 seconds
Started May 02 02:09:34 PM PDT 24
Finished May 02 02:09:44 PM PDT 24
Peak memory 218552 kb
Host smart-51b85ed5-9b2f-48b0-b3cf-5959f8e974ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711644042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.711644042
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.999757850
Short name T292
Test name
Test status
Simulation time 22312601161 ps
CPU time 27.9 seconds
Started May 02 02:08:56 PM PDT 24
Finished May 02 02:09:26 PM PDT 24
Peak memory 219380 kb
Host smart-157959f6-3d28-4275-8b00-da4a3bccb023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999757850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.999757850
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2209544781
Short name T94
Test name
Test status
Simulation time 14770027180 ps
CPU time 24.13 seconds
Started May 02 02:07:15 PM PDT 24
Finished May 02 02:07:40 PM PDT 24
Peak memory 224600 kb
Host smart-23094483-181c-4732-bd31-fb85a264a40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209544781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2209544781
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1384071627
Short name T368
Test name
Test status
Simulation time 742141383 ps
CPU time 0.98 seconds
Started May 02 02:07:57 PM PDT 24
Finished May 02 02:07:59 PM PDT 24
Peak memory 207016 kb
Host smart-b46e49cf-e9d8-422c-9a08-dd9fda004daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384071627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1384071627
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2774143179
Short name T122
Test name
Test status
Simulation time 29012015428 ps
CPU time 120.76 seconds
Started May 02 02:08:30 PM PDT 24
Finished May 02 02:10:32 PM PDT 24
Peak memory 218816 kb
Host smart-73b315bd-5689-4660-bdca-1a7cfc6f888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774143179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2774143179
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1080062409
Short name T218
Test name
Test status
Simulation time 2124314621 ps
CPU time 7.84 seconds
Started May 02 02:08:29 PM PDT 24
Finished May 02 02:08:38 PM PDT 24
Peak memory 223988 kb
Host smart-b57063ae-2895-4148-9e79-9e69d02e1b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080062409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1080062409
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_intercept.483616146
Short name T326
Test name
Test status
Simulation time 252311389 ps
CPU time 4.34 seconds
Started May 02 02:11:50 PM PDT 24
Finished May 02 02:11:56 PM PDT 24
Peak memory 218516 kb
Host smart-bad418cd-8b2c-49b5-bca0-bc0820538e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483616146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.483616146
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3874893368
Short name T85
Test name
Test status
Simulation time 42608444826 ps
CPU time 27.23 seconds
Started May 02 02:06:27 PM PDT 24
Finished May 02 02:06:56 PM PDT 24
Peak memory 216332 kb
Host smart-b5de36ba-5ff3-4b3c-bdae-e08384cabdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874893368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3874893368
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3820810736
Short name T53
Test name
Test status
Simulation time 1547288385 ps
CPU time 23.26 seconds
Started May 02 02:10:22 PM PDT 24
Finished May 02 02:10:46 PM PDT 24
Peak memory 222612 kb
Host smart-ca8a15b9-d2c6-4b97-b585-01a5af76394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820810736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3820810736
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2123018494
Short name T76
Test name
Test status
Simulation time 5757112826 ps
CPU time 17.87 seconds
Started May 02 02:10:53 PM PDT 24
Finished May 02 02:11:12 PM PDT 24
Peak memory 235064 kb
Host smart-5f3612ad-037d-4a41-ac6d-8ad187d298f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123018494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2123018494
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_upload.3991812907
Short name T203
Test name
Test status
Simulation time 11860034349 ps
CPU time 20.34 seconds
Started May 02 02:07:41 PM PDT 24
Finished May 02 02:08:03 PM PDT 24
Peak memory 224496 kb
Host smart-b19cbf7e-f1f0-4be1-a2bd-025d68bf1427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991812907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3991812907
Directory /workspace/9.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3847039363
Short name T193
Test name
Test status
Simulation time 17229543111 ps
CPU time 23.65 seconds
Started May 02 02:06:33 PM PDT 24
Finished May 02 02:06:58 PM PDT 24
Peak memory 237236 kb
Host smart-7c8f174b-d23c-48cc-82a1-6d5a71cfe0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847039363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3847039363
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3757726554
Short name T324
Test name
Test status
Simulation time 1785759726 ps
CPU time 8.17 seconds
Started May 02 02:08:33 PM PDT 24
Finished May 02 02:08:42 PM PDT 24
Peak memory 218516 kb
Host smart-1995ffa6-f83c-4316-9732-8226ae9598d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757726554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3757726554
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2628903027
Short name T262
Test name
Test status
Simulation time 1344339477 ps
CPU time 16.27 seconds
Started May 02 02:09:03 PM PDT 24
Finished May 02 02:09:22 PM PDT 24
Peak memory 218484 kb
Host smart-ddf7058b-7538-4653-85d4-9a9f75bc7c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628903027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2628903027
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.100935582
Short name T400
Test name
Test status
Simulation time 5639902395 ps
CPU time 28.18 seconds
Started May 02 02:09:35 PM PDT 24
Finished May 02 02:10:04 PM PDT 24
Peak memory 216392 kb
Host smart-c2e36864-d4f2-4b22-a34f-8b6af9000a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100935582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.100935582
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3261584647
Short name T449
Test name
Test status
Simulation time 15349683 ps
CPU time 0.73 seconds
Started May 02 02:08:07 PM PDT 24
Finished May 02 02:08:10 PM PDT 24
Peak memory 205412 kb
Host smart-67845a77-6902-4243-963d-8ff37b49e775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261584647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3261584647
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3435970558
Short name T383
Test name
Test status
Simulation time 304467436 ps
CPU time 19.56 seconds
Started May 02 02:19:13 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 216984 kb
Host smart-f7c73ce9-73e3-445a-9958-e8e890691de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435970558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3435970558
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4185243710
Short name T295
Test name
Test status
Simulation time 1499817551 ps
CPU time 10.71 seconds
Started May 02 02:09:11 PM PDT 24
Finished May 02 02:09:23 PM PDT 24
Peak memory 222876 kb
Host smart-cac83aff-c1a6-4373-8ee8-696b3251b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185243710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4185243710
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3957106079
Short name T348
Test name
Test status
Simulation time 3082922458 ps
CPU time 10.45 seconds
Started May 02 02:06:52 PM PDT 24
Finished May 02 02:07:03 PM PDT 24
Peak memory 216784 kb
Host smart-15bc0cae-a9d5-4105-be65-be8409f88f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957106079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3957106079
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.556216560
Short name T194
Test name
Test status
Simulation time 1922883354 ps
CPU time 8.75 seconds
Started May 02 02:11:16 PM PDT 24
Finished May 02 02:11:26 PM PDT 24
Peak memory 232656 kb
Host smart-c02f73d3-14e4-4b0e-9509-299fb0170149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556216560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.556216560
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2556135153
Short name T381
Test name
Test status
Simulation time 597155288 ps
CPU time 4.2 seconds
Started May 02 02:18:48 PM PDT 24
Finished May 02 02:18:54 PM PDT 24
Peak memory 215232 kb
Host smart-40b17e63-6928-46f6-9052-0e95c34cef3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556135153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
556135153
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/7.spi_device_upload.360725510
Short name T26
Test name
Test status
Simulation time 47841405289 ps
CPU time 21.89 seconds
Started May 02 02:07:29 PM PDT 24
Finished May 02 02:07:53 PM PDT 24
Peak memory 224584 kb
Host smart-0066a021-8cc9-4fd8-aa7f-ddd15c0e4ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360725510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.360725510
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_upload.1426629352
Short name T339
Test name
Test status
Simulation time 24826570669 ps
CPU time 19.76 seconds
Started May 02 02:07:43 PM PDT 24
Finished May 02 02:08:04 PM PDT 24
Peak memory 232740 kb
Host smart-3fe51ce3-5595-46f7-b02a-518e8ffbaa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426629352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1426629352
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4182802525
Short name T353
Test name
Test status
Simulation time 362218901 ps
CPU time 3.48 seconds
Started May 02 02:08:04 PM PDT 24
Finished May 02 02:08:09 PM PDT 24
Peak memory 218912 kb
Host smart-a53bb755-9544-43ed-bfbb-24bc80155a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182802525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4182802525
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4067237438
Short name T362
Test name
Test status
Simulation time 60357597523 ps
CPU time 44.05 seconds
Started May 02 02:08:28 PM PDT 24
Finished May 02 02:09:13 PM PDT 24
Peak memory 236932 kb
Host smart-1053af06-7205-493f-aa4f-80056fdf9b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067237438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4067237438
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.203533355
Short name T79
Test name
Test status
Simulation time 5939942636 ps
CPU time 10.36 seconds
Started May 02 02:08:45 PM PDT 24
Finished May 02 02:08:57 PM PDT 24
Peak memory 226960 kb
Host smart-81296802-3c15-472a-85c3-49a05660d476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203533355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.203533355
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.755634381
Short name T304
Test name
Test status
Simulation time 1036189488 ps
CPU time 12.87 seconds
Started May 02 02:09:11 PM PDT 24
Finished May 02 02:09:26 PM PDT 24
Peak memory 249244 kb
Host smart-ade7c5fb-0a98-4c77-aa16-a42d0520c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755634381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.755634381
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1152957242
Short name T314
Test name
Test status
Simulation time 5155167347 ps
CPU time 68.02 seconds
Started May 02 02:09:44 PM PDT 24
Finished May 02 02:10:53 PM PDT 24
Peak memory 232796 kb
Host smart-fa3a166d-185c-4d14-8cd5-cd018014dd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152957242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1152957242
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2542880345
Short name T246
Test name
Test status
Simulation time 1266404344 ps
CPU time 9.96 seconds
Started May 02 02:09:33 PM PDT 24
Finished May 02 02:09:44 PM PDT 24
Peak memory 218992 kb
Host smart-3d6fac50-94d9-4d58-8e56-8b68321eea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542880345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2542880345
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1461341774
Short name T225
Test name
Test status
Simulation time 83518689 ps
CPU time 2.3 seconds
Started May 02 02:10:18 PM PDT 24
Finished May 02 02:10:21 PM PDT 24
Peak memory 218576 kb
Host smart-68542346-ab6c-42ea-ac51-3a62f71ea92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461341774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1461341774
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2232498153
Short name T323
Test name
Test status
Simulation time 6896473929 ps
CPU time 22.85 seconds
Started May 02 02:11:02 PM PDT 24
Finished May 02 02:11:27 PM PDT 24
Peak memory 237496 kb
Host smart-f4d975d8-6d5c-4ab4-8b22-c51b59a69ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232498153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2232498153
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2050653487
Short name T182
Test name
Test status
Simulation time 24437075161 ps
CPU time 125.92 seconds
Started May 02 02:07:42 PM PDT 24
Finished May 02 02:09:49 PM PDT 24
Peak memory 236784 kb
Host smart-bfdab8df-fe7d-4dd2-a347-2a76f8b0915f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050653487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2050653487
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.461085025
Short name T327
Test name
Test status
Simulation time 589015906 ps
CPU time 9.97 seconds
Started May 02 02:07:45 PM PDT 24
Finished May 02 02:07:56 PM PDT 24
Peak memory 218796 kb
Host smart-6f841b2d-b4f7-484f-8ab0-6eb25d3f0bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461085025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.461085025
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1920791975
Short name T291
Test name
Test status
Simulation time 50601538588 ps
CPU time 28.92 seconds
Started May 02 02:07:43 PM PDT 24
Finished May 02 02:08:13 PM PDT 24
Peak memory 223496 kb
Host smart-013d55ce-8fb7-4288-9dda-05373af4c57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920791975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1920791975
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2479348418
Short name T289
Test name
Test status
Simulation time 627531095 ps
CPU time 9.28 seconds
Started May 02 02:08:04 PM PDT 24
Finished May 02 02:08:15 PM PDT 24
Peak memory 222840 kb
Host smart-7f464ff3-6341-4ba9-806a-9dbd8e6c3eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479348418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2479348418
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1804819966
Short name T239
Test name
Test status
Simulation time 8618512404 ps
CPU time 6.69 seconds
Started May 02 02:08:05 PM PDT 24
Finished May 02 02:08:13 PM PDT 24
Peak memory 219040 kb
Host smart-176e8e92-264f-448e-b678-32d52785bcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804819966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1804819966
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2776977110
Short name T71
Test name
Test status
Simulation time 31932110808 ps
CPU time 7.55 seconds
Started May 02 02:08:24 PM PDT 24
Finished May 02 02:08:33 PM PDT 24
Peak memory 222624 kb
Host smart-077856e0-f024-4b39-a8a6-9df3708a1105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776977110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2776977110
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3244561883
Short name T170
Test name
Test status
Simulation time 4671877720 ps
CPU time 13.23 seconds
Started May 02 02:08:13 PM PDT 24
Finished May 02 02:08:27 PM PDT 24
Peak memory 216556 kb
Host smart-23ba5f55-256a-44a2-8831-f86523324411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244561883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3244561883
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.140535892
Short name T305
Test name
Test status
Simulation time 20711753716 ps
CPU time 98.32 seconds
Started May 02 02:08:38 PM PDT 24
Finished May 02 02:10:18 PM PDT 24
Peak memory 240960 kb
Host smart-57dd8e85-4c88-4946-a0d9-eb966be38aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140535892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.140535892
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3296709939
Short name T181
Test name
Test status
Simulation time 4097089311 ps
CPU time 13.05 seconds
Started May 02 02:08:34 PM PDT 24
Finished May 02 02:08:49 PM PDT 24
Peak memory 231828 kb
Host smart-bc276a8a-a4a8-4e2f-9477-b3ad348074c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296709939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3296709939
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2065984453
Short name T293
Test name
Test status
Simulation time 12150597629 ps
CPU time 12.9 seconds
Started May 02 02:09:01 PM PDT 24
Finished May 02 02:09:16 PM PDT 24
Peak memory 232756 kb
Host smart-d786da9d-9705-4196-aaff-19548d464c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065984453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2065984453
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1400015913
Short name T294
Test name
Test status
Simulation time 5398664927 ps
CPU time 10.95 seconds
Started May 02 02:09:12 PM PDT 24
Finished May 02 02:09:25 PM PDT 24
Peak memory 235076 kb
Host smart-5c43297a-9e30-449c-ac45-e4329adc7498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400015913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1400015913
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3959589727
Short name T284
Test name
Test status
Simulation time 14893098999 ps
CPU time 137.96 seconds
Started May 02 02:09:28 PM PDT 24
Finished May 02 02:11:47 PM PDT 24
Peak memory 251624 kb
Host smart-25d506ed-9b46-4fc1-b0f5-104aa494cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959589727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3959589727
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1786920271
Short name T78
Test name
Test status
Simulation time 1960290604 ps
CPU time 18.49 seconds
Started May 02 02:11:01 PM PDT 24
Finished May 02 02:11:21 PM PDT 24
Peak memory 239688 kb
Host smart-736d698f-e4d5-4052-9466-44bed7203118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786920271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1786920271
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1550095523
Short name T354
Test name
Test status
Simulation time 133276095 ps
CPU time 4.01 seconds
Started May 02 02:11:39 PM PDT 24
Finished May 02 02:11:44 PM PDT 24
Peak memory 218544 kb
Host smart-e77a756a-2f98-4e6f-9859-67313c310128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550095523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1550095523
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2464735736
Short name T87
Test name
Test status
Simulation time 44226018266 ps
CPU time 58.57 seconds
Started May 02 02:11:50 PM PDT 24
Finished May 02 02:12:50 PM PDT 24
Peak memory 234512 kb
Host smart-df53ab1f-a2f5-4d6c-9a0d-18281d509812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464735736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2464735736
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1144121002
Short name T67
Test name
Test status
Simulation time 283297274 ps
CPU time 4.59 seconds
Started May 02 02:11:49 PM PDT 24
Finished May 02 02:11:55 PM PDT 24
Peak memory 221400 kb
Host smart-f91348b9-e0a3-42fe-b585-b0eb0960d04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144121002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1144121002
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3287877285
Short name T81
Test name
Test status
Simulation time 19611405656 ps
CPU time 20.28 seconds
Started May 02 02:07:24 PM PDT 24
Finished May 02 02:07:46 PM PDT 24
Peak memory 218964 kb
Host smart-41f97a74-80b0-4c9e-89a3-9304cf64dc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287877285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3287877285
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_upload.995756229
Short name T244
Test name
Test status
Simulation time 1119575554 ps
CPU time 5.68 seconds
Started May 02 02:07:29 PM PDT 24
Finished May 02 02:07:36 PM PDT 24
Peak memory 223504 kb
Host smart-434a61f8-1ec2-46eb-9f1f-f8016efc25c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995756229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.995756229
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2053065493
Short name T113
Test name
Test status
Simulation time 4110003893 ps
CPU time 55.85 seconds
Started May 02 02:11:25 PM PDT 24
Finished May 02 02:12:22 PM PDT 24
Peak memory 240916 kb
Host smart-f66e397c-285b-47b7-91cc-75fb404a728b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053065493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2053065493
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2907803619
Short name T390
Test name
Test status
Simulation time 816498704 ps
CPU time 20.75 seconds
Started May 02 02:18:46 PM PDT 24
Finished May 02 02:19:08 PM PDT 24
Peak memory 215084 kb
Host smart-329bfb4a-9af9-4b8d-ac57-e0dbe4a8cfe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907803619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2907803619
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3539326726
Short name T185
Test name
Test status
Simulation time 970158700 ps
CPU time 5.07 seconds
Started May 02 02:06:24 PM PDT 24
Finished May 02 02:06:31 PM PDT 24
Peak memory 218640 kb
Host smart-a262ee73-cb19-4734-b992-67278e2eb57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539326726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3539326726
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.750032464
Short name T335
Test name
Test status
Simulation time 8737002941 ps
CPU time 24.88 seconds
Started May 02 02:06:32 PM PDT 24
Finished May 02 02:06:58 PM PDT 24
Peak memory 218756 kb
Host smart-9bb16ebe-5442-4fb9-9d72-2afd57867222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750032464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.750032464
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2904881042
Short name T230
Test name
Test status
Simulation time 2328409994 ps
CPU time 16.21 seconds
Started May 02 02:07:48 PM PDT 24
Finished May 02 02:08:04 PM PDT 24
Peak memory 223672 kb
Host smart-329ac3c1-d5ec-437f-a54b-f1ae988a1673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904881042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2904881042
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1843050978
Short name T209
Test name
Test status
Simulation time 4266095840 ps
CPU time 13.99 seconds
Started May 02 02:08:30 PM PDT 24
Finished May 02 02:08:45 PM PDT 24
Peak memory 221444 kb
Host smart-0018132e-3418-4ad8-bb61-d676ca0520f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843050978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1843050978
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.83433867
Short name T107
Test name
Test status
Simulation time 178881119 ps
CPU time 1.38 seconds
Started May 02 02:08:50 PM PDT 24
Finished May 02 02:08:53 PM PDT 24
Peak memory 208132 kb
Host smart-05cbe579-dd33-4393-bf3c-0ed1f35388c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83433867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.83433867
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1104418186
Short name T286
Test name
Test status
Simulation time 1695012236 ps
CPU time 7.31 seconds
Started May 02 02:09:04 PM PDT 24
Finished May 02 02:09:14 PM PDT 24
Peak memory 224380 kb
Host smart-c2db5f38-ef57-435d-9d10-5b7bb0ff068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104418186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1104418186
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1600399443
Short name T280
Test name
Test status
Simulation time 4739905342 ps
CPU time 8.1 seconds
Started May 02 02:09:35 PM PDT 24
Finished May 02 02:09:44 PM PDT 24
Peak memory 223832 kb
Host smart-65fbd187-1702-462b-8e3d-0f18b1bdfcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600399443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1600399443
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1649707073
Short name T77
Test name
Test status
Simulation time 1687457177 ps
CPU time 6.17 seconds
Started May 02 02:09:43 PM PDT 24
Finished May 02 02:09:51 PM PDT 24
Peak memory 219040 kb
Host smart-82c00d9e-822a-4ddd-bd97-914b1c8659c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649707073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1649707073
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3535744779
Short name T98
Test name
Test status
Simulation time 473405850 ps
CPU time 5 seconds
Started May 02 02:06:48 PM PDT 24
Finished May 02 02:06:54 PM PDT 24
Peak memory 218532 kb
Host smart-b72d3a22-2bb5-45c0-9a6c-78733540137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535744779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3535744779
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.498365426
Short name T80
Test name
Test status
Simulation time 470533736 ps
CPU time 3.57 seconds
Started May 02 02:09:57 PM PDT 24
Finished May 02 02:10:02 PM PDT 24
Peak memory 222400 kb
Host smart-1dd66c6e-cb76-4cd5-acc4-279e0c1623d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498365426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.498365426
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3998847621
Short name T70
Test name
Test status
Simulation time 3179186050 ps
CPU time 4.41 seconds
Started May 02 02:10:11 PM PDT 24
Finished May 02 02:10:17 PM PDT 24
Peak memory 219232 kb
Host smart-e7114374-9a80-41cd-af09-3727417a0a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998847621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3998847621
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3644883263
Short name T271
Test name
Test status
Simulation time 4761583081 ps
CPU time 4.18 seconds
Started May 02 02:10:19 PM PDT 24
Finished May 02 02:10:24 PM PDT 24
Peak memory 222460 kb
Host smart-f22b45ec-5359-427c-b1ad-876263708113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644883263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3644883263
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2673054411
Short name T398
Test name
Test status
Simulation time 9836333954 ps
CPU time 57.46 seconds
Started May 02 02:10:36 PM PDT 24
Finished May 02 02:11:34 PM PDT 24
Peak memory 216400 kb
Host smart-e3919c12-e700-4600-acc8-a0f9d49f7f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673054411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2673054411
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_upload.4023134817
Short name T204
Test name
Test status
Simulation time 1221909276 ps
CPU time 9.71 seconds
Started May 02 02:10:43 PM PDT 24
Finished May 02 02:10:54 PM PDT 24
Peak memory 234896 kb
Host smart-62c8f2dc-06cf-4bca-9c66-389417f2ca4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023134817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4023134817
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.955009073
Short name T227
Test name
Test status
Simulation time 425804182 ps
CPU time 2.29 seconds
Started May 02 02:11:00 PM PDT 24
Finished May 02 02:11:04 PM PDT 24
Peak memory 218536 kb
Host smart-8cbbcccb-5b5d-47f8-a246-0359a3b3dd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955009073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.955009073
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3162589639
Short name T86
Test name
Test status
Simulation time 305909980 ps
CPU time 3.05 seconds
Started May 02 02:11:08 PM PDT 24
Finished May 02 02:11:12 PM PDT 24
Peak memory 218604 kb
Host smart-7130108c-1d19-4aad-821b-82fd2885f363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162589639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3162589639
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.758784861
Short name T180
Test name
Test status
Simulation time 8209857089 ps
CPU time 18.92 seconds
Started May 02 02:11:16 PM PDT 24
Finished May 02 02:11:36 PM PDT 24
Peak memory 234596 kb
Host smart-dab10eef-ac2b-462d-a50a-1d41ae751f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758784861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.758784861
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3850543491
Short name T187
Test name
Test status
Simulation time 324023312 ps
CPU time 3.44 seconds
Started May 02 02:11:33 PM PDT 24
Finished May 02 02:11:37 PM PDT 24
Peak memory 218804 kb
Host smart-546055cd-9efb-4fd3-83a7-29961bf1a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850543491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3850543491
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2954563698
Short name T259
Test name
Test status
Simulation time 1132702222 ps
CPU time 5.05 seconds
Started May 02 02:07:12 PM PDT 24
Finished May 02 02:07:18 PM PDT 24
Peak memory 218508 kb
Host smart-86977074-85dc-4a1f-b66c-d6b9c2b460e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954563698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2954563698
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1544491254
Short name T101
Test name
Test status
Simulation time 2573762802 ps
CPU time 24.59 seconds
Started May 02 02:08:42 PM PDT 24
Finished May 02 02:09:08 PM PDT 24
Peak memory 224360 kb
Host smart-a05a078d-0564-4811-aff0-e4976b44f706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544491254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1544491254
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2628069894
Short name T343
Test name
Test status
Simulation time 121300677 ps
CPU time 3.38 seconds
Started May 02 02:06:32 PM PDT 24
Finished May 02 02:06:36 PM PDT 24
Peak memory 223044 kb
Host smart-d547c631-f155-49cf-b5b3-48ed35f6b77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628069894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2628069894
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4007092318
Short name T307
Test name
Test status
Simulation time 373054169 ps
CPU time 15.32 seconds
Started May 02 02:06:34 PM PDT 24
Finished May 02 02:06:51 PM PDT 24
Peak memory 251708 kb
Host smart-e13f3731-425c-4298-a56c-8d6cad557521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007092318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4007092318
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.39005996
Short name T212
Test name
Test status
Simulation time 15827994853 ps
CPU time 43.8 seconds
Started May 02 02:07:56 PM PDT 24
Finished May 02 02:08:41 PM PDT 24
Peak memory 234412 kb
Host smart-394eb560-8740-40d1-9e05-6ab789bfbf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39005996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.39005996
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2839283216
Short name T231
Test name
Test status
Simulation time 35796957561 ps
CPU time 22.27 seconds
Started May 02 02:08:05 PM PDT 24
Finished May 02 02:08:28 PM PDT 24
Peak memory 227008 kb
Host smart-69b2e98e-a8b8-4120-960b-8b56f26c9c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839283216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2839283216
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4001470792
Short name T357
Test name
Test status
Simulation time 68679167909 ps
CPU time 30.9 seconds
Started May 02 02:08:05 PM PDT 24
Finished May 02 02:08:38 PM PDT 24
Peak memory 234072 kb
Host smart-e4120a95-9469-4a89-beda-e308508fa7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001470792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4001470792
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.118637994
Short name T208
Test name
Test status
Simulation time 12920099936 ps
CPU time 11.94 seconds
Started May 02 02:08:43 PM PDT 24
Finished May 02 02:08:57 PM PDT 24
Peak memory 218980 kb
Host smart-c47def42-976d-48be-bd4a-e00deb3120cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118637994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.118637994
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3931657808
Short name T356
Test name
Test status
Simulation time 347000099 ps
CPU time 2.2 seconds
Started May 02 02:09:12 PM PDT 24
Finished May 02 02:09:16 PM PDT 24
Peak memory 218716 kb
Host smart-5a282274-cfba-40bb-9382-01aed7121edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931657808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3931657808
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_intercept.420922271
Short name T273
Test name
Test status
Simulation time 622106258 ps
CPU time 6.03 seconds
Started May 02 02:09:15 PM PDT 24
Finished May 02 02:09:22 PM PDT 24
Peak memory 224472 kb
Host smart-af1433d6-b1e3-4549-83e8-7ea10a3722a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420922271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.420922271
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2099865584
Short name T74
Test name
Test status
Simulation time 833787876 ps
CPU time 5.26 seconds
Started May 02 02:09:13 PM PDT 24
Finished May 02 02:09:20 PM PDT 24
Peak memory 222984 kb
Host smart-885b0736-771e-49e4-bf99-1fa4873aba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099865584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2099865584
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_upload.292531571
Short name T197
Test name
Test status
Simulation time 5531901449 ps
CPU time 10.98 seconds
Started May 02 02:09:12 PM PDT 24
Finished May 02 02:09:25 PM PDT 24
Peak memory 232740 kb
Host smart-4e81b6ff-b121-4f9c-82b3-7242cc9516cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292531571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.292531571
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1555444294
Short name T351
Test name
Test status
Simulation time 267511286 ps
CPU time 3.8 seconds
Started May 02 02:09:19 PM PDT 24
Finished May 02 02:09:25 PM PDT 24
Peak memory 218736 kb
Host smart-03cdcafa-d0df-4200-a675-151a4757a9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555444294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1555444294
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2849719994
Short name T296
Test name
Test status
Simulation time 856774338 ps
CPU time 5.36 seconds
Started May 02 02:09:19 PM PDT 24
Finished May 02 02:09:26 PM PDT 24
Peak memory 224376 kb
Host smart-a8684ca6-60aa-40c0-8a55-471818f3f298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849719994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2849719994
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_upload.2725432513
Short name T200
Test name
Test status
Simulation time 255761711 ps
CPU time 2.43 seconds
Started May 02 02:09:28 PM PDT 24
Finished May 02 02:09:32 PM PDT 24
Peak memory 222184 kb
Host smart-214cf17e-d5f4-4dc4-9ecd-6e8faa8745e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725432513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2725432513
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3852613869
Short name T310
Test name
Test status
Simulation time 11780930201 ps
CPU time 39.83 seconds
Started May 02 02:09:34 PM PDT 24
Finished May 02 02:10:14 PM PDT 24
Peak memory 237792 kb
Host smart-47cec097-b6f2-4147-a3d3-0be4fe783d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852613869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3852613869
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4227069548
Short name T99
Test name
Test status
Simulation time 31235526202 ps
CPU time 21.02 seconds
Started May 02 02:09:54 PM PDT 24
Finished May 02 02:10:16 PM PDT 24
Peak memory 232768 kb
Host smart-1170bd6d-ca4c-43f0-809c-7bb3891730c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227069548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4227069548
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_upload.3591261704
Short name T176
Test name
Test status
Simulation time 40783299873 ps
CPU time 30.18 seconds
Started May 02 02:09:52 PM PDT 24
Finished May 02 02:10:23 PM PDT 24
Peak memory 218832 kb
Host smart-7a1783bd-c709-44e0-8041-880ada7a8970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591261704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3591261704
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3714988167
Short name T169
Test name
Test status
Simulation time 412910618 ps
CPU time 3.05 seconds
Started May 02 02:10:05 PM PDT 24
Finished May 02 02:10:11 PM PDT 24
Peak memory 222332 kb
Host smart-a8bfed8e-acc6-4bb1-8575-66fa2ebee423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714988167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3714988167
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3277507471
Short name T213
Test name
Test status
Simulation time 1058307573 ps
CPU time 6.55 seconds
Started May 02 02:10:15 PM PDT 24
Finished May 02 02:10:24 PM PDT 24
Peak memory 234292 kb
Host smart-c06782cb-6d8a-4a84-8aec-0bbbe62a829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277507471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3277507471
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4125901075
Short name T359
Test name
Test status
Simulation time 985473987 ps
CPU time 6.39 seconds
Started May 02 02:10:13 PM PDT 24
Finished May 02 02:10:20 PM PDT 24
Peak memory 223844 kb
Host smart-af897a0f-8212-4ca6-bbf5-a285edccd0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125901075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4125901075
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3005340996
Short name T223
Test name
Test status
Simulation time 8142313294 ps
CPU time 13.34 seconds
Started May 02 02:10:20 PM PDT 24
Finished May 02 02:10:34 PM PDT 24
Peak memory 220952 kb
Host smart-102b5de7-f67f-49ee-bb42-4338a59c1cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005340996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3005340996
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2247338238
Short name T331
Test name
Test status
Simulation time 2452554628 ps
CPU time 8.47 seconds
Started May 02 02:10:35 PM PDT 24
Finished May 02 02:10:45 PM PDT 24
Peak memory 218612 kb
Host smart-fc9c18e1-f88e-4f14-9f5f-c792f42bb2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247338238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2247338238
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1344202629
Short name T330
Test name
Test status
Simulation time 237229791 ps
CPU time 5.7 seconds
Started May 02 02:10:24 PM PDT 24
Finished May 02 02:10:31 PM PDT 24
Peak memory 218848 kb
Host smart-83d9f59a-3a55-44de-835a-1dcc2af55686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344202629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1344202629
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3220875376
Short name T220
Test name
Test status
Simulation time 2131413874 ps
CPU time 8.93 seconds
Started May 02 02:10:43 PM PDT 24
Finished May 02 02:10:53 PM PDT 24
Peak memory 219212 kb
Host smart-eaff4779-2b09-49c0-888f-57748ce0af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220875376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3220875376
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.144056012
Short name T214
Test name
Test status
Simulation time 5395051465 ps
CPU time 32.9 seconds
Started May 02 02:10:42 PM PDT 24
Finished May 02 02:11:17 PM PDT 24
Peak memory 236312 kb
Host smart-48b00c0b-8dbc-48a2-84b6-b45ed2ee8ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144056012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.144056012
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.559636857
Short name T363
Test name
Test status
Simulation time 1942657518 ps
CPU time 3.38 seconds
Started May 02 02:10:42 PM PDT 24
Finished May 02 02:10:47 PM PDT 24
Peak memory 216816 kb
Host smart-79eae7a4-3591-47c0-9ede-0cd6b855dda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559636857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.559636857
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4151461843
Short name T201
Test name
Test status
Simulation time 18045332011 ps
CPU time 30.86 seconds
Started May 02 02:10:46 PM PDT 24
Finished May 02 02:11:18 PM PDT 24
Peak memory 232764 kb
Host smart-a78b4bb0-9c50-4ba4-ae6e-0008680fd3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151461843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4151461843
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.253799253
Short name T72
Test name
Test status
Simulation time 671906343 ps
CPU time 6.7 seconds
Started May 02 02:07:06 PM PDT 24
Finished May 02 02:07:14 PM PDT 24
Peak memory 218424 kb
Host smart-b6279640-cdac-4149-a841-951b9b5c4974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253799253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
253799253
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3318322453
Short name T300
Test name
Test status
Simulation time 740793426 ps
CPU time 19.69 seconds
Started May 02 02:11:10 PM PDT 24
Finished May 02 02:11:31 PM PDT 24
Peak memory 240520 kb
Host smart-06f57346-1785-4d4e-a5d3-d92f7d1e63dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318322453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3318322453
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1287380776
Short name T301
Test name
Test status
Simulation time 163774219 ps
CPU time 2.87 seconds
Started May 02 02:11:17 PM PDT 24
Finished May 02 02:11:22 PM PDT 24
Peak memory 218772 kb
Host smart-4959be57-3491-42a3-9e3d-d54dd9f47306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287380776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1287380776
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2337722312
Short name T25
Test name
Test status
Simulation time 11640581353 ps
CPU time 30.47 seconds
Started May 02 02:11:43 PM PDT 24
Finished May 02 02:12:15 PM PDT 24
Peak memory 219088 kb
Host smart-6d011e8c-9b96-43a6-a8f3-e6bf396743a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337722312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2337722312
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3589471735
Short name T313
Test name
Test status
Simulation time 25111073397 ps
CPU time 39.2 seconds
Started May 02 02:11:41 PM PDT 24
Finished May 02 02:12:21 PM PDT 24
Peak memory 238728 kb
Host smart-eb632fda-9d0b-49eb-8290-7bdaa1f814a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589471735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3589471735
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.82361902
Short name T195
Test name
Test status
Simulation time 5303335761 ps
CPU time 16.9 seconds
Started May 02 02:11:43 PM PDT 24
Finished May 02 02:12:02 PM PDT 24
Peak memory 234236 kb
Host smart-94073398-7125-445c-961a-67b3b67f711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82361902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.82361902
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2648575076
Short name T340
Test name
Test status
Simulation time 8518589053 ps
CPU time 24.35 seconds
Started May 02 02:11:40 PM PDT 24
Finished May 02 02:12:06 PM PDT 24
Peak memory 223488 kb
Host smart-def910a2-fa5b-48b6-9478-f01cd34019d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648575076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2648575076
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3661447279
Short name T263
Test name
Test status
Simulation time 7741529593 ps
CPU time 24.29 seconds
Started May 02 02:11:50 PM PDT 24
Finished May 02 02:12:16 PM PDT 24
Peak memory 235660 kb
Host smart-f8f27f99-f727-4024-bbe9-939d19d452ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661447279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3661447279
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_upload.3426365655
Short name T205
Test name
Test status
Simulation time 1872055757 ps
CPU time 7.76 seconds
Started May 02 02:11:49 PM PDT 24
Finished May 02 02:11:58 PM PDT 24
Peak memory 222908 kb
Host smart-22222e6d-a2d6-4b1b-a00d-56bb3b9791bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426365655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3426365655
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_upload.2701771451
Short name T254
Test name
Test status
Simulation time 427567965 ps
CPU time 5.55 seconds
Started May 02 02:11:48 PM PDT 24
Finished May 02 02:11:55 PM PDT 24
Peak memory 216356 kb
Host smart-f8e9cadc-7306-4a89-9778-aabf4d2c6c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701771451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2701771451
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1544428914
Short name T189
Test name
Test status
Simulation time 849216452 ps
CPU time 3.58 seconds
Started May 02 02:07:28 PM PDT 24
Finished May 02 02:07:33 PM PDT 24
Peak memory 219960 kb
Host smart-7e303216-c30a-4501-8c2a-f33d3c39d7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544428914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1544428914
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.126054627
Short name T272
Test name
Test status
Simulation time 678582019 ps
CPU time 3.34 seconds
Started May 02 02:07:37 PM PDT 24
Finished May 02 02:07:42 PM PDT 24
Peak memory 222704 kb
Host smart-6fc45510-c407-42e1-a661-76e6b0a91c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126054627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
126054627
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3426399877
Short name T448
Test name
Test status
Simulation time 54603731 ps
CPU time 0.8 seconds
Started May 02 02:07:36 PM PDT 24
Finished May 02 02:07:38 PM PDT 24
Peak memory 206700 kb
Host smart-19b89b5e-c743-4da8-8fd6-4c299daebde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426399877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3426399877
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3372378967
Short name T105
Test name
Test status
Simulation time 65623869 ps
CPU time 1.14 seconds
Started May 02 02:18:49 PM PDT 24
Finished May 02 02:18:52 PM PDT 24
Peak memory 216036 kb
Host smart-c6f5f053-301a-4e66-9d47-47bfe63edf1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372378967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3372378967
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3685028660
Short name T794
Test name
Test status
Simulation time 131919117 ps
CPU time 4.46 seconds
Started May 02 02:19:07 PM PDT 24
Finished May 02 02:19:14 PM PDT 24
Peak memory 215300 kb
Host smart-b189991c-934b-438d-ba89-c65e12c21203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685028660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3685028660
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2071458491
Short name T131
Test name
Test status
Simulation time 1171284021 ps
CPU time 20.29 seconds
Started May 02 02:19:01 PM PDT 24
Finished May 02 02:19:25 PM PDT 24
Peak memory 215124 kb
Host smart-2cdd2828-dca6-49ba-bee8-1cb3f0d4a585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071458491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2071458491
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1441041695
Short name T768
Test name
Test status
Simulation time 634946506 ps
CPU time 14.83 seconds
Started May 02 02:18:48 PM PDT 24
Finished May 02 02:19:05 PM PDT 24
Peak memory 206836 kb
Host smart-ed717600-e343-4021-8a46-000d41166f25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441041695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1441041695
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.462768611
Short name T765
Test name
Test status
Simulation time 2435953661 ps
CPU time 13 seconds
Started May 02 02:18:51 PM PDT 24
Finished May 02 02:19:06 PM PDT 24
Peak memory 206932 kb
Host smart-783071d5-913d-4555-a333-d71c94c9e902
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462768611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.462768611
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2523439966
Short name T102
Test name
Test status
Simulation time 44721112 ps
CPU time 0.98 seconds
Started May 02 02:18:49 PM PDT 24
Finished May 02 02:18:52 PM PDT 24
Peak memory 206664 kb
Host smart-bf29a7db-d6a7-4835-925f-abad338b8fcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523439966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2523439966
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3550532374
Short name T35
Test name
Test status
Simulation time 51779670 ps
CPU time 3.76 seconds
Started May 02 02:18:49 PM PDT 24
Finished May 02 02:18:55 PM PDT 24
Peak memory 217764 kb
Host smart-8784f024-c08f-45bd-a02d-9f937d0e376c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550532374 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3550532374
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3644589357
Short name T145
Test name
Test status
Simulation time 28859631 ps
CPU time 1.9 seconds
Started May 02 02:18:48 PM PDT 24
Finished May 02 02:18:52 PM PDT 24
Peak memory 206840 kb
Host smart-f7148b6c-e450-4454-bdaf-4085b42df7fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644589357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
644589357
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2687856558
Short name T769
Test name
Test status
Simulation time 14079195 ps
CPU time 0.74 seconds
Started May 02 02:18:39 PM PDT 24
Finished May 02 02:18:42 PM PDT 24
Peak memory 203468 kb
Host smart-84875d98-da76-4675-92c2-e8cc3c91f1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687856558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
687856558
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3002765319
Short name T137
Test name
Test status
Simulation time 77538069 ps
CPU time 1.73 seconds
Started May 02 02:18:52 PM PDT 24
Finished May 02 02:18:55 PM PDT 24
Peak memory 215136 kb
Host smart-8cd06a65-66b6-4ef0-b44e-274ec850778b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002765319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3002765319
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3410289057
Short name T818
Test name
Test status
Simulation time 104537212 ps
CPU time 0.66 seconds
Started May 02 02:18:40 PM PDT 24
Finished May 02 02:18:42 PM PDT 24
Peak memory 203288 kb
Host smart-e900844c-3764-4e27-a4d2-8ab00d95d0ef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410289057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3410289057
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2832948389
Short name T809
Test name
Test status
Simulation time 300284550 ps
CPU time 1.98 seconds
Started May 02 02:18:49 PM PDT 24
Finished May 02 02:18:54 PM PDT 24
Peak memory 215096 kb
Host smart-aa0e5404-4239-440c-862e-f571e3a56a80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832948389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2832948389
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2386270966
Short name T812
Test name
Test status
Simulation time 242200755 ps
CPU time 3.23 seconds
Started May 02 02:18:42 PM PDT 24
Finished May 02 02:18:47 PM PDT 24
Peak memory 215160 kb
Host smart-755af306-067e-4dec-959f-dcb9c5bee7ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386270966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
386270966
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3506268837
Short name T758
Test name
Test status
Simulation time 862653723 ps
CPU time 14.16 seconds
Started May 02 02:18:53 PM PDT 24
Finished May 02 02:19:09 PM PDT 24
Peak memory 206900 kb
Host smart-99b33542-2173-4124-a6a8-9549b22cde16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506268837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3506268837
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3361186444
Short name T159
Test name
Test status
Simulation time 5818291193 ps
CPU time 26.52 seconds
Started May 02 02:18:47 PM PDT 24
Finished May 02 02:19:16 PM PDT 24
Peak memory 206892 kb
Host smart-de0b369b-0091-4661-9a59-f8dceaa6dfc4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361186444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3361186444
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.187464140
Short name T746
Test name
Test status
Simulation time 102498887 ps
CPU time 1.88 seconds
Started May 02 02:18:49 PM PDT 24
Finished May 02 02:18:53 PM PDT 24
Peak memory 215140 kb
Host smart-cb360a1c-a4e9-4a55-80d0-1038a445c6c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187464140 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.187464140
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.390785859
Short name T789
Test name
Test status
Simulation time 395619183 ps
CPU time 1.85 seconds
Started May 02 02:18:50 PM PDT 24
Finished May 02 02:18:54 PM PDT 24
Peak memory 207052 kb
Host smart-ebda9ab6-b8cf-4db6-aa8c-3cc9bf536cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390785859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.390785859
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.224252401
Short name T799
Test name
Test status
Simulation time 12889826 ps
CPU time 0.74 seconds
Started May 02 02:18:49 PM PDT 24
Finished May 02 02:18:52 PM PDT 24
Peak memory 203800 kb
Host smart-17a70799-a4d9-41d1-85d8-2f4e69064cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224252401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.224252401
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2373555298
Short name T140
Test name
Test status
Simulation time 124224463 ps
CPU time 1.23 seconds
Started May 02 02:18:48 PM PDT 24
Finished May 02 02:18:51 PM PDT 24
Peak memory 215176 kb
Host smart-77edb88c-7b9f-4272-b0d9-8c10be796e19
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373555298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2373555298
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4140516122
Short name T732
Test name
Test status
Simulation time 15010004 ps
CPU time 0.65 seconds
Started May 02 02:18:49 PM PDT 24
Finished May 02 02:18:52 PM PDT 24
Peak memory 203408 kb
Host smart-b8ceffae-cbae-4a36-9e38-acf823ff3101
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140516122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4140516122
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2146229409
Short name T775
Test name
Test status
Simulation time 64628222 ps
CPU time 3.88 seconds
Started May 02 02:18:50 PM PDT 24
Finished May 02 02:18:56 PM PDT 24
Peak memory 215100 kb
Host smart-80bb4b67-4fba-4d3c-af9a-68addc1604d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146229409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2146229409
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2524620393
Short name T162
Test name
Test status
Simulation time 375602028 ps
CPU time 8.21 seconds
Started May 02 02:18:49 PM PDT 24
Finished May 02 02:19:00 PM PDT 24
Peak memory 215088 kb
Host smart-725ccee7-3f78-42fa-9bcd-f12359c0109f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524620393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2524620393
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1061537373
Short name T37
Test name
Test status
Simulation time 108932006 ps
CPU time 3.55 seconds
Started May 02 02:19:04 PM PDT 24
Finished May 02 02:19:11 PM PDT 24
Peak memory 217624 kb
Host smart-ff368811-2c30-4023-a883-a9b49b0f476d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061537373 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1061537373
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3247665669
Short name T149
Test name
Test status
Simulation time 67896559 ps
CPU time 2.15 seconds
Started May 02 02:19:03 PM PDT 24
Finished May 02 02:19:08 PM PDT 24
Peak memory 206924 kb
Host smart-a0ac0b23-a24b-4858-abd9-66606666a3f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247665669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3247665669
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1317637496
Short name T820
Test name
Test status
Simulation time 23477202 ps
CPU time 0.72 seconds
Started May 02 02:19:06 PM PDT 24
Finished May 02 02:19:09 PM PDT 24
Peak memory 203504 kb
Host smart-ee1f7605-d815-49a3-9e3a-e40d5476eb80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317637496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1317637496
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1024728689
Short name T753
Test name
Test status
Simulation time 545080689 ps
CPU time 3.78 seconds
Started May 02 02:19:07 PM PDT 24
Finished May 02 02:19:14 PM PDT 24
Peak memory 215056 kb
Host smart-ae56dc0c-288d-4b65-bde7-60dd48e6c371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024728689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1024728689
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.227517462
Short name T388
Test name
Test status
Simulation time 1451217868 ps
CPU time 16.4 seconds
Started May 02 02:19:06 PM PDT 24
Finished May 02 02:19:25 PM PDT 24
Peak memory 215108 kb
Host smart-9657a7de-da1a-45d0-8357-03e267518ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227517462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.227517462
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3307778698
Short name T829
Test name
Test status
Simulation time 24772799 ps
CPU time 1.64 seconds
Started May 02 02:19:08 PM PDT 24
Finished May 02 02:19:12 PM PDT 24
Peak memory 216252 kb
Host smart-1b98045d-a24d-410a-be44-4b6af94581df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307778698 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3307778698
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2662645628
Short name T825
Test name
Test status
Simulation time 110522142 ps
CPU time 2.8 seconds
Started May 02 02:19:06 PM PDT 24
Finished May 02 02:19:11 PM PDT 24
Peak memory 215080 kb
Host smart-90766447-5d8f-4969-bacd-d8c65d868c1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662645628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2662645628
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.344105645
Short name T367
Test name
Test status
Simulation time 38802180 ps
CPU time 0.76 seconds
Started May 02 02:19:07 PM PDT 24
Finished May 02 02:19:11 PM PDT 24
Peak memory 203428 kb
Host smart-caa03f94-4262-4a0f-a5af-2ea5960d37c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344105645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.344105645
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1689396973
Short name T40
Test name
Test status
Simulation time 56101633 ps
CPU time 1.76 seconds
Started May 02 02:19:07 PM PDT 24
Finished May 02 02:19:11 PM PDT 24
Peak memory 206896 kb
Host smart-5e70c3c2-0984-4491-90fd-7b9fcc4fbced
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689396973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1689396973
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1446996226
Short name T834
Test name
Test status
Simulation time 1594007874 ps
CPU time 22.11 seconds
Started May 02 02:19:04 PM PDT 24
Finished May 02 02:19:29 PM PDT 24
Peak memory 215048 kb
Host smart-5e4d0fbf-e074-451e-8aa2-5420a474ddc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446996226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1446996226
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3205614901
Short name T163
Test name
Test status
Simulation time 448268895 ps
CPU time 2.83 seconds
Started May 02 02:19:07 PM PDT 24
Finished May 02 02:19:12 PM PDT 24
Peak memory 217460 kb
Host smart-26eb5d5a-aee0-4291-bc96-6241107ce56f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205614901 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3205614901
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.451535151
Short name T39
Test name
Test status
Simulation time 48288621 ps
CPU time 1.91 seconds
Started May 02 02:19:08 PM PDT 24
Finished May 02 02:19:13 PM PDT 24
Peak memory 214812 kb
Host smart-38aae7a8-a926-4811-bd76-eedd0b6e1587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451535151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.451535151
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1189738069
Short name T822
Test name
Test status
Simulation time 29839135 ps
CPU time 0.74 seconds
Started May 02 02:19:06 PM PDT 24
Finished May 02 02:19:10 PM PDT 24
Peak memory 203480 kb
Host smart-03d47fe1-5a82-416b-926f-e93b5fe6c27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189738069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1189738069
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.430188085
Short name T811
Test name
Test status
Simulation time 900557505 ps
CPU time 3.61 seconds
Started May 02 02:19:08 PM PDT 24
Finished May 02 02:19:14 PM PDT 24
Peak memory 215100 kb
Host smart-fdc4683e-afc2-433f-9c40-a4140d2320d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430188085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.430188085
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2314140412
Short name T828
Test name
Test status
Simulation time 141650385 ps
CPU time 3.37 seconds
Started May 02 02:19:08 PM PDT 24
Finished May 02 02:19:14 PM PDT 24
Peak memory 215124 kb
Host smart-52afee34-4660-43cb-9ebc-28e02300ae45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314140412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2314140412
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2311091723
Short name T387
Test name
Test status
Simulation time 425702980 ps
CPU time 6.37 seconds
Started May 02 02:19:06 PM PDT 24
Finished May 02 02:19:15 PM PDT 24
Peak memory 216756 kb
Host smart-3ee9cdf1-ac10-4836-9065-0d3a50a7339e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311091723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2311091723
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4222924647
Short name T779
Test name
Test status
Simulation time 534230510 ps
CPU time 3.73 seconds
Started May 02 02:19:13 PM PDT 24
Finished May 02 02:19:18 PM PDT 24
Peak memory 216920 kb
Host smart-c7d09468-0d4b-4eb2-b31e-765e0516aef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222924647 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4222924647
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.389185121
Short name T786
Test name
Test status
Simulation time 73842192 ps
CPU time 1.87 seconds
Started May 02 02:19:07 PM PDT 24
Finished May 02 02:19:11 PM PDT 24
Peak memory 215044 kb
Host smart-116f045c-e251-4a01-aa41-06b9aef3ea6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389185121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.389185121
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2425781167
Short name T739
Test name
Test status
Simulation time 38290629 ps
CPU time 0.68 seconds
Started May 02 02:19:08 PM PDT 24
Finished May 02 02:19:11 PM PDT 24
Peak memory 203516 kb
Host smart-39ec05c5-b7f3-42ad-8d2d-30b36c0a81c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425781167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2425781167
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1180870429
Short name T749
Test name
Test status
Simulation time 107530739 ps
CPU time 2.79 seconds
Started May 02 02:19:05 PM PDT 24
Finished May 02 02:19:11 PM PDT 24
Peak memory 215128 kb
Host smart-acef6c1d-5661-494f-901c-ad75b8c51ea3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180870429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1180870429
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1222660107
Short name T798
Test name
Test status
Simulation time 283859479 ps
CPU time 1.63 seconds
Started May 02 02:19:08 PM PDT 24
Finished May 02 02:19:12 PM PDT 24
Peak memory 216280 kb
Host smart-16241962-fa62-4625-a9c0-7d57b4c3f1bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222660107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1222660107
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3458557489
Short name T386
Test name
Test status
Simulation time 852500995 ps
CPU time 12.36 seconds
Started May 02 02:19:08 PM PDT 24
Finished May 02 02:19:23 PM PDT 24
Peak memory 215728 kb
Host smart-471ee81c-8a09-43f9-ad12-5160c7d1b2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458557489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3458557489
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2401034539
Short name T835
Test name
Test status
Simulation time 209129846 ps
CPU time 3.74 seconds
Started May 02 02:19:13 PM PDT 24
Finished May 02 02:19:18 PM PDT 24
Peak memory 217080 kb
Host smart-40bc9bb0-26d9-45dc-b2a3-e5f1db22eaec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401034539 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2401034539
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1735893031
Short name T148
Test name
Test status
Simulation time 40602364 ps
CPU time 1.35 seconds
Started May 02 02:19:15 PM PDT 24
Finished May 02 02:19:18 PM PDT 24
Peak memory 215004 kb
Host smart-2067d89f-62d8-4d9c-a86c-00cdd3c620a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735893031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1735893031
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2996757275
Short name T756
Test name
Test status
Simulation time 43146297 ps
CPU time 0.72 seconds
Started May 02 02:19:15 PM PDT 24
Finished May 02 02:19:17 PM PDT 24
Peak memory 203492 kb
Host smart-96a48043-6125-4f13-8996-768c181fd00a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996757275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2996757275
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2278670677
Short name T736
Test name
Test status
Simulation time 56312141 ps
CPU time 1.83 seconds
Started May 02 02:19:16 PM PDT 24
Finished May 02 02:19:20 PM PDT 24
Peak memory 215056 kb
Host smart-82c19718-8d4a-4ddc-9d3e-d45e9bcc7ac8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278670677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2278670677
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.847327841
Short name T800
Test name
Test status
Simulation time 189053794 ps
CPU time 3.08 seconds
Started May 02 02:19:14 PM PDT 24
Finished May 02 02:19:19 PM PDT 24
Peak memory 215200 kb
Host smart-aa786287-4a50-4f4d-a2b7-f71f9ae28476
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847327841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.847327841
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1072587934
Short name T384
Test name
Test status
Simulation time 2144502161 ps
CPU time 12.89 seconds
Started May 02 02:19:17 PM PDT 24
Finished May 02 02:19:31 PM PDT 24
Peak memory 215228 kb
Host smart-088e9790-2637-45c5-90df-c873d2919665
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072587934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1072587934
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.604354059
Short name T750
Test name
Test status
Simulation time 28846774 ps
CPU time 1.69 seconds
Started May 02 02:19:17 PM PDT 24
Finished May 02 02:19:20 PM PDT 24
Peak memory 216240 kb
Host smart-fb0c27be-5444-4eec-8376-cde1919d5306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604354059 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.604354059
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.658239945
Short name T147
Test name
Test status
Simulation time 38069010 ps
CPU time 2.29 seconds
Started May 02 02:19:15 PM PDT 24
Finished May 02 02:19:19 PM PDT 24
Peak memory 206900 kb
Host smart-a2c778ec-673f-425c-886b-5cda9d8cf85e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658239945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.658239945
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2890534391
Short name T764
Test name
Test status
Simulation time 37386623 ps
CPU time 0.71 seconds
Started May 02 02:19:12 PM PDT 24
Finished May 02 02:19:14 PM PDT 24
Peak memory 203544 kb
Host smart-ac29532f-46ae-4d03-afd9-eb47e1b13d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890534391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2890534391
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2002439831
Short name T832
Test name
Test status
Simulation time 132483523 ps
CPU time 1.82 seconds
Started May 02 02:19:12 PM PDT 24
Finished May 02 02:19:16 PM PDT 24
Peak memory 206852 kb
Host smart-6350aa82-a7a0-48d9-a87a-ee3f770cf305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002439831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2002439831
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2854891273
Short name T133
Test name
Test status
Simulation time 155936680 ps
CPU time 2.5 seconds
Started May 02 02:19:15 PM PDT 24
Finished May 02 02:19:19 PM PDT 24
Peak memory 215184 kb
Host smart-d9742a4f-5fb6-47da-8f85-5a9bb253633f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854891273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2854891273
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1764627122
Short name T836
Test name
Test status
Simulation time 1137226782 ps
CPU time 24.2 seconds
Started May 02 02:19:11 PM PDT 24
Finished May 02 02:19:37 PM PDT 24
Peak memory 215124 kb
Host smart-941b8bd8-d2e0-4d05-8ddd-330180573855
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764627122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1764627122
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2245301994
Short name T134
Test name
Test status
Simulation time 155233232 ps
CPU time 3.89 seconds
Started May 02 02:19:15 PM PDT 24
Finished May 02 02:19:21 PM PDT 24
Peak memory 217536 kb
Host smart-8d0c55fd-9018-4be5-b40c-68082a56dd81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245301994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2245301994
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2899310476
Short name T796
Test name
Test status
Simulation time 30528002 ps
CPU time 1.87 seconds
Started May 02 02:19:13 PM PDT 24
Finished May 02 02:19:16 PM PDT 24
Peak memory 215112 kb
Host smart-cdf05da4-7159-49fa-8664-fd3c43348c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899310476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2899310476
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1598137329
Short name T741
Test name
Test status
Simulation time 16398388 ps
CPU time 0.73 seconds
Started May 02 02:19:13 PM PDT 24
Finished May 02 02:19:15 PM PDT 24
Peak memory 203504 kb
Host smart-3ca69998-5efd-4253-87ad-9db58d700f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598137329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1598137329
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4276386661
Short name T151
Test name
Test status
Simulation time 48785592 ps
CPU time 2.74 seconds
Started May 02 02:19:17 PM PDT 24
Finished May 02 02:19:21 PM PDT 24
Peak memory 215076 kb
Host smart-e2d81ef5-29da-433c-ba22-93c2bbd36a1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276386661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4276386661
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.711382593
Short name T129
Test name
Test status
Simulation time 631094347 ps
CPU time 3.71 seconds
Started May 02 02:19:14 PM PDT 24
Finished May 02 02:19:19 PM PDT 24
Peak memory 215220 kb
Host smart-896a7981-7cb3-4b42-b0cf-dd588a8f694c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711382593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.711382593
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.708105663
Short name T783
Test name
Test status
Simulation time 136005130 ps
CPU time 2.43 seconds
Started May 02 02:19:23 PM PDT 24
Finished May 02 02:19:28 PM PDT 24
Peak memory 217556 kb
Host smart-169fa375-a6df-423d-8300-864b7ed7a709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708105663 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.708105663
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2786823803
Short name T153
Test name
Test status
Simulation time 347903988 ps
CPU time 2.22 seconds
Started May 02 02:19:14 PM PDT 24
Finished May 02 02:19:18 PM PDT 24
Peak memory 206860 kb
Host smart-9fca792e-9dd9-48ad-b9f6-e5b17aa0c50a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786823803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2786823803
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.278134766
Short name T792
Test name
Test status
Simulation time 12107502 ps
CPU time 0.73 seconds
Started May 02 02:19:13 PM PDT 24
Finished May 02 02:19:16 PM PDT 24
Peak memory 203516 kb
Host smart-0dcbe406-70de-4f91-b0e7-10e950566327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278134766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.278134766
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1678308518
Short name T797
Test name
Test status
Simulation time 60205889 ps
CPU time 1.9 seconds
Started May 02 02:19:25 PM PDT 24
Finished May 02 02:19:30 PM PDT 24
Peak memory 206896 kb
Host smart-0e0b8a94-b887-4be1-b3ae-3d534d91212c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678308518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1678308518
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.868173691
Short name T766
Test name
Test status
Simulation time 48099018 ps
CPU time 3.02 seconds
Started May 02 02:19:13 PM PDT 24
Finished May 02 02:19:17 PM PDT 24
Peak memory 216204 kb
Host smart-20e6ac3f-788f-4e36-b327-edb0dff4cefe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868173691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.868173691
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1134003880
Short name T382
Test name
Test status
Simulation time 1098615330 ps
CPU time 16.07 seconds
Started May 02 02:19:12 PM PDT 24
Finished May 02 02:19:30 PM PDT 24
Peak memory 215200 kb
Host smart-2bdb7310-e75f-4f6e-9971-4f23580d0e57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134003880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1134003880
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1553692730
Short name T130
Test name
Test status
Simulation time 150006067 ps
CPU time 1.67 seconds
Started May 02 02:19:21 PM PDT 24
Finished May 02 02:19:24 PM PDT 24
Peak memory 215100 kb
Host smart-26958dae-65f2-4af4-8ef4-bf5101fe6a61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553692730 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1553692730
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2117423797
Short name T795
Test name
Test status
Simulation time 32088200 ps
CPU time 1.84 seconds
Started May 02 02:19:21 PM PDT 24
Finished May 02 02:19:24 PM PDT 24
Peak memory 215072 kb
Host smart-7da8c672-2e38-44d2-93a5-a8137ff56a5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117423797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2117423797
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1954365138
Short name T759
Test name
Test status
Simulation time 16180524 ps
CPU time 0.74 seconds
Started May 02 02:19:22 PM PDT 24
Finished May 02 02:19:25 PM PDT 24
Peak memory 203508 kb
Host smart-ff102cda-4281-4722-a47e-941719a007e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954365138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1954365138
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.121766078
Short name T773
Test name
Test status
Simulation time 198207486 ps
CPU time 3.95 seconds
Started May 02 02:19:24 PM PDT 24
Finished May 02 02:19:31 PM PDT 24
Peak memory 215080 kb
Host smart-e8c252fe-75e1-478d-8f38-297add3764f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121766078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.121766078
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4049105716
Short name T826
Test name
Test status
Simulation time 626168908 ps
CPU time 3.69 seconds
Started May 02 02:19:22 PM PDT 24
Finished May 02 02:19:28 PM PDT 24
Peak memory 215336 kb
Host smart-7cc4e9e2-d4a5-474d-84fb-b4fee9176533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049105716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4049105716
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.936299023
Short name T123
Test name
Test status
Simulation time 322494045 ps
CPU time 7.41 seconds
Started May 02 02:19:23 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 215648 kb
Host smart-79445d1e-fdfc-4be2-9fa8-f9f7b526db0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936299023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.936299023
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1139001875
Short name T136
Test name
Test status
Simulation time 355686562 ps
CPU time 2.56 seconds
Started May 02 02:19:21 PM PDT 24
Finished May 02 02:19:24 PM PDT 24
Peak memory 216680 kb
Host smart-7813ff25-6257-4305-88de-26d639dc86ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139001875 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1139001875
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2899277775
Short name T777
Test name
Test status
Simulation time 29600855 ps
CPU time 1.97 seconds
Started May 02 02:19:26 PM PDT 24
Finished May 02 02:19:32 PM PDT 24
Peak memory 215068 kb
Host smart-36776b73-f71e-4a67-bb50-5a2cb08cb27e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899277775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2899277775
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2754807196
Short name T168
Test name
Test status
Simulation time 17056970 ps
CPU time 0.75 seconds
Started May 02 02:19:28 PM PDT 24
Finished May 02 02:19:33 PM PDT 24
Peak memory 203736 kb
Host smart-e1feb7df-1a59-4f63-ac78-623323c2345b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754807196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2754807196
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1411635894
Short name T837
Test name
Test status
Simulation time 95301393 ps
CPU time 2.63 seconds
Started May 02 02:19:21 PM PDT 24
Finished May 02 02:19:25 PM PDT 24
Peak memory 215096 kb
Host smart-cd2d4a23-f9f7-4cdd-919d-0eef01f81f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411635894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1411635894
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2369766708
Short name T128
Test name
Test status
Simulation time 183125071 ps
CPU time 3.94 seconds
Started May 02 02:19:18 PM PDT 24
Finished May 02 02:19:23 PM PDT 24
Peak memory 215168 kb
Host smart-cb61ebe6-3ac9-4cf0-a332-3860c45eb456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369766708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2369766708
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1419514905
Short name T389
Test name
Test status
Simulation time 1581660909 ps
CPU time 7.31 seconds
Started May 02 02:19:25 PM PDT 24
Finished May 02 02:19:36 PM PDT 24
Peak memory 215220 kb
Host smart-2481a91d-4d5b-450b-a9b9-859372bfd88f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419514905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1419514905
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.414484806
Short name T139
Test name
Test status
Simulation time 412637250 ps
CPU time 14.95 seconds
Started May 02 02:18:49 PM PDT 24
Finished May 02 02:19:07 PM PDT 24
Peak memory 215076 kb
Host smart-984d5438-acf3-444f-a5a7-f49281ba690a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414484806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.414484806
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1247080610
Short name T752
Test name
Test status
Simulation time 6058750357 ps
CPU time 13.8 seconds
Started May 02 02:18:44 PM PDT 24
Finished May 02 02:19:00 PM PDT 24
Peak memory 215176 kb
Host smart-4dd4ce00-9d31-425e-b0be-f617b983d05f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247080610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1247080610
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3063865358
Short name T160
Test name
Test status
Simulation time 41898985 ps
CPU time 0.93 seconds
Started May 02 02:18:50 PM PDT 24
Finished May 02 02:18:53 PM PDT 24
Peak memory 206704 kb
Host smart-abd3b6a4-ee3a-430d-8085-b9f882074bc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063865358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3063865358
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1220874197
Short name T801
Test name
Test status
Simulation time 162013939 ps
CPU time 3.92 seconds
Started May 02 02:18:48 PM PDT 24
Finished May 02 02:18:54 PM PDT 24
Peak memory 217940 kb
Host smart-d5ac15a2-7adf-43cb-a083-3da35279f575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220874197 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1220874197
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2294749184
Short name T780
Test name
Test status
Simulation time 322240770 ps
CPU time 2.45 seconds
Started May 02 02:18:48 PM PDT 24
Finished May 02 02:18:53 PM PDT 24
Peak memory 215080 kb
Host smart-32d57bca-4d0c-45ed-ac3d-83505baf24d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294749184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
294749184
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2843484964
Short name T838
Test name
Test status
Simulation time 16412609 ps
CPU time 0.69 seconds
Started May 02 02:18:51 PM PDT 24
Finished May 02 02:18:53 PM PDT 24
Peak memory 203840 kb
Host smart-b448651b-aeb8-420b-9e68-7cafecf20944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843484964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
843484964
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3617529738
Short name T142
Test name
Test status
Simulation time 203029998 ps
CPU time 1.67 seconds
Started May 02 02:18:50 PM PDT 24
Finished May 02 02:18:54 PM PDT 24
Peak memory 215072 kb
Host smart-d4ea2b60-e2e0-4e60-affa-1763a7c9f86d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617529738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3617529738
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3213566697
Short name T782
Test name
Test status
Simulation time 16750425 ps
CPU time 0.64 seconds
Started May 02 02:18:50 PM PDT 24
Finished May 02 02:18:52 PM PDT 24
Peak memory 203736 kb
Host smart-2de55a3d-959b-4c57-b4f6-d9eabd276558
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213566697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3213566697
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3330828687
Short name T748
Test name
Test status
Simulation time 61871818 ps
CPU time 3.65 seconds
Started May 02 02:18:53 PM PDT 24
Finished May 02 02:18:58 PM PDT 24
Peak memory 215124 kb
Host smart-72ade448-fb03-4f26-9019-ecf1b0aea98b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330828687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3330828687
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1361989496
Short name T127
Test name
Test status
Simulation time 212065856 ps
CPU time 2.67 seconds
Started May 02 02:18:51 PM PDT 24
Finished May 02 02:18:55 PM PDT 24
Peak memory 215340 kb
Host smart-18f1495c-394c-41aa-b51a-ab2dca72644b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361989496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
361989496
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3891330865
Short name T385
Test name
Test status
Simulation time 304730073 ps
CPU time 18.84 seconds
Started May 02 02:18:50 PM PDT 24
Finished May 02 02:19:11 PM PDT 24
Peak memory 215064 kb
Host smart-1603c0c3-25af-4bc5-9702-9fa19a8d2dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891330865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3891330865
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.351008338
Short name T738
Test name
Test status
Simulation time 49359139 ps
CPU time 0.73 seconds
Started May 02 02:19:23 PM PDT 24
Finished May 02 02:19:27 PM PDT 24
Peak memory 203792 kb
Host smart-21306938-faa3-4beb-89b8-011e04375e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351008338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.351008338
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1089598420
Short name T831
Test name
Test status
Simulation time 25083196 ps
CPU time 0.77 seconds
Started May 02 02:19:24 PM PDT 24
Finished May 02 02:19:28 PM PDT 24
Peak memory 203812 kb
Host smart-e6734e6b-5ddd-4cb9-b300-4f10c54174e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089598420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1089598420
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1890926522
Short name T740
Test name
Test status
Simulation time 17532611 ps
CPU time 0.73 seconds
Started May 02 02:19:22 PM PDT 24
Finished May 02 02:19:24 PM PDT 24
Peak memory 203464 kb
Host smart-a7aad195-2189-4bbc-9ecd-9b25cd226131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890926522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1890926522
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2998040953
Short name T745
Test name
Test status
Simulation time 32839151 ps
CPU time 0.75 seconds
Started May 02 02:19:28 PM PDT 24
Finished May 02 02:19:33 PM PDT 24
Peak memory 203448 kb
Host smart-add6fa5a-30a1-4b6d-ad33-ad502ea2f764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998040953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2998040953
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1482092837
Short name T771
Test name
Test status
Simulation time 15658341 ps
CPU time 0.72 seconds
Started May 02 02:19:27 PM PDT 24
Finished May 02 02:19:32 PM PDT 24
Peak memory 203744 kb
Host smart-6d12dc59-849e-4823-9d35-d5f71f78c4ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482092837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1482092837
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1663945910
Short name T804
Test name
Test status
Simulation time 51381069 ps
CPU time 0.71 seconds
Started May 02 02:19:24 PM PDT 24
Finished May 02 02:19:28 PM PDT 24
Peak memory 203796 kb
Host smart-f429f16d-e948-48c7-86fd-62e4486f9aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663945910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1663945910
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1676008240
Short name T816
Test name
Test status
Simulation time 39673270 ps
CPU time 0.71 seconds
Started May 02 02:19:24 PM PDT 24
Finished May 02 02:19:28 PM PDT 24
Peak memory 203520 kb
Host smart-b3c83684-777d-4241-b3bb-ad60e218d81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676008240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1676008240
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4059775560
Short name T167
Test name
Test status
Simulation time 14438443 ps
CPU time 0.71 seconds
Started May 02 02:19:23 PM PDT 24
Finished May 02 02:19:26 PM PDT 24
Peak memory 203800 kb
Host smart-45f3156d-7de6-4be3-b9ad-82921bd0d4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059775560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4059775560
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2716232928
Short name T824
Test name
Test status
Simulation time 28344890 ps
CPU time 0.73 seconds
Started May 02 02:19:24 PM PDT 24
Finished May 02 02:19:28 PM PDT 24
Peak memory 203536 kb
Host smart-ffef59fe-88bc-4b02-be4b-d73e3380de8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716232928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2716232928
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2499263410
Short name T784
Test name
Test status
Simulation time 11426204 ps
CPU time 0.68 seconds
Started May 02 02:19:23 PM PDT 24
Finished May 02 02:19:27 PM PDT 24
Peak memory 203812 kb
Host smart-f0e88349-433a-4c81-a39b-5d3142052cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499263410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2499263410
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4157772739
Short name T817
Test name
Test status
Simulation time 113439197 ps
CPU time 7.33 seconds
Started May 02 02:19:02 PM PDT 24
Finished May 02 02:19:13 PM PDT 24
Peak memory 206876 kb
Host smart-8fcd4de7-1ed9-4ddc-9731-ebf13d493b5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157772739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4157772739
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3078829177
Short name T808
Test name
Test status
Simulation time 721460940 ps
CPU time 12.14 seconds
Started May 02 02:19:01 PM PDT 24
Finished May 02 02:19:17 PM PDT 24
Peak memory 206856 kb
Host smart-f8fa7e27-1ab8-4876-8a12-0ee61b49af69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078829177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3078829177
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4149077913
Short name T104
Test name
Test status
Simulation time 17241072 ps
CPU time 0.94 seconds
Started May 02 02:18:59 PM PDT 24
Finished May 02 02:19:04 PM PDT 24
Peak memory 206672 kb
Host smart-8963ffdd-db94-4bd2-badc-7c1acfa03500
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149077913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4149077913
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.921157443
Short name T774
Test name
Test status
Simulation time 154360558 ps
CPU time 2.49 seconds
Started May 02 02:19:00 PM PDT 24
Finished May 02 02:19:06 PM PDT 24
Peak memory 216604 kb
Host smart-74c8c90e-4e24-4cb2-a88f-507775c7025f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921157443 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.921157443
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.652785536
Short name T790
Test name
Test status
Simulation time 158166382 ps
CPU time 2.53 seconds
Started May 02 02:19:01 PM PDT 24
Finished May 02 02:19:07 PM PDT 24
Peak memory 215068 kb
Host smart-34eeed31-4ebd-4664-a29b-88f9ca7c22e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652785536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.652785536
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1790977436
Short name T735
Test name
Test status
Simulation time 50939386 ps
CPU time 0.71 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:00 PM PDT 24
Peak memory 203532 kb
Host smart-4af7b556-c880-4f59-af73-3946ab8d6811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790977436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
790977436
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3141781646
Short name T802
Test name
Test status
Simulation time 132385878 ps
CPU time 1.22 seconds
Started May 02 02:18:55 PM PDT 24
Finished May 02 02:18:58 PM PDT 24
Peak memory 215036 kb
Host smart-e1bc7beb-8ff2-4644-b606-62938a5122f0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141781646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3141781646
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.981840663
Short name T734
Test name
Test status
Simulation time 29513559 ps
CPU time 0.65 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:01 PM PDT 24
Peak memory 203348 kb
Host smart-d44667a8-9726-4af1-8683-65afe88d8af1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981840663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.981840663
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3973781521
Short name T810
Test name
Test status
Simulation time 107364976 ps
CPU time 1.92 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:02 PM PDT 24
Peak memory 215068 kb
Host smart-a0cf39fd-6bb3-4834-b757-a792e0e5d191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973781521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3973781521
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.871672336
Short name T118
Test name
Test status
Simulation time 128946763 ps
CPU time 4.44 seconds
Started May 02 02:18:50 PM PDT 24
Finished May 02 02:18:57 PM PDT 24
Peak memory 215172 kb
Host smart-7e545826-9131-413a-a905-9da6dfaa2309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871672336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.871672336
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1826278532
Short name T116
Test name
Test status
Simulation time 202176254 ps
CPU time 11.65 seconds
Started May 02 02:18:47 PM PDT 24
Finished May 02 02:19:00 PM PDT 24
Peak memory 215056 kb
Host smart-da6fdf53-3ce4-45f7-bafa-8476a86a0ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826278532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1826278532
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3025134711
Short name T806
Test name
Test status
Simulation time 14385942 ps
CPU time 0.71 seconds
Started May 02 02:19:28 PM PDT 24
Finished May 02 02:19:33 PM PDT 24
Peak memory 203412 kb
Host smart-2a94fb50-dc9d-4bb9-826a-f596f1a53249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025134711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3025134711
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1117359325
Short name T751
Test name
Test status
Simulation time 12217199 ps
CPU time 0.75 seconds
Started May 02 02:19:23 PM PDT 24
Finished May 02 02:19:26 PM PDT 24
Peak memory 203492 kb
Host smart-92c25712-5d86-4e74-abe1-9c6e114c86e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117359325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1117359325
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4091171877
Short name T821
Test name
Test status
Simulation time 25903280 ps
CPU time 0.76 seconds
Started May 02 02:19:22 PM PDT 24
Finished May 02 02:19:25 PM PDT 24
Peak memory 203540 kb
Host smart-920cc42e-5a44-42f0-9a2d-e91dae6a73f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091171877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4091171877
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1559597592
Short name T762
Test name
Test status
Simulation time 14089950 ps
CPU time 0.71 seconds
Started May 02 02:19:25 PM PDT 24
Finished May 02 02:19:29 PM PDT 24
Peak memory 203516 kb
Host smart-3910f1f8-7c09-4ab8-b9cd-83390f818e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559597592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1559597592
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.565380555
Short name T744
Test name
Test status
Simulation time 13552481 ps
CPU time 0.71 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 203520 kb
Host smart-f87ae003-5109-4bdb-8f57-d23b0f04bbb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565380555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.565380555
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1007386609
Short name T763
Test name
Test status
Simulation time 36485488 ps
CPU time 0.71 seconds
Started May 02 02:19:28 PM PDT 24
Finished May 02 02:19:33 PM PDT 24
Peak memory 203500 kb
Host smart-ade3f399-0e7d-425f-81a9-cf57f32ef1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007386609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1007386609
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.375514888
Short name T729
Test name
Test status
Simulation time 34295759 ps
CPU time 0.76 seconds
Started May 02 02:19:30 PM PDT 24
Finished May 02 02:19:36 PM PDT 24
Peak memory 203508 kb
Host smart-635405f3-13d0-435e-8127-e30b5a481e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375514888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.375514888
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3526678450
Short name T166
Test name
Test status
Simulation time 171238914 ps
CPU time 0.8 seconds
Started May 02 02:19:32 PM PDT 24
Finished May 02 02:19:37 PM PDT 24
Peak memory 203512 kb
Host smart-e9e7750f-e127-492f-b383-90eaa1c323bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526678450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3526678450
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1563665845
Short name T737
Test name
Test status
Simulation time 34383065 ps
CPU time 0.76 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 203440 kb
Host smart-4ffbe174-49cb-42f9-8057-81d2c72d5a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563665845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1563665845
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1043355643
Short name T731
Test name
Test status
Simulation time 45353184 ps
CPU time 0.76 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:35 PM PDT 24
Peak memory 203500 kb
Host smart-2263c7a5-4d98-4a52-be79-8432a2922ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043355643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1043355643
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.265582046
Short name T144
Test name
Test status
Simulation time 3598737196 ps
CPU time 16.16 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:16 PM PDT 24
Peak memory 206964 kb
Host smart-2dccc6d1-87d0-4d85-9efa-cdf33832fc4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265582046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.265582046
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3680136685
Short name T143
Test name
Test status
Simulation time 185551563 ps
CPU time 11.92 seconds
Started May 02 02:18:58 PM PDT 24
Finished May 02 02:19:13 PM PDT 24
Peak memory 206828 kb
Host smart-66143bb4-f211-4f8e-a49f-376854bfbf3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680136685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3680136685
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1326647436
Short name T103
Test name
Test status
Simulation time 19616990 ps
CPU time 1.16 seconds
Started May 02 02:19:00 PM PDT 24
Finished May 02 02:19:05 PM PDT 24
Peak memory 206840 kb
Host smart-91d32ec0-c141-4d9d-9840-f8e0edcfdb78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326647436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1326647436
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3330772219
Short name T833
Test name
Test status
Simulation time 132247209 ps
CPU time 3.62 seconds
Started May 02 02:19:00 PM PDT 24
Finished May 02 02:19:07 PM PDT 24
Peak memory 216120 kb
Host smart-0931a3aa-b76e-47a4-a3b9-a7c1436b64cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330772219 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3330772219
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.869465280
Short name T793
Test name
Test status
Simulation time 29062310 ps
CPU time 0.74 seconds
Started May 02 02:18:59 PM PDT 24
Finished May 02 02:19:03 PM PDT 24
Peak memory 203488 kb
Host smart-a9112d78-56ba-4016-b45e-bfc47e8b27be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869465280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.869465280
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1276568110
Short name T813
Test name
Test status
Simulation time 20248382 ps
CPU time 1.25 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:02 PM PDT 24
Peak memory 215044 kb
Host smart-571645ea-6af6-45a8-85d1-59be3072a385
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276568110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1276568110
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1321771570
Short name T781
Test name
Test status
Simulation time 17564303 ps
CPU time 0.66 seconds
Started May 02 02:19:01 PM PDT 24
Finished May 02 02:19:05 PM PDT 24
Peak memory 203388 kb
Host smart-023bff38-049a-409e-8c4b-79ea5e5a8de3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321771570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1321771570
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2805069813
Short name T767
Test name
Test status
Simulation time 277664545 ps
CPU time 2.95 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:03 PM PDT 24
Peak memory 215136 kb
Host smart-c65bfab3-6b44-482f-807e-9d2a87388b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805069813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2805069813
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3430453553
Short name T125
Test name
Test status
Simulation time 131185637 ps
CPU time 4.25 seconds
Started May 02 02:18:59 PM PDT 24
Finished May 02 02:19:08 PM PDT 24
Peak memory 215328 kb
Host smart-045cf6af-e843-4c08-bfeb-e5626678224f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430453553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
430453553
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2317236596
Short name T743
Test name
Test status
Simulation time 39872949 ps
CPU time 0.67 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 203812 kb
Host smart-3b25a43c-e6f5-4884-b569-bad46ee1912e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317236596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2317236596
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1263756535
Short name T787
Test name
Test status
Simulation time 78997192 ps
CPU time 0.7 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 203500 kb
Host smart-17945c87-50ba-42e4-8c58-5fa90a8e4c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263756535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1263756535
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.526286255
Short name T785
Test name
Test status
Simulation time 16354430 ps
CPU time 0.73 seconds
Started May 02 02:19:30 PM PDT 24
Finished May 02 02:19:35 PM PDT 24
Peak memory 203820 kb
Host smart-68305ab9-9408-48f4-b0af-e5e2369ccca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526286255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.526286255
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1221604023
Short name T830
Test name
Test status
Simulation time 11090098 ps
CPU time 0.8 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 203536 kb
Host smart-b304b411-0f00-4184-b173-4424ad8e14aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221604023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1221604023
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.107601944
Short name T733
Test name
Test status
Simulation time 55167310 ps
CPU time 0.76 seconds
Started May 02 02:19:30 PM PDT 24
Finished May 02 02:19:35 PM PDT 24
Peak memory 203808 kb
Host smart-06776a8d-d0ab-45f2-95e1-3a8870dd870f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107601944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.107601944
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2508343774
Short name T778
Test name
Test status
Simulation time 54881453 ps
CPU time 0.75 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 203520 kb
Host smart-d9bc8332-7342-4f04-9ffd-d83c07d973a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508343774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2508343774
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3323830444
Short name T757
Test name
Test status
Simulation time 39766780 ps
CPU time 0.68 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 203804 kb
Host smart-3c82398e-fa06-4423-8476-4c6cd77acded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323830444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3323830444
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.581526252
Short name T730
Test name
Test status
Simulation time 12708801 ps
CPU time 0.68 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 203772 kb
Host smart-c2f9c678-1772-445a-b078-c5dba3fcc61d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581526252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.581526252
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2725207138
Short name T805
Test name
Test status
Simulation time 31166258 ps
CPU time 0.7 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:34 PM PDT 24
Peak memory 203516 kb
Host smart-9045ecca-3db2-4351-a28d-a60bfbc331a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725207138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2725207138
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1559308275
Short name T807
Test name
Test status
Simulation time 43406874 ps
CPU time 0.71 seconds
Started May 02 02:19:29 PM PDT 24
Finished May 02 02:19:33 PM PDT 24
Peak memory 203796 kb
Host smart-310726bc-05c0-4257-a23f-99b70cc122c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559308275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1559308275
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.305868046
Short name T132
Test name
Test status
Simulation time 61291151 ps
CPU time 3.78 seconds
Started May 02 02:18:59 PM PDT 24
Finished May 02 02:19:07 PM PDT 24
Peak memory 217360 kb
Host smart-c968c070-5e5e-407b-9af0-6b7e738b720b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305868046 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.305868046
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2613477025
Short name T152
Test name
Test status
Simulation time 88102872 ps
CPU time 2.26 seconds
Started May 02 02:18:59 PM PDT 24
Finished May 02 02:19:05 PM PDT 24
Peak memory 215052 kb
Host smart-40354b7b-8919-4fe4-bc43-0ec896124fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613477025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
613477025
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.431436520
Short name T755
Test name
Test status
Simulation time 67491743 ps
CPU time 0.73 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:01 PM PDT 24
Peak memory 203476 kb
Host smart-74f81905-a5be-4767-ade1-a9f07533dbe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431436520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.431436520
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3654314898
Short name T161
Test name
Test status
Simulation time 139161502 ps
CPU time 3.13 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:02 PM PDT 24
Peak memory 215172 kb
Host smart-20214d70-8e48-4ec2-8655-99f2dce40956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654314898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3654314898
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.445591333
Short name T126
Test name
Test status
Simulation time 307923136 ps
CPU time 3.38 seconds
Started May 02 02:18:58 PM PDT 24
Finished May 02 02:19:04 PM PDT 24
Peak memory 215196 kb
Host smart-fb570d25-e734-448c-9c27-3f30fd862b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445591333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.445591333
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1075206322
Short name T770
Test name
Test status
Simulation time 6015777468 ps
CPU time 15.34 seconds
Started May 02 02:19:01 PM PDT 24
Finished May 02 02:19:21 PM PDT 24
Peak memory 215236 kb
Host smart-3f7af023-5ccc-4895-98a9-2e77c55d6e68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075206322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1075206322
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1181083291
Short name T36
Test name
Test status
Simulation time 192381593 ps
CPU time 3.09 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:02 PM PDT 24
Peak memory 217548 kb
Host smart-f591be9f-bfe2-4372-97ca-ad47512025c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181083291 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1181083291
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1019687007
Short name T788
Test name
Test status
Simulation time 368901312 ps
CPU time 2.6 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:02 PM PDT 24
Peak memory 215076 kb
Host smart-239ad8a5-e724-43e8-82ca-a6ce6e454008
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019687007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
019687007
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2433777946
Short name T803
Test name
Test status
Simulation time 12330635 ps
CPU time 0.72 seconds
Started May 02 02:18:58 PM PDT 24
Finished May 02 02:19:02 PM PDT 24
Peak memory 203520 kb
Host smart-072ee8a8-02fe-402a-8c3b-439e4ecccb45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433777946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
433777946
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1164088742
Short name T150
Test name
Test status
Simulation time 477358876 ps
CPU time 3.97 seconds
Started May 02 02:19:01 PM PDT 24
Finished May 02 02:19:09 PM PDT 24
Peak memory 215096 kb
Host smart-c51d02cb-faf1-47e8-9ecf-e282a4af70d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164088742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1164088742
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3607167112
Short name T760
Test name
Test status
Simulation time 312576344 ps
CPU time 1.95 seconds
Started May 02 02:19:01 PM PDT 24
Finished May 02 02:19:07 PM PDT 24
Peak memory 215220 kb
Host smart-5b1fa7f0-10f0-483f-9fd7-61541e1556c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607167112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
607167112
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2136219562
Short name T391
Test name
Test status
Simulation time 1142021291 ps
CPU time 18.1 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:18 PM PDT 24
Peak memory 215088 kb
Host smart-b826092f-b67c-4934-a1aa-527056dce511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136219562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2136219562
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1450427120
Short name T117
Test name
Test status
Simulation time 107245811 ps
CPU time 1.86 seconds
Started May 02 02:19:01 PM PDT 24
Finished May 02 02:19:07 PM PDT 24
Peak memory 216188 kb
Host smart-5b78378f-f5f9-46e1-993d-cab8b8151d05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450427120 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1450427120
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1995841225
Short name T138
Test name
Test status
Simulation time 69600228 ps
CPU time 2.35 seconds
Started May 02 02:18:56 PM PDT 24
Finished May 02 02:19:00 PM PDT 24
Peak memory 206908 kb
Host smart-56d4026c-cd7f-45fe-af8e-4d989b65ad16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995841225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
995841225
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1263729686
Short name T761
Test name
Test status
Simulation time 24691990 ps
CPU time 0.7 seconds
Started May 02 02:18:58 PM PDT 24
Finished May 02 02:19:03 PM PDT 24
Peak memory 203516 kb
Host smart-a7bf5042-6a7b-498f-a304-b2e9b8de7454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263729686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
263729686
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.398069201
Short name T791
Test name
Test status
Simulation time 603153110 ps
CPU time 3.71 seconds
Started May 02 02:19:00 PM PDT 24
Finished May 02 02:19:08 PM PDT 24
Peak memory 215036 kb
Host smart-fad32514-496c-47db-a65d-eb14c98fb66e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398069201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.398069201
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1314095483
Short name T823
Test name
Test status
Simulation time 137995993 ps
CPU time 3.68 seconds
Started May 02 02:19:07 PM PDT 24
Finished May 02 02:19:13 PM PDT 24
Peak memory 215352 kb
Host smart-24f90997-6800-4aaf-bbdd-243981f77f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314095483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
314095483
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1348473742
Short name T754
Test name
Test status
Simulation time 209212686 ps
CPU time 6.44 seconds
Started May 02 02:18:57 PM PDT 24
Finished May 02 02:19:07 PM PDT 24
Peak memory 215064 kb
Host smart-b5473d82-ec31-4873-ac97-ec190de81cd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348473742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1348473742
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2851006792
Short name T776
Test name
Test status
Simulation time 149062417 ps
CPU time 2.52 seconds
Started May 02 02:19:04 PM PDT 24
Finished May 02 02:19:09 PM PDT 24
Peak memory 216352 kb
Host smart-877fe25c-6daf-4cf4-a775-8fe2bce59412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851006792 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2851006792
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3347519541
Short name T827
Test name
Test status
Simulation time 65321632 ps
CPU time 1.93 seconds
Started May 02 02:19:05 PM PDT 24
Finished May 02 02:19:09 PM PDT 24
Peak memory 215064 kb
Host smart-16967002-7a8d-44a1-b109-79ded17a3ff1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347519541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
347519541
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2028615094
Short name T742
Test name
Test status
Simulation time 185910379 ps
CPU time 0.71 seconds
Started May 02 02:19:01 PM PDT 24
Finished May 02 02:19:05 PM PDT 24
Peak memory 203492 kb
Host smart-4453d936-0f34-410b-a3cd-da611b683ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028615094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
028615094
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3435417477
Short name T38
Test name
Test status
Simulation time 208303721 ps
CPU time 1.76 seconds
Started May 02 02:19:04 PM PDT 24
Finished May 02 02:19:08 PM PDT 24
Peak memory 215120 kb
Host smart-67d2fd29-dc62-4116-bf4c-6422d8f94744
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435417477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3435417477
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3193820886
Short name T747
Test name
Test status
Simulation time 24305428 ps
CPU time 1.5 seconds
Started May 02 02:18:59 PM PDT 24
Finished May 02 02:19:04 PM PDT 24
Peak memory 215276 kb
Host smart-73a7e4ef-81fa-439e-b8d8-5d6f112471b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193820886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
193820886
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.28716738
Short name T135
Test name
Test status
Simulation time 94391266 ps
CPU time 2.52 seconds
Started May 02 02:19:06 PM PDT 24
Finished May 02 02:19:12 PM PDT 24
Peak memory 216652 kb
Host smart-3603c054-318e-4c29-a2b3-8c1d786f45fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28716738 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.28716738
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4179411845
Short name T146
Test name
Test status
Simulation time 117339753 ps
CPU time 1.75 seconds
Started May 02 02:19:06 PM PDT 24
Finished May 02 02:19:10 PM PDT 24
Peak memory 215132 kb
Host smart-ba5d2d5a-d2f1-4942-b48f-3d1228841b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179411845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
179411845
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.890916661
Short name T819
Test name
Test status
Simulation time 37325702 ps
CPU time 0.7 seconds
Started May 02 02:19:05 PM PDT 24
Finished May 02 02:19:08 PM PDT 24
Peak memory 203504 kb
Host smart-e8522a03-98b6-42a0-883b-cecd07980e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890916661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.890916661
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3377881578
Short name T772
Test name
Test status
Simulation time 205662521 ps
CPU time 2.68 seconds
Started May 02 02:19:05 PM PDT 24
Finished May 02 02:19:10 PM PDT 24
Peak memory 215112 kb
Host smart-e646c667-d41e-4b51-a8b5-bf9404854415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377881578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3377881578
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1490983458
Short name T814
Test name
Test status
Simulation time 76136818 ps
CPU time 2.01 seconds
Started May 02 02:19:06 PM PDT 24
Finished May 02 02:19:11 PM PDT 24
Peak memory 216388 kb
Host smart-da543af4-1d1b-412d-a6a9-ec1b87499532
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490983458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
490983458
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.928810601
Short name T815
Test name
Test status
Simulation time 622932336 ps
CPU time 13.88 seconds
Started May 02 02:19:06 PM PDT 24
Finished May 02 02:19:23 PM PDT 24
Peak memory 215508 kb
Host smart-4317c319-759b-4b7b-8388-359cdce079c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928810601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.928810601
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1156087017
Short name T724
Test name
Test status
Simulation time 14479777 ps
CPU time 0.74 seconds
Started May 02 02:06:26 PM PDT 24
Finished May 02 02:06:28 PM PDT 24
Peak memory 205400 kb
Host smart-7aecf8df-a266-4392-b6ea-bd269dd56154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156087017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
156087017
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1139951842
Short name T344
Test name
Test status
Simulation time 117591554 ps
CPU time 2.13 seconds
Started May 02 02:06:24 PM PDT 24
Finished May 02 02:06:28 PM PDT 24
Peak memory 218600 kb
Host smart-a6bbee89-44c0-4343-a107-7e6f263e8b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139951842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1139951842
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2962132127
Short name T551
Test name
Test status
Simulation time 31405731 ps
CPU time 0.78 seconds
Started May 02 02:06:17 PM PDT 24
Finished May 02 02:06:20 PM PDT 24
Peak memory 206684 kb
Host smart-fc8c1f65-c76e-4ac6-91f3-d2cf81902904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962132127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2962132127
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1169574223
Short name T545
Test name
Test status
Simulation time 4064714312 ps
CPU time 20.35 seconds
Started May 02 02:06:26 PM PDT 24
Finished May 02 02:06:48 PM PDT 24
Peak memory 235532 kb
Host smart-b1fbfcee-c462-4e75-b647-78a857f9b079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169574223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1169574223
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.622654731
Short name T364
Test name
Test status
Simulation time 8440463022 ps
CPU time 43.04 seconds
Started May 02 02:06:24 PM PDT 24
Finished May 02 02:07:08 PM PDT 24
Peak memory 237328 kb
Host smart-0112bad8-bfc0-4d6d-bae4-21b4f730af53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622654731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.622654731
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3391942907
Short name T211
Test name
Test status
Simulation time 6880067246 ps
CPU time 20.88 seconds
Started May 02 02:06:23 PM PDT 24
Finished May 02 02:06:45 PM PDT 24
Peak memory 237864 kb
Host smart-e79b2e55-0769-4630-9106-1b23bed4d959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391942907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3391942907
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2536830259
Short name T434
Test name
Test status
Simulation time 2527990308 ps
CPU time 9.6 seconds
Started May 02 02:06:24 PM PDT 24
Finished May 02 02:06:35 PM PDT 24
Peak memory 234840 kb
Host smart-54621e3d-5e10-4341-bd5d-96d66ec55037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536830259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2536830259
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4144923315
Short name T470
Test name
Test status
Simulation time 1682431730 ps
CPU time 6.01 seconds
Started May 02 02:06:27 PM PDT 24
Finished May 02 02:06:35 PM PDT 24
Peak memory 222448 kb
Host smart-74e02084-b426-453c-b5b0-73aa7c3915e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4144923315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4144923315
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3103090345
Short name T52
Test name
Test status
Simulation time 76000661 ps
CPU time 1 seconds
Started May 02 02:06:26 PM PDT 24
Finished May 02 02:06:29 PM PDT 24
Peak memory 235144 kb
Host smart-57fe6c91-c0d9-4778-b320-c267efda146e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103090345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3103090345
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1699230905
Short name T429
Test name
Test status
Simulation time 1437668176 ps
CPU time 11.59 seconds
Started May 02 02:06:25 PM PDT 24
Finished May 02 02:06:38 PM PDT 24
Peak memory 216272 kb
Host smart-d484aa43-e7a6-497f-8ad9-c44fe6efa165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699230905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1699230905
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2731040697
Short name T516
Test name
Test status
Simulation time 233735083 ps
CPU time 3.29 seconds
Started May 02 02:06:25 PM PDT 24
Finished May 02 02:06:30 PM PDT 24
Peak memory 216300 kb
Host smart-93d9d818-a5af-40b4-bf98-38ce82452cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731040697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2731040697
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.726845453
Short name T570
Test name
Test status
Simulation time 325940555 ps
CPU time 0.98 seconds
Started May 02 02:06:26 PM PDT 24
Finished May 02 02:06:28 PM PDT 24
Peak memory 206836 kb
Host smart-a08ef47f-d530-414e-9301-e6abfb9bc8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726845453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.726845453
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.823290679
Short name T10
Test name
Test status
Simulation time 334755208 ps
CPU time 4.01 seconds
Started May 02 02:06:26 PM PDT 24
Finished May 02 02:06:31 PM PDT 24
Peak memory 217564 kb
Host smart-eb766ed1-69b0-478a-a053-c072a554678c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823290679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.823290679
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3777289559
Short name T623
Test name
Test status
Simulation time 39823767 ps
CPU time 0.74 seconds
Started May 02 02:06:39 PM PDT 24
Finished May 02 02:06:40 PM PDT 24
Peak memory 205380 kb
Host smart-5cd0449b-6be3-457f-a2a4-e901b6a0b284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777289559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
777289559
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3048930171
Short name T651
Test name
Test status
Simulation time 17972947 ps
CPU time 0.78 seconds
Started May 02 02:06:27 PM PDT 24
Finished May 02 02:06:29 PM PDT 24
Peak memory 206740 kb
Host smart-3b981a9a-78f9-489f-8a81-4fdeacff84f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048930171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3048930171
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1807002060
Short name T75
Test name
Test status
Simulation time 3978643459 ps
CPU time 9.98 seconds
Started May 02 02:06:32 PM PDT 24
Finished May 02 02:06:42 PM PDT 24
Peak memory 232688 kb
Host smart-38c01f9a-4d41-420a-a8c2-3b1a05be3aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807002060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1807002060
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3803716148
Short name T547
Test name
Test status
Simulation time 7445479587 ps
CPU time 18.16 seconds
Started May 02 02:06:35 PM PDT 24
Finished May 02 02:06:55 PM PDT 24
Peak memory 220500 kb
Host smart-f9a42432-20ca-4bac-abd5-737ab8372701
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3803716148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3803716148
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4073125239
Short name T51
Test name
Test status
Simulation time 125378241 ps
CPU time 0.99 seconds
Started May 02 02:06:34 PM PDT 24
Finished May 02 02:06:36 PM PDT 24
Peak memory 235544 kb
Host smart-dc88099b-69cf-49b8-b33b-a7f229325131
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073125239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4073125239
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3988239471
Short name T366
Test name
Test status
Simulation time 297655944 ps
CPU time 1.06 seconds
Started May 02 02:06:35 PM PDT 24
Finished May 02 02:06:37 PM PDT 24
Peak memory 207148 kb
Host smart-d8b79e53-dbeb-4e5e-a2f3-f764ddcaf568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988239471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3988239471
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3510497715
Short name T402
Test name
Test status
Simulation time 2083599331 ps
CPU time 8.74 seconds
Started May 02 02:06:36 PM PDT 24
Finished May 02 02:06:46 PM PDT 24
Peak memory 216300 kb
Host smart-a27ef64b-f24a-48ec-9abc-e22ef7a2e62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510497715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3510497715
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3530050623
Short name T609
Test name
Test status
Simulation time 1897509684 ps
CPU time 7.37 seconds
Started May 02 02:06:34 PM PDT 24
Finished May 02 02:06:43 PM PDT 24
Peak memory 216204 kb
Host smart-d7759093-8660-406d-a99c-030bd6d57a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530050623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3530050623
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1429192005
Short name T628
Test name
Test status
Simulation time 251339588 ps
CPU time 5.54 seconds
Started May 02 02:06:34 PM PDT 24
Finished May 02 02:06:41 PM PDT 24
Peak memory 216284 kb
Host smart-21918b73-55ea-44f2-861d-16b3dee881b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429192005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1429192005
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2935595194
Short name T692
Test name
Test status
Simulation time 101706233 ps
CPU time 0.85 seconds
Started May 02 02:06:33 PM PDT 24
Finished May 02 02:06:35 PM PDT 24
Peak memory 205756 kb
Host smart-c737e13d-2353-4bab-8b9a-281d948b1bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935595194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2935595194
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1862928135
Short name T687
Test name
Test status
Simulation time 18174883 ps
CPU time 0.71 seconds
Started May 02 02:07:44 PM PDT 24
Finished May 02 02:07:46 PM PDT 24
Peak memory 204816 kb
Host smart-e3dd5bd6-89c4-4b58-af48-52a9b8ee47bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862928135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1862928135
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2595844186
Short name T302
Test name
Test status
Simulation time 1794133282 ps
CPU time 14.52 seconds
Started May 02 02:07:42 PM PDT 24
Finished May 02 02:07:57 PM PDT 24
Peak memory 235116 kb
Host smart-d2b96e25-908e-4ff5-b77a-045f789621aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595844186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2595844186
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3137456980
Short name T256
Test name
Test status
Simulation time 17902663972 ps
CPU time 18 seconds
Started May 02 02:07:33 PM PDT 24
Finished May 02 02:07:53 PM PDT 24
Peak memory 240752 kb
Host smart-6d98cdcf-2258-4230-b0a0-df02a586eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137456980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3137456980
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2874306808
Short name T537
Test name
Test status
Simulation time 627730292 ps
CPU time 4.29 seconds
Started May 02 02:07:45 PM PDT 24
Finished May 02 02:07:50 PM PDT 24
Peak memory 222976 kb
Host smart-f23fcbb4-898d-4153-a7e3-79d80d029e1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2874306808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2874306808
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2676477903
Short name T401
Test name
Test status
Simulation time 2664208939 ps
CPU time 7.39 seconds
Started May 02 02:07:35 PM PDT 24
Finished May 02 02:07:44 PM PDT 24
Peak memory 219552 kb
Host smart-145f911f-fcfb-411b-860d-d3b54d9dd5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676477903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2676477903
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2917244799
Short name T647
Test name
Test status
Simulation time 1187727247 ps
CPU time 2.98 seconds
Started May 02 02:07:38 PM PDT 24
Finished May 02 02:07:42 PM PDT 24
Peak memory 216280 kb
Host smart-0e95cc76-8c45-44cc-a8af-72b14d0f9004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917244799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2917244799
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.764862112
Short name T522
Test name
Test status
Simulation time 122937614 ps
CPU time 1.32 seconds
Started May 02 02:07:34 PM PDT 24
Finished May 02 02:07:37 PM PDT 24
Peak memory 208028 kb
Host smart-40b80093-c388-44bd-b3c8-a81eb1ebb359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764862112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.764862112
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2319811612
Short name T585
Test name
Test status
Simulation time 219041315 ps
CPU time 1.17 seconds
Started May 02 02:07:38 PM PDT 24
Finished May 02 02:07:41 PM PDT 24
Peak memory 206828 kb
Host smart-568bba96-358a-49b6-b9e8-204dae487e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319811612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2319811612
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1544317728
Short name T680
Test name
Test status
Simulation time 15573198 ps
CPU time 0.76 seconds
Started May 02 02:07:56 PM PDT 24
Finished May 02 02:07:58 PM PDT 24
Peak memory 205384 kb
Host smart-56060bab-0f71-48fb-b250-8b1dd3aa78ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544317728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1544317728
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4227912186
Short name T575
Test name
Test status
Simulation time 259608334 ps
CPU time 0.81 seconds
Started May 02 02:07:44 PM PDT 24
Finished May 02 02:07:46 PM PDT 24
Peak memory 206620 kb
Host smart-e52d6b17-7b74-4d70-961a-58ebc55ab408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227912186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4227912186
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2089080933
Short name T287
Test name
Test status
Simulation time 4422465299 ps
CPU time 7.75 seconds
Started May 02 02:07:56 PM PDT 24
Finished May 02 02:08:05 PM PDT 24
Peak memory 216744 kb
Host smart-3544ba49-dc1b-47ee-9f50-ea9b2f50d93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089080933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2089080933
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3079703326
Short name T632
Test name
Test status
Simulation time 145995577 ps
CPU time 4.71 seconds
Started May 02 02:07:55 PM PDT 24
Finished May 02 02:08:01 PM PDT 24
Peak memory 223036 kb
Host smart-fce58f9b-6602-4e0f-a059-6dceaf8de9b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3079703326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3079703326
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4019026198
Short name T55
Test name
Test status
Simulation time 6536781595 ps
CPU time 18.9 seconds
Started May 02 02:07:44 PM PDT 24
Finished May 02 02:08:04 PM PDT 24
Peak memory 216344 kb
Host smart-421d96d8-ab44-4f30-84a2-0f4066cef899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019026198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4019026198
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1171562413
Short name T446
Test name
Test status
Simulation time 640789800 ps
CPU time 4.5 seconds
Started May 02 02:07:44 PM PDT 24
Finished May 02 02:07:49 PM PDT 24
Peak memory 216312 kb
Host smart-7e756b9d-f66d-4975-94cc-fe35c19d5899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171562413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1171562413
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1720596541
Short name T621
Test name
Test status
Simulation time 759609833 ps
CPU time 3.1 seconds
Started May 02 02:07:56 PM PDT 24
Finished May 02 02:08:00 PM PDT 24
Peak memory 216196 kb
Host smart-c439a2bf-f3b1-4715-b1ae-8c9afcffa3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720596541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1720596541
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2008713314
Short name T556
Test name
Test status
Simulation time 233163516 ps
CPU time 1 seconds
Started May 02 02:07:46 PM PDT 24
Finished May 02 02:07:48 PM PDT 24
Peak memory 206776 kb
Host smart-13aefddf-5a88-4a2d-9102-166b84121fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008713314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2008713314
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3668648021
Short name T92
Test name
Test status
Simulation time 638802374 ps
CPU time 7.47 seconds
Started May 02 02:07:57 PM PDT 24
Finished May 02 02:08:06 PM PDT 24
Peak memory 223372 kb
Host smart-674f6f2c-0c27-4292-9c30-e95dcefb09b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668648021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3668648021
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1735844272
Short name T594
Test name
Test status
Simulation time 13488197 ps
CPU time 0.76 seconds
Started May 02 02:08:06 PM PDT 24
Finished May 02 02:08:09 PM PDT 24
Peak memory 205400 kb
Host smart-92704a1b-b472-4756-8e02-a1f87ae700b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735844272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1735844272
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1056854504
Short name T454
Test name
Test status
Simulation time 3060394938 ps
CPU time 34.68 seconds
Started May 02 02:08:03 PM PDT 24
Finished May 02 02:08:39 PM PDT 24
Peak memory 218584 kb
Host smart-e772774a-22f7-4ace-8411-bf6c40990019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056854504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1056854504
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3660893832
Short name T665
Test name
Test status
Simulation time 47069542 ps
CPU time 0.78 seconds
Started May 02 02:07:57 PM PDT 24
Finished May 02 02:07:59 PM PDT 24
Peak memory 206652 kb
Host smart-2de4f911-d5ac-41f0-a013-d7f0b5435810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660893832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3660893832
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.170363519
Short name T378
Test name
Test status
Simulation time 3571270642 ps
CPU time 50.15 seconds
Started May 02 02:08:06 PM PDT 24
Finished May 02 02:08:57 PM PDT 24
Peak memory 224560 kb
Host smart-71c95fb0-7304-4559-ade8-d74eca321d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170363519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.170363519
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2131563625
Short name T328
Test name
Test status
Simulation time 9789905553 ps
CPU time 49.41 seconds
Started May 02 02:08:09 PM PDT 24
Finished May 02 02:09:00 PM PDT 24
Peak memory 226808 kb
Host smart-a9c1658e-c78c-4737-bd78-9f0b54ff2341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131563625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2131563625
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4189291730
Short name T370
Test name
Test status
Simulation time 1052763346 ps
CPU time 5.11 seconds
Started May 02 02:08:04 PM PDT 24
Finished May 02 02:08:10 PM PDT 24
Peak memory 216896 kb
Host smart-e76447f2-e21a-4792-b207-d049bb0fc0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189291730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4189291730
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4005481624
Short name T489
Test name
Test status
Simulation time 1354406194 ps
CPU time 5.31 seconds
Started May 02 02:08:04 PM PDT 24
Finished May 02 02:08:10 PM PDT 24
Peak memory 220324 kb
Host smart-7c892383-3b92-44cd-a100-68f74530c159
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4005481624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4005481624
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4116455626
Short name T715
Test name
Test status
Simulation time 550575751 ps
CPU time 7.28 seconds
Started May 02 02:07:55 PM PDT 24
Finished May 02 02:08:04 PM PDT 24
Peak memory 216260 kb
Host smart-609e0a3d-2839-48aa-a132-2a315f4c90dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116455626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4116455626
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3973823017
Short name T16
Test name
Test status
Simulation time 13829144328 ps
CPU time 9.88 seconds
Started May 02 02:07:55 PM PDT 24
Finished May 02 02:08:07 PM PDT 24
Peak memory 216332 kb
Host smart-1721fdd2-987f-4396-a4c5-1dce37e5df59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973823017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3973823017
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.746277476
Short name T631
Test name
Test status
Simulation time 657871415 ps
CPU time 17.19 seconds
Started May 02 02:07:56 PM PDT 24
Finished May 02 02:08:15 PM PDT 24
Peak memory 216196 kb
Host smart-027e848b-44d8-4c80-9c6a-53799e28617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746277476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.746277476
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2868890117
Short name T566
Test name
Test status
Simulation time 33758286 ps
CPU time 0.74 seconds
Started May 02 02:07:55 PM PDT 24
Finished May 02 02:07:56 PM PDT 24
Peak memory 205792 kb
Host smart-b1188722-45f6-4190-8e9c-46b9cbd6c7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868890117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2868890117
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3712847279
Short name T73
Test name
Test status
Simulation time 122686375949 ps
CPU time 35.6 seconds
Started May 02 02:08:07 PM PDT 24
Finished May 02 02:08:45 PM PDT 24
Peak memory 240972 kb
Host smart-36448b01-2578-47b4-a38e-6b297954a4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712847279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3712847279
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3864584835
Short name T704
Test name
Test status
Simulation time 47919967 ps
CPU time 0.78 seconds
Started May 02 02:08:05 PM PDT 24
Finished May 02 02:08:08 PM PDT 24
Peak memory 205652 kb
Host smart-e4935db2-3009-47c1-af58-3b6634fd4c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864584835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3864584835
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3530607654
Short name T526
Test name
Test status
Simulation time 196587940 ps
CPU time 4.57 seconds
Started May 02 02:08:05 PM PDT 24
Finished May 02 02:08:12 PM PDT 24
Peak memory 223064 kb
Host smart-264783c5-3c99-4ab5-b1e4-dbad4decff18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3530607654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3530607654
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.384671656
Short name T719
Test name
Test status
Simulation time 692881359 ps
CPU time 2.63 seconds
Started May 02 02:08:09 PM PDT 24
Finished May 02 02:08:13 PM PDT 24
Peak memory 218328 kb
Host smart-31a70fd8-9a1d-4b15-89b8-006880a4d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384671656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.384671656
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.39385103
Short name T442
Test name
Test status
Simulation time 8852929377 ps
CPU time 25.98 seconds
Started May 02 02:08:03 PM PDT 24
Finished May 02 02:08:31 PM PDT 24
Peak memory 216320 kb
Host smart-bc8012a0-a827-4fa0-81ef-3f269b55b47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39385103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.39385103
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2467440536
Short name T645
Test name
Test status
Simulation time 130156929 ps
CPU time 2.22 seconds
Started May 02 02:08:04 PM PDT 24
Finished May 02 02:08:08 PM PDT 24
Peak memory 216244 kb
Host smart-40bafe88-a1d7-4922-aeca-6cf7665d7aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467440536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2467440536
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2312721912
Short name T635
Test name
Test status
Simulation time 208525080 ps
CPU time 0.79 seconds
Started May 02 02:08:09 PM PDT 24
Finished May 02 02:08:12 PM PDT 24
Peak memory 205744 kb
Host smart-587e4823-bf4d-4002-ab3b-5b5aa34c5ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312721912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2312721912
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.782388552
Short name T265
Test name
Test status
Simulation time 316091350 ps
CPU time 4.05 seconds
Started May 02 02:08:07 PM PDT 24
Finished May 02 02:08:13 PM PDT 24
Peak memory 216384 kb
Host smart-8d28366e-0496-454e-9ed9-5118a61e06f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782388552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.782388552
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2519103148
Short name T506
Test name
Test status
Simulation time 107036837 ps
CPU time 0.76 seconds
Started May 02 02:08:11 PM PDT 24
Finished May 02 02:08:14 PM PDT 24
Peak memory 204844 kb
Host smart-2c1983e8-ce07-47da-8b51-ee0875ae4d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519103148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2519103148
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2603070042
Short name T569
Test name
Test status
Simulation time 69397144 ps
CPU time 0.81 seconds
Started May 02 02:08:11 PM PDT 24
Finished May 02 02:08:14 PM PDT 24
Peak memory 207012 kb
Host smart-7d79e541-29cb-45c8-adfb-ec67ac28e9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603070042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2603070042
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2076247931
Short name T618
Test name
Test status
Simulation time 3459019418 ps
CPU time 54.21 seconds
Started May 02 02:08:15 PM PDT 24
Finished May 02 02:09:10 PM PDT 24
Peak memory 249160 kb
Host smart-1b2a992f-ba6f-40ad-ac55-77a5ecf8189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076247931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2076247931
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.384087240
Short name T49
Test name
Test status
Simulation time 1443105505 ps
CPU time 5.76 seconds
Started May 02 02:08:11 PM PDT 24
Finished May 02 02:08:18 PM PDT 24
Peak memory 218832 kb
Host smart-f242f15c-ef88-4bf9-94b2-ba0d08b0ae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384087240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.384087240
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.100551607
Short name T452
Test name
Test status
Simulation time 5741312558 ps
CPU time 29.87 seconds
Started May 02 02:08:14 PM PDT 24
Finished May 02 02:08:45 PM PDT 24
Peak memory 224596 kb
Host smart-dc3eb4e5-af3d-474a-bc80-5a27ef82614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100551607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.100551607
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.939208663
Short name T114
Test name
Test status
Simulation time 732429816 ps
CPU time 3.95 seconds
Started May 02 02:08:14 PM PDT 24
Finished May 02 02:08:20 PM PDT 24
Peak memory 218912 kb
Host smart-09bc7c8a-7c40-48d5-8c0a-52bc335d0dab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=939208663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.939208663
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2085432466
Short name T726
Test name
Test status
Simulation time 1632997808 ps
CPU time 16.34 seconds
Started May 02 02:08:12 PM PDT 24
Finished May 02 02:08:30 PM PDT 24
Peak memory 216264 kb
Host smart-2aa794e0-db2a-4a54-9343-f66aab44122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085432466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2085432466
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.603157828
Short name T552
Test name
Test status
Simulation time 1315125253 ps
CPU time 6.5 seconds
Started May 02 02:08:12 PM PDT 24
Finished May 02 02:08:20 PM PDT 24
Peak memory 216224 kb
Host smart-77e3b8f4-7cdb-484c-aee8-489d51e31139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603157828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.603157828
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.606866067
Short name T467
Test name
Test status
Simulation time 4833535353 ps
CPU time 3.59 seconds
Started May 02 02:08:13 PM PDT 24
Finished May 02 02:08:18 PM PDT 24
Peak memory 216360 kb
Host smart-099643b6-8d61-4841-b67e-9386f220e7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606866067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.606866067
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3484373561
Short name T444
Test name
Test status
Simulation time 214795835 ps
CPU time 0.79 seconds
Started May 02 02:08:12 PM PDT 24
Finished May 02 02:08:15 PM PDT 24
Peak memory 205764 kb
Host smart-ec8afa59-cb9e-4600-841c-8e466cd128ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484373561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3484373561
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4021682007
Short name T693
Test name
Test status
Simulation time 1067845729 ps
CPU time 7.08 seconds
Started May 02 02:08:11 PM PDT 24
Finished May 02 02:08:20 PM PDT 24
Peak memory 222568 kb
Host smart-2ed3600a-00c2-42b1-a247-11ba67b48fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021682007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4021682007
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1219316641
Short name T441
Test name
Test status
Simulation time 37049509 ps
CPU time 0.73 seconds
Started May 02 02:08:23 PM PDT 24
Finished May 02 02:08:26 PM PDT 24
Peak memory 205408 kb
Host smart-2b58a25f-63b9-43fb-b5b8-96d40a488a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219316641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1219316641
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4190538586
Short name T93
Test name
Test status
Simulation time 1366619923 ps
CPU time 5.14 seconds
Started May 02 02:08:24 PM PDT 24
Finished May 02 02:08:31 PM PDT 24
Peak memory 223360 kb
Host smart-219e2606-a46b-4cbb-b7ea-0e171902b5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190538586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4190538586
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3074830623
Short name T604
Test name
Test status
Simulation time 35940411 ps
CPU time 0.82 seconds
Started May 02 02:08:15 PM PDT 24
Finished May 02 02:08:17 PM PDT 24
Peak memory 206656 kb
Host smart-06a2cc32-c392-4702-9113-184bcbe4833c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074830623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3074830623
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1326476290
Short name T110
Test name
Test status
Simulation time 10941231720 ps
CPU time 48.7 seconds
Started May 02 02:08:21 PM PDT 24
Finished May 02 02:09:11 PM PDT 24
Peak memory 232804 kb
Host smart-22a5b756-528b-4b30-863a-57bf7bae58fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326476290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1326476290
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4116671075
Short name T215
Test name
Test status
Simulation time 3324009690 ps
CPU time 28.21 seconds
Started May 02 02:08:21 PM PDT 24
Finished May 02 02:08:52 PM PDT 24
Peak memory 218804 kb
Host smart-8377ce79-703e-491f-a3b4-79bb25b8f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116671075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4116671075
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1031641824
Short name T179
Test name
Test status
Simulation time 2284984413 ps
CPU time 11.27 seconds
Started May 02 02:08:21 PM PDT 24
Finished May 02 02:08:34 PM PDT 24
Peak memory 232280 kb
Host smart-0f062089-48f4-4b35-8577-d2ee22611aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031641824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1031641824
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1870118875
Short name T58
Test name
Test status
Simulation time 10429780317 ps
CPU time 10.98 seconds
Started May 02 02:08:21 PM PDT 24
Finished May 02 02:08:34 PM PDT 24
Peak memory 223076 kb
Host smart-f5e679ca-27ee-4335-8b39-56ea12af746b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870118875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1870118875
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.802839675
Short name T648
Test name
Test status
Simulation time 88249015 ps
CPU time 3.8 seconds
Started May 02 02:08:22 PM PDT 24
Finished May 02 02:08:28 PM PDT 24
Peak memory 219220 kb
Host smart-3bb9f4d7-d8d2-440a-8c0b-c27735eb4640
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=802839675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.802839675
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1621835640
Short name T549
Test name
Test status
Simulation time 5707552824 ps
CPU time 9.66 seconds
Started May 02 02:08:12 PM PDT 24
Finished May 02 02:08:24 PM PDT 24
Peak memory 216276 kb
Host smart-76ab9063-7f08-4ffa-a7c6-e80e53041e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621835640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1621835640
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1640883364
Short name T427
Test name
Test status
Simulation time 108275935 ps
CPU time 1.26 seconds
Started May 02 02:08:20 PM PDT 24
Finished May 02 02:08:23 PM PDT 24
Peak memory 216060 kb
Host smart-09824652-4115-4d84-935c-e5fc8e736495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640883364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1640883364
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.567036152
Short name T567
Test name
Test status
Simulation time 29990635 ps
CPU time 0.76 seconds
Started May 02 02:08:23 PM PDT 24
Finished May 02 02:08:26 PM PDT 24
Peak memory 205844 kb
Host smart-cb774ff4-f46a-418e-a219-c79bd3ccb579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567036152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.567036152
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1434353727
Short name T264
Test name
Test status
Simulation time 4627463927 ps
CPU time 19.56 seconds
Started May 02 02:08:21 PM PDT 24
Finished May 02 02:08:42 PM PDT 24
Peak memory 239700 kb
Host smart-f4c99179-0d7e-483c-bb21-2c59de0c77b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434353727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1434353727
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.559767825
Short name T562
Test name
Test status
Simulation time 14975093 ps
CPU time 0.7 seconds
Started May 02 02:08:21 PM PDT 24
Finished May 02 02:08:24 PM PDT 24
Peak memory 204828 kb
Host smart-61510a99-8dc6-4ce9-9a21-58c3f91aa259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559767825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.559767825
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.397720587
Short name T619
Test name
Test status
Simulation time 9913871159 ps
CPU time 14.14 seconds
Started May 02 02:08:23 PM PDT 24
Finished May 02 02:08:40 PM PDT 24
Peak memory 224132 kb
Host smart-f9230403-a656-4b39-8fbd-29b92193b782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397720587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.397720587
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4208665579
Short name T471
Test name
Test status
Simulation time 33257229 ps
CPU time 0.8 seconds
Started May 02 02:08:21 PM PDT 24
Finished May 02 02:08:24 PM PDT 24
Peak memory 206028 kb
Host smart-3045d60f-6c5c-4631-bbd8-78de08394727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208665579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4208665579
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1832505614
Short name T318
Test name
Test status
Simulation time 28245169637 ps
CPU time 82.74 seconds
Started May 02 02:08:22 PM PDT 24
Finished May 02 02:09:47 PM PDT 24
Peak memory 239972 kb
Host smart-fb31288b-bfd0-4f6b-a26b-f9b5afb915f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832505614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1832505614
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1645651612
Short name T183
Test name
Test status
Simulation time 470453473 ps
CPU time 2.57 seconds
Started May 02 02:08:20 PM PDT 24
Finished May 02 02:08:23 PM PDT 24
Peak memory 218884 kb
Host smart-7de21e6f-2286-4b53-8db4-d7785542a223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645651612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1645651612
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1802665273
Short name T261
Test name
Test status
Simulation time 13011173738 ps
CPU time 134.24 seconds
Started May 02 02:08:20 PM PDT 24
Finished May 02 02:10:36 PM PDT 24
Peak memory 245944 kb
Host smart-27fc43d7-148f-49be-b93c-39f8434496ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802665273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1802665273
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1077524758
Short name T360
Test name
Test status
Simulation time 5784856369 ps
CPU time 9.18 seconds
Started May 02 02:08:24 PM PDT 24
Finished May 02 02:08:35 PM PDT 24
Peak memory 218768 kb
Host smart-1fa21ab1-9bf7-4b34-b3dc-cab82b33ec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077524758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1077524758
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1980051649
Short name T234
Test name
Test status
Simulation time 2711939031 ps
CPU time 9.41 seconds
Started May 02 02:08:21 PM PDT 24
Finished May 02 02:08:33 PM PDT 24
Peak memory 221556 kb
Host smart-c95aa745-d646-4010-a7af-841018cf1c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980051649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1980051649
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2109003198
Short name T657
Test name
Test status
Simulation time 1262261267 ps
CPU time 5.77 seconds
Started May 02 02:08:21 PM PDT 24
Finished May 02 02:08:28 PM PDT 24
Peak memory 222980 kb
Host smart-f1737ff3-7b8e-4dd1-9bc3-099bfc4d948c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2109003198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2109003198
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.598441873
Short name T430
Test name
Test status
Simulation time 2304437205 ps
CPU time 12.9 seconds
Started May 02 02:08:20 PM PDT 24
Finished May 02 02:08:35 PM PDT 24
Peak memory 216444 kb
Host smart-5c6085a2-a8dc-42f7-80e4-066e0086a3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598441873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.598441873
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.320901745
Short name T597
Test name
Test status
Simulation time 1040221225 ps
CPU time 7.9 seconds
Started May 02 02:08:22 PM PDT 24
Finished May 02 02:08:32 PM PDT 24
Peak memory 216248 kb
Host smart-13c6cf89-35b7-45fd-adcb-d07cdece1b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320901745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.320901745
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2549093515
Short name T520
Test name
Test status
Simulation time 379618536 ps
CPU time 15.63 seconds
Started May 02 02:08:24 PM PDT 24
Finished May 02 02:08:41 PM PDT 24
Peak memory 216252 kb
Host smart-d9e807bf-8393-4c14-97ab-ed985d63568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549093515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2549093515
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2078071624
Short name T439
Test name
Test status
Simulation time 85712651 ps
CPU time 0.95 seconds
Started May 02 02:08:23 PM PDT 24
Finished May 02 02:08:26 PM PDT 24
Peak memory 206816 kb
Host smart-b39f8196-7f75-4958-aec2-f11c01adf618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078071624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2078071624
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4118496084
Short name T341
Test name
Test status
Simulation time 289562327 ps
CPU time 3.1 seconds
Started May 02 02:08:20 PM PDT 24
Finished May 02 02:08:24 PM PDT 24
Peak memory 218808 kb
Host smart-f01ecec2-cafe-4ff4-88b1-ef747c1f98a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118496084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4118496084
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2099058700
Short name T465
Test name
Test status
Simulation time 16029081 ps
CPU time 0.71 seconds
Started May 02 02:08:29 PM PDT 24
Finished May 02 02:08:32 PM PDT 24
Peak memory 205372 kb
Host smart-2f0753c8-db4f-4c94-a70e-9661603d46d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099058700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2099058700
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1744980751
Short name T581
Test name
Test status
Simulation time 37174647 ps
CPU time 0.75 seconds
Started May 02 02:08:20 PM PDT 24
Finished May 02 02:08:22 PM PDT 24
Peak memory 206672 kb
Host smart-1f2e733e-f893-4e1d-a79a-f9d18145bc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744980751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1744980751
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2993493825
Short name T184
Test name
Test status
Simulation time 6020086329 ps
CPU time 58.31 seconds
Started May 02 02:08:33 PM PDT 24
Finished May 02 02:09:33 PM PDT 24
Peak memory 219116 kb
Host smart-26f4e508-001e-4324-84e2-6911166c6a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993493825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2993493825
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1276007859
Short name T207
Test name
Test status
Simulation time 2907894624 ps
CPU time 10.39 seconds
Started May 02 02:08:29 PM PDT 24
Finished May 02 02:08:41 PM PDT 24
Peak memory 232508 kb
Host smart-cb2357da-8722-4dd3-aad7-b12dc90fe42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276007859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1276007859
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.700351213
Short name T171
Test name
Test status
Simulation time 2992769481 ps
CPU time 6.98 seconds
Started May 02 02:08:28 PM PDT 24
Finished May 02 02:08:37 PM PDT 24
Peak memory 223216 kb
Host smart-7a287583-1a84-433c-9ab5-1bb48add09d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=700351213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.700351213
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3974105977
Short name T164
Test name
Test status
Simulation time 309319705 ps
CPU time 1.17 seconds
Started May 02 02:08:29 PM PDT 24
Finished May 02 02:08:32 PM PDT 24
Peak memory 207360 kb
Host smart-9d2e2a4e-b650-4cf7-a50d-209c0db91e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974105977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3974105977
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2889317909
Short name T66
Test name
Test status
Simulation time 2991528961 ps
CPU time 25.21 seconds
Started May 02 02:08:28 PM PDT 24
Finished May 02 02:08:54 PM PDT 24
Peak memory 216648 kb
Host smart-df8223b9-72c8-4624-a3fb-fd6972729349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889317909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2889317909
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3612890526
Short name T515
Test name
Test status
Simulation time 2295341080 ps
CPU time 6.4 seconds
Started May 02 02:08:28 PM PDT 24
Finished May 02 02:08:35 PM PDT 24
Peak memory 216328 kb
Host smart-5738bdcf-dd90-4a90-a229-421fa801b787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612890526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3612890526
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2552838966
Short name T615
Test name
Test status
Simulation time 515275192 ps
CPU time 1.44 seconds
Started May 02 02:08:30 PM PDT 24
Finished May 02 02:08:33 PM PDT 24
Peak memory 216344 kb
Host smart-6e61a3f5-71a4-4739-9568-68c395960a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552838966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2552838966
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2093610289
Short name T15
Test name
Test status
Simulation time 31977644 ps
CPU time 0.72 seconds
Started May 02 02:08:29 PM PDT 24
Finished May 02 02:08:31 PM PDT 24
Peak memory 205792 kb
Host smart-f70354c6-03f6-456c-98cb-3c0ddfec7beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093610289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2093610289
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1030712009
Short name T525
Test name
Test status
Simulation time 13285362 ps
CPU time 0.73 seconds
Started May 02 02:08:35 PM PDT 24
Finished May 02 02:08:37 PM PDT 24
Peak memory 205384 kb
Host smart-43e06ce1-e9d8-45b5-9ad5-aa34c3d62112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030712009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1030712009
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2253202891
Short name T662
Test name
Test status
Simulation time 58703680 ps
CPU time 0.8 seconds
Started May 02 02:08:28 PM PDT 24
Finished May 02 02:08:30 PM PDT 24
Peak memory 206692 kb
Host smart-04b097c5-4e61-4541-a446-d9bb3db829a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253202891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2253202891
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3377514963
Short name T257
Test name
Test status
Simulation time 39438142572 ps
CPU time 125.55 seconds
Started May 02 02:08:29 PM PDT 24
Finished May 02 02:10:37 PM PDT 24
Peak memory 240920 kb
Host smart-974d9c6c-34ec-4184-909c-e6ad093fb9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377514963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3377514963
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2399063659
Short name T707
Test name
Test status
Simulation time 4188764415 ps
CPU time 11.7 seconds
Started May 02 02:08:36 PM PDT 24
Finished May 02 02:08:49 PM PDT 24
Peak memory 221512 kb
Host smart-6ce3e06d-0aba-4728-ad30-caeb06432be7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2399063659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2399063659
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1992488537
Short name T44
Test name
Test status
Simulation time 152120931 ps
CPU time 1 seconds
Started May 02 02:08:36 PM PDT 24
Finished May 02 02:08:38 PM PDT 24
Peak memory 206932 kb
Host smart-13871f49-cecc-42ed-8c64-2b1d06a0a82d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992488537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1992488537
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.173558857
Short name T642
Test name
Test status
Simulation time 1563898981 ps
CPU time 24.28 seconds
Started May 02 02:08:29 PM PDT 24
Finished May 02 02:08:55 PM PDT 24
Peak memory 216328 kb
Host smart-da5fb158-014c-4221-ab34-1d43720fbc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173558857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.173558857
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2070992649
Short name T614
Test name
Test status
Simulation time 1015895496 ps
CPU time 4.11 seconds
Started May 02 02:08:29 PM PDT 24
Finished May 02 02:08:35 PM PDT 24
Peak memory 216320 kb
Host smart-01bb2237-ae37-4241-924a-246dccde9d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070992649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2070992649
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2819980987
Short name T510
Test name
Test status
Simulation time 6366915127 ps
CPU time 10.2 seconds
Started May 02 02:08:28 PM PDT 24
Finished May 02 02:08:40 PM PDT 24
Peak memory 216508 kb
Host smart-9d09e92b-c464-4a0f-a863-417c1cd5ef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819980987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2819980987
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3827061846
Short name T582
Test name
Test status
Simulation time 801620529 ps
CPU time 0.94 seconds
Started May 02 02:08:27 PM PDT 24
Finished May 02 02:08:30 PM PDT 24
Peak memory 206776 kb
Host smart-59c441d7-9973-4692-91c0-1f7de8600ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827061846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3827061846
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4200369891
Short name T690
Test name
Test status
Simulation time 32469603 ps
CPU time 0.72 seconds
Started May 02 02:08:44 PM PDT 24
Finished May 02 02:08:46 PM PDT 24
Peak memory 205852 kb
Host smart-3a6e5d42-84f1-4e5f-ad05-fc273f5b0954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200369891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4200369891
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4165626821
Short name T462
Test name
Test status
Simulation time 113342400 ps
CPU time 0.76 seconds
Started May 02 02:08:36 PM PDT 24
Finished May 02 02:08:38 PM PDT 24
Peak memory 206008 kb
Host smart-e8af85b6-17a0-4680-9ef5-ea55fc07d893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165626821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4165626821
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.790096391
Short name T696
Test name
Test status
Simulation time 5474200306 ps
CPU time 69.4 seconds
Started May 02 02:08:43 PM PDT 24
Finished May 02 02:09:55 PM PDT 24
Peak memory 240820 kb
Host smart-c3f49f47-5430-4344-8a45-fa728b09126c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790096391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.790096391
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.806879874
Short name T210
Test name
Test status
Simulation time 985923040 ps
CPU time 6.55 seconds
Started May 02 02:08:38 PM PDT 24
Finished May 02 02:08:46 PM PDT 24
Peak memory 224076 kb
Host smart-49c83593-2b95-4a38-b394-d8356f0e4831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806879874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.806879874
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1870705773
Short name T226
Test name
Test status
Simulation time 1212374218 ps
CPU time 9.14 seconds
Started May 02 02:08:38 PM PDT 24
Finished May 02 02:08:49 PM PDT 24
Peak memory 221296 kb
Host smart-39099af6-6db8-42c9-8066-2f94e2868bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870705773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1870705773
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1732156341
Short name T540
Test name
Test status
Simulation time 1365697508 ps
CPU time 15.32 seconds
Started May 02 02:08:43 PM PDT 24
Finished May 02 02:09:00 PM PDT 24
Peak memory 221916 kb
Host smart-3711d13f-0814-4fbd-aa28-a75fda5d2f0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1732156341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1732156341
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1657957873
Short name T698
Test name
Test status
Simulation time 7253449167 ps
CPU time 23.26 seconds
Started May 02 02:08:36 PM PDT 24
Finished May 02 02:09:00 PM PDT 24
Peak memory 220236 kb
Host smart-3b80648e-a7f1-4c48-a8d8-62de1361fed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657957873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1657957873
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3263677522
Short name T649
Test name
Test status
Simulation time 4384628661 ps
CPU time 16.16 seconds
Started May 02 02:08:36 PM PDT 24
Finished May 02 02:08:54 PM PDT 24
Peak memory 216256 kb
Host smart-54a14216-e29c-4c76-8ff6-2d0d1eaeb1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263677522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3263677522
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2262354086
Short name T491
Test name
Test status
Simulation time 39254574 ps
CPU time 0.74 seconds
Started May 02 02:08:36 PM PDT 24
Finished May 02 02:08:38 PM PDT 24
Peak memory 205804 kb
Host smart-908da1c7-1db2-4d94-84dc-0876021eebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262354086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2262354086
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.8656684
Short name T595
Test name
Test status
Simulation time 192958054 ps
CPU time 0.93 seconds
Started May 02 02:08:38 PM PDT 24
Finished May 02 02:08:40 PM PDT 24
Peak memory 206780 kb
Host smart-19216b7a-e133-4f84-9e96-ea5620253308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8656684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.8656684
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2211767137
Short name T445
Test name
Test status
Simulation time 43151514 ps
CPU time 0.71 seconds
Started May 02 02:06:47 PM PDT 24
Finished May 02 02:06:49 PM PDT 24
Peak memory 204860 kb
Host smart-f9ff1903-6910-4ba5-b52b-024a68b82a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211767137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
211767137
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1483591806
Short name T694
Test name
Test status
Simulation time 15915140 ps
CPU time 0.76 seconds
Started May 02 02:06:38 PM PDT 24
Finished May 02 02:06:40 PM PDT 24
Peak memory 206648 kb
Host smart-a9b331cb-b748-401b-af9b-0c23bb5ff45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483591806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1483591806
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4150362043
Short name T557
Test name
Test status
Simulation time 1013035078 ps
CPU time 14.36 seconds
Started May 02 02:06:44 PM PDT 24
Finished May 02 02:06:59 PM PDT 24
Peak memory 233732 kb
Host smart-49747707-109d-4df2-aed0-3bd8c4596126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150362043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4150362043
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3352945500
Short name T178
Test name
Test status
Simulation time 4216297058 ps
CPU time 12.23 seconds
Started May 02 02:06:40 PM PDT 24
Finished May 02 02:06:54 PM PDT 24
Peak memory 232352 kb
Host smart-422a9e08-4d37-4362-9398-b3e6f4e31e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352945500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3352945500
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3697671176
Short name T8
Test name
Test status
Simulation time 64127512 ps
CPU time 2.62 seconds
Started May 02 02:06:41 PM PDT 24
Finished May 02 02:06:45 PM PDT 24
Peak memory 222016 kb
Host smart-6d0a0b87-5676-472f-a404-d4171f2b13ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697671176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3697671176
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2457004440
Short name T242
Test name
Test status
Simulation time 24283412696 ps
CPU time 34.5 seconds
Started May 02 02:06:40 PM PDT 24
Finished May 02 02:07:17 PM PDT 24
Peak memory 224572 kb
Host smart-976d5d55-cff2-4e03-95b7-564d374d975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457004440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2457004440
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3933113412
Short name T464
Test name
Test status
Simulation time 1142387787 ps
CPU time 13.22 seconds
Started May 02 02:06:40 PM PDT 24
Finished May 02 02:06:55 PM PDT 24
Peak memory 222376 kb
Host smart-c5116b27-a7a1-4835-83ef-8571d16a1c02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3933113412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3933113412
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1048363519
Short name T399
Test name
Test status
Simulation time 2820143776 ps
CPU time 33.03 seconds
Started May 02 02:06:39 PM PDT 24
Finished May 02 02:07:13 PM PDT 24
Peak memory 216332 kb
Host smart-367a58b4-6640-40d3-8de0-727bb28560f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048363519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1048363519
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1618648835
Short name T675
Test name
Test status
Simulation time 42458904716 ps
CPU time 27.29 seconds
Started May 02 02:06:40 PM PDT 24
Finished May 02 02:07:10 PM PDT 24
Peak memory 217500 kb
Host smart-02bd27ac-7ece-49f7-a9a0-3cb84c12c861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618648835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1618648835
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4189038834
Short name T423
Test name
Test status
Simulation time 402873797 ps
CPU time 2.15 seconds
Started May 02 02:06:40 PM PDT 24
Finished May 02 02:06:44 PM PDT 24
Peak memory 216264 kb
Host smart-c4784068-11db-4596-9519-d8cf402b80ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189038834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4189038834
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1777851943
Short name T443
Test name
Test status
Simulation time 70934333 ps
CPU time 0.93 seconds
Started May 02 02:06:40 PM PDT 24
Finished May 02 02:06:43 PM PDT 24
Peak memory 205828 kb
Host smart-fd063686-e473-42a6-a872-2329b7fd3747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777851943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1777851943
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.529358643
Short name T192
Test name
Test status
Simulation time 13943624244 ps
CPU time 14.3 seconds
Started May 02 02:06:40 PM PDT 24
Finished May 02 02:06:56 PM PDT 24
Peak memory 238920 kb
Host smart-9a668d5a-0088-4fce-baf7-f2256b5beed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529358643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.529358643
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3282913137
Short name T472
Test name
Test status
Simulation time 12504749 ps
CPU time 0.72 seconds
Started May 02 02:08:49 PM PDT 24
Finished May 02 02:08:51 PM PDT 24
Peak memory 205368 kb
Host smart-1ef67062-52da-4c51-9d5b-b586323460ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282913137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3282913137
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2564494162
Short name T22
Test name
Test status
Simulation time 25718407 ps
CPU time 0.8 seconds
Started May 02 02:08:41 PM PDT 24
Finished May 02 02:08:44 PM PDT 24
Peak memory 206708 kb
Host smart-43d34deb-9ef5-4a7c-8963-37ac722fc349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564494162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2564494162
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2523753837
Short name T517
Test name
Test status
Simulation time 3816029355 ps
CPU time 56.37 seconds
Started May 02 02:08:42 PM PDT 24
Finished May 02 02:09:41 PM PDT 24
Peak memory 249168 kb
Host smart-b19c642a-4dc5-47a6-8d0e-451c10cbd57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523753837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2523753837
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3186982624
Short name T199
Test name
Test status
Simulation time 7205714538 ps
CPU time 41.65 seconds
Started May 02 02:08:45 PM PDT 24
Finished May 02 02:09:29 PM PDT 24
Peak memory 218660 kb
Host smart-c158c4ec-5e2f-4397-8574-43259a85a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186982624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3186982624
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.448001661
Short name T320
Test name
Test status
Simulation time 9804576007 ps
CPU time 26.64 seconds
Started May 02 02:08:45 PM PDT 24
Finished May 02 02:09:13 PM PDT 24
Peak memory 232516 kb
Host smart-08a77b3a-4231-4bb7-94e6-331b5b15a5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448001661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.448001661
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2055765431
Short name T484
Test name
Test status
Simulation time 3012387496 ps
CPU time 7.08 seconds
Started May 02 02:08:43 PM PDT 24
Finished May 02 02:08:53 PM PDT 24
Peak memory 223052 kb
Host smart-4f42eb09-67d4-402a-bfcd-bea0892b93b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2055765431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2055765431
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1084422013
Short name T165
Test name
Test status
Simulation time 61961860 ps
CPU time 1.13 seconds
Started May 02 02:08:51 PM PDT 24
Finished May 02 02:08:53 PM PDT 24
Peak memory 207264 kb
Host smart-2bac9a2a-93e3-4990-a045-04a89c27aba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084422013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1084422013
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.454296291
Short name T405
Test name
Test status
Simulation time 1885837157 ps
CPU time 7.39 seconds
Started May 02 02:08:46 PM PDT 24
Finished May 02 02:08:55 PM PDT 24
Peak memory 216276 kb
Host smart-059a4cff-997a-4893-9c1d-01f4d7095047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454296291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.454296291
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4096462683
Short name T468
Test name
Test status
Simulation time 2396167075 ps
CPU time 8.74 seconds
Started May 02 02:08:44 PM PDT 24
Finished May 02 02:08:55 PM PDT 24
Peak memory 216312 kb
Host smart-14dcac36-38ae-4f4b-8d85-6b17ba40217b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096462683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4096462683
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3446405172
Short name T578
Test name
Test status
Simulation time 811637522 ps
CPU time 3.28 seconds
Started May 02 02:08:48 PM PDT 24
Finished May 02 02:08:53 PM PDT 24
Peak memory 216308 kb
Host smart-fa40108d-d6c7-4970-94a1-0fdec792a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446405172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3446405172
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3196491805
Short name T686
Test name
Test status
Simulation time 41338245 ps
CPU time 0.83 seconds
Started May 02 02:08:43 PM PDT 24
Finished May 02 02:08:46 PM PDT 24
Peak memory 205780 kb
Host smart-d780e5b1-9411-4f71-a5d0-c20635b95c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196491805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3196491805
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4117214478
Short name T488
Test name
Test status
Simulation time 12694543 ps
CPU time 0.71 seconds
Started May 02 02:08:56 PM PDT 24
Finished May 02 02:08:58 PM PDT 24
Peak memory 205372 kb
Host smart-834b7d34-bf49-4d5d-bc66-cfac7ef957e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117214478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4117214478
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.659112960
Short name T106
Test name
Test status
Simulation time 39041103839 ps
CPU time 35.71 seconds
Started May 02 02:08:51 PM PDT 24
Finished May 02 02:09:28 PM PDT 24
Peak memory 232704 kb
Host smart-e042b6ae-d55c-4838-bf41-711c51aa5826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659112960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.659112960
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3470500097
Short name T487
Test name
Test status
Simulation time 19916654 ps
CPU time 0.77 seconds
Started May 02 02:08:51 PM PDT 24
Finished May 02 02:08:53 PM PDT 24
Peak memory 205672 kb
Host smart-133a4c74-a874-4e71-9d4c-064dbfb1b35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470500097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3470500097
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.346617804
Short name T373
Test name
Test status
Simulation time 1580119859 ps
CPU time 17.47 seconds
Started May 02 02:08:52 PM PDT 24
Finished May 02 02:09:11 PM PDT 24
Peak memory 238780 kb
Host smart-e3f0c0e1-e756-4561-948d-71f07d4bdd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346617804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.346617804
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2055164265
Short name T248
Test name
Test status
Simulation time 410690982 ps
CPU time 3.23 seconds
Started May 02 02:08:57 PM PDT 24
Finished May 02 02:09:01 PM PDT 24
Peak memory 218896 kb
Host smart-9fb6a21c-e9b4-49e2-9b46-cf630b3d9b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055164265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2055164265
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3185761871
Short name T611
Test name
Test status
Simulation time 258658994 ps
CPU time 3.23 seconds
Started May 02 02:08:52 PM PDT 24
Finished May 02 02:08:57 PM PDT 24
Peak memory 218936 kb
Host smart-5f7afb73-951d-492e-9109-4be5ef06a5c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3185761871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3185761871
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3511835090
Short name T18
Test name
Test status
Simulation time 3530087162 ps
CPU time 7.01 seconds
Started May 02 02:08:50 PM PDT 24
Finished May 02 02:08:58 PM PDT 24
Peak memory 216592 kb
Host smart-e55ba8c0-805d-4cdc-8a3a-56a8def121a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511835090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3511835090
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.437684868
Short name T498
Test name
Test status
Simulation time 15263131196 ps
CPU time 7.67 seconds
Started May 02 02:08:56 PM PDT 24
Finished May 02 02:09:05 PM PDT 24
Peak memory 216320 kb
Host smart-c553ad75-713d-44b8-b20f-7233994ca67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437684868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.437684868
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3430804967
Short name T705
Test name
Test status
Simulation time 128866976 ps
CPU time 0.86 seconds
Started May 02 02:08:51 PM PDT 24
Finished May 02 02:08:53 PM PDT 24
Peak memory 206804 kb
Host smart-261bf4aa-ed20-427b-a139-183ae3e079c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430804967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3430804967
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2500291784
Short name T28
Test name
Test status
Simulation time 4490776152 ps
CPU time 14.53 seconds
Started May 02 02:08:51 PM PDT 24
Finished May 02 02:09:07 PM PDT 24
Peak memory 218652 kb
Host smart-4138cc4d-6520-4d1c-904b-e1a2ab76792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500291784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2500291784
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1997518348
Short name T655
Test name
Test status
Simulation time 43222343 ps
CPU time 0.71 seconds
Started May 02 02:08:55 PM PDT 24
Finished May 02 02:08:57 PM PDT 24
Peak memory 204876 kb
Host smart-ac3c85a1-6a94-4f12-855c-1d2edde53c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997518348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1997518348
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1606581483
Short name T672
Test name
Test status
Simulation time 49219218 ps
CPU time 0.83 seconds
Started May 02 02:08:49 PM PDT 24
Finished May 02 02:08:51 PM PDT 24
Peak memory 206656 kb
Host smart-45fd86b0-8975-4ddb-8bce-a5b7a87cc8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606581483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1606581483
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1517519180
Short name T309
Test name
Test status
Simulation time 1816843873 ps
CPU time 19.13 seconds
Started May 02 02:08:56 PM PDT 24
Finished May 02 02:09:16 PM PDT 24
Peak memory 235308 kb
Host smart-23e93139-a29c-405f-9af9-3233307a8a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517519180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1517519180
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3907255980
Short name T48
Test name
Test status
Simulation time 224528079 ps
CPU time 4.7 seconds
Started May 02 02:08:58 PM PDT 24
Finished May 02 02:09:04 PM PDT 24
Peak memory 224304 kb
Host smart-5da420b4-162d-4f69-adb0-afb4d687c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907255980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3907255980
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1981067757
Short name T275
Test name
Test status
Simulation time 531179803 ps
CPU time 5.71 seconds
Started May 02 02:08:56 PM PDT 24
Finished May 02 02:09:03 PM PDT 24
Peak memory 221920 kb
Host smart-d3bd509f-c5ce-49b6-b62f-facf83447f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981067757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1981067757
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4177376530
Short name T666
Test name
Test status
Simulation time 549083982 ps
CPU time 4.34 seconds
Started May 02 02:09:00 PM PDT 24
Finished May 02 02:09:06 PM PDT 24
Peak memory 218524 kb
Host smart-99293684-1c9b-48af-b7ba-9b67b332c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177376530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4177376530
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2902627412
Short name T461
Test name
Test status
Simulation time 2954324198 ps
CPU time 5.65 seconds
Started May 02 02:08:59 PM PDT 24
Finished May 02 02:09:05 PM PDT 24
Peak memory 219316 kb
Host smart-f424eae1-45aa-4bb7-8203-6837d20f0abe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2902627412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2902627412
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2025085148
Short name T407
Test name
Test status
Simulation time 1802859556 ps
CPU time 25.78 seconds
Started May 02 02:08:53 PM PDT 24
Finished May 02 02:09:20 PM PDT 24
Peak memory 216312 kb
Host smart-948784f5-6284-445c-9f75-ab3a50c497b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025085148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2025085148
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1390648907
Short name T542
Test name
Test status
Simulation time 1239620240 ps
CPU time 7.16 seconds
Started May 02 02:08:54 PM PDT 24
Finished May 02 02:09:02 PM PDT 24
Peak memory 216344 kb
Host smart-bbd0a180-ab46-4914-a293-892b28bcb5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390648907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1390648907
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.252043118
Short name T656
Test name
Test status
Simulation time 55415078 ps
CPU time 0.96 seconds
Started May 02 02:08:49 PM PDT 24
Finished May 02 02:08:51 PM PDT 24
Peak memory 207828 kb
Host smart-c48a5b85-c1cd-47eb-8dd9-5ef44555416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252043118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.252043118
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3560193991
Short name T717
Test name
Test status
Simulation time 148879805 ps
CPU time 0.86 seconds
Started May 02 02:08:53 PM PDT 24
Finished May 02 02:08:55 PM PDT 24
Peak memory 206796 kb
Host smart-26210fbb-7db1-4968-aae7-514399490984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560193991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3560193991
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.817385144
Short name T270
Test name
Test status
Simulation time 24012517616 ps
CPU time 16.7 seconds
Started May 02 02:08:56 PM PDT 24
Finished May 02 02:09:13 PM PDT 24
Peak memory 219060 kb
Host smart-b27583b8-0c33-4156-b5c1-2690b07af582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817385144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.817385144
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.338969727
Short name T514
Test name
Test status
Simulation time 18634753 ps
CPU time 0.71 seconds
Started May 02 02:09:05 PM PDT 24
Finished May 02 02:09:09 PM PDT 24
Peak memory 205720 kb
Host smart-a5666c57-d996-420f-a834-d4119948e24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338969727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.338969727
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2474204216
Short name T548
Test name
Test status
Simulation time 36845453 ps
CPU time 0.76 seconds
Started May 02 02:09:05 PM PDT 24
Finished May 02 02:09:09 PM PDT 24
Peak memory 206648 kb
Host smart-52ece95a-9f56-4cc3-9810-08e0124298c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474204216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2474204216
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2703625213
Short name T706
Test name
Test status
Simulation time 5161406850 ps
CPU time 22.08 seconds
Started May 02 02:09:05 PM PDT 24
Finished May 02 02:09:31 PM PDT 24
Peak memory 248484 kb
Host smart-1fcc07e8-205f-406c-bbf0-4b07b42e9e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703625213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2703625213
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.127250734
Short name T124
Test name
Test status
Simulation time 6540410007 ps
CPU time 61.21 seconds
Started May 02 02:09:09 PM PDT 24
Finished May 02 02:10:13 PM PDT 24
Peak memory 236140 kb
Host smart-38fea524-6bb6-4429-abad-a842fd73a078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127250734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.127250734
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.573614270
Short name T240
Test name
Test status
Simulation time 6752437178 ps
CPU time 3.34 seconds
Started May 02 02:09:03 PM PDT 24
Finished May 02 02:09:09 PM PDT 24
Peak memory 218572 kb
Host smart-7f502716-17df-45d7-a203-9e9ad4de586e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573614270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.573614270
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.400434856
Short name T590
Test name
Test status
Simulation time 1964189006 ps
CPU time 8.64 seconds
Started May 02 02:09:05 PM PDT 24
Finished May 02 02:09:17 PM PDT 24
Peak memory 221436 kb
Host smart-29b9e260-badb-4738-b741-145036e8ba1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=400434856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.400434856
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3035090720
Short name T59
Test name
Test status
Simulation time 6252632788 ps
CPU time 30.04 seconds
Started May 02 02:09:04 PM PDT 24
Finished May 02 02:09:37 PM PDT 24
Peak memory 221964 kb
Host smart-f106bf55-206d-4ffc-98f1-42f4fd72a69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035090720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3035090720
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3039703188
Short name T550
Test name
Test status
Simulation time 830185979 ps
CPU time 2.04 seconds
Started May 02 02:09:05 PM PDT 24
Finished May 02 02:09:11 PM PDT 24
Peak memory 207740 kb
Host smart-80e2efba-f836-4d13-802a-ec60e40c27cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039703188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3039703188
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.950361060
Short name T695
Test name
Test status
Simulation time 497838273 ps
CPU time 5.28 seconds
Started May 02 02:09:04 PM PDT 24
Finished May 02 02:09:12 PM PDT 24
Peak memory 216344 kb
Host smart-11662ca7-ba04-4ef2-9acf-54cb35535f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950361060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.950361060
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2315829593
Short name T511
Test name
Test status
Simulation time 43341641 ps
CPU time 0.85 seconds
Started May 02 02:09:04 PM PDT 24
Finished May 02 02:09:08 PM PDT 24
Peak memory 205824 kb
Host smart-2c8ce096-b035-47f7-b840-dd2b6506e2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315829593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2315829593
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3954298648
Short name T599
Test name
Test status
Simulation time 38506175 ps
CPU time 0.73 seconds
Started May 02 02:09:11 PM PDT 24
Finished May 02 02:09:13 PM PDT 24
Peak memory 205396 kb
Host smart-f07b2257-6a88-491f-9f6f-f886315ab685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954298648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3954298648
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.984601418
Short name T451
Test name
Test status
Simulation time 40974381 ps
CPU time 0.75 seconds
Started May 02 02:09:04 PM PDT 24
Finished May 02 02:09:09 PM PDT 24
Peak memory 206684 kb
Host smart-9a2f318e-f0f2-47d0-b66d-29e5a63a98ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984601418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.984601418
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3819550958
Short name T279
Test name
Test status
Simulation time 45340667361 ps
CPU time 133.7 seconds
Started May 02 02:09:12 PM PDT 24
Finished May 02 02:11:28 PM PDT 24
Peak memory 231736 kb
Host smart-9f599d99-9512-48d6-8236-0c8ec07b2223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819550958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3819550958
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.829023374
Short name T493
Test name
Test status
Simulation time 4312345581 ps
CPU time 12.8 seconds
Started May 02 02:09:09 PM PDT 24
Finished May 02 02:09:24 PM PDT 24
Peak memory 220724 kb
Host smart-e58db72c-1288-4882-bbd6-1aa143171019
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=829023374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.829023374
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3087060399
Short name T395
Test name
Test status
Simulation time 12027453654 ps
CPU time 59.72 seconds
Started May 02 02:09:03 PM PDT 24
Finished May 02 02:10:05 PM PDT 24
Peak memory 216348 kb
Host smart-acaab0d3-8776-4f03-b762-647139f5f392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087060399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3087060399
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1096238160
Short name T519
Test name
Test status
Simulation time 10829151503 ps
CPU time 8.25 seconds
Started May 02 02:09:03 PM PDT 24
Finished May 02 02:09:13 PM PDT 24
Peak memory 216284 kb
Host smart-5c6c2614-2053-4056-a769-6318d651ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096238160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1096238160
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.985088453
Short name T3
Test name
Test status
Simulation time 176078321 ps
CPU time 2.65 seconds
Started May 02 02:09:05 PM PDT 24
Finished May 02 02:09:11 PM PDT 24
Peak memory 216312 kb
Host smart-8880f305-bc6e-45b8-931e-f532881c7609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985088453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.985088453
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2084671316
Short name T633
Test name
Test status
Simulation time 87942303 ps
CPU time 0.97 seconds
Started May 02 02:09:05 PM PDT 24
Finished May 02 02:09:09 PM PDT 24
Peak memory 206824 kb
Host smart-a14ae5e8-0e55-40e4-83da-70135d87a832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084671316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2084671316
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2211508354
Short name T463
Test name
Test status
Simulation time 46586493 ps
CPU time 0.7 seconds
Started May 02 02:09:20 PM PDT 24
Finished May 02 02:09:22 PM PDT 24
Peak memory 205408 kb
Host smart-82ad3e8a-9bcd-48a3-95bd-1d75b2f012d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211508354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2211508354
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3317241678
Short name T278
Test name
Test status
Simulation time 167565289 ps
CPU time 3.77 seconds
Started May 02 02:09:14 PM PDT 24
Finished May 02 02:09:19 PM PDT 24
Peak memory 223028 kb
Host smart-ce861943-16ef-4781-b75a-4151d4ba0211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317241678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3317241678
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4191274498
Short name T637
Test name
Test status
Simulation time 16936212 ps
CPU time 0.78 seconds
Started May 02 02:09:11 PM PDT 24
Finished May 02 02:09:15 PM PDT 24
Peak memory 205656 kb
Host smart-d860bab4-5d2d-4bf5-a0d9-907d66a23381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191274498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4191274498
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2952497094
Short name T625
Test name
Test status
Simulation time 9849496786 ps
CPU time 79.81 seconds
Started May 02 02:09:15 PM PDT 24
Finished May 02 02:10:36 PM PDT 24
Peak memory 254708 kb
Host smart-8b33d629-82a2-411c-b594-281ece56a2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952497094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2952497094
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3170280450
Short name T100
Test name
Test status
Simulation time 276865781 ps
CPU time 3.56 seconds
Started May 02 02:09:13 PM PDT 24
Finished May 02 02:09:19 PM PDT 24
Peak memory 223116 kb
Host smart-86d311f4-08a5-4205-abbf-c96b101c836f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170280450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3170280450
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2537183209
Short name T247
Test name
Test status
Simulation time 2478343130 ps
CPU time 33.19 seconds
Started May 02 02:09:15 PM PDT 24
Finished May 02 02:09:49 PM PDT 24
Peak memory 227460 kb
Host smart-6179803b-530c-476c-913a-adb6ce21656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537183209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2537183209
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2481983634
Short name T347
Test name
Test status
Simulation time 273971539 ps
CPU time 2.7 seconds
Started May 02 02:09:12 PM PDT 24
Finished May 02 02:09:17 PM PDT 24
Peak memory 218524 kb
Host smart-1e29e410-5298-4d83-8b39-6c557b4eed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481983634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2481983634
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2239815837
Short name T644
Test name
Test status
Simulation time 2699209527 ps
CPU time 7.69 seconds
Started May 02 02:09:14 PM PDT 24
Finished May 02 02:09:23 PM PDT 24
Peak memory 222204 kb
Host smart-08ffa5b0-8de0-4c70-a934-56609f5a491b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2239815837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2239815837
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3225294301
Short name T691
Test name
Test status
Simulation time 1567854457 ps
CPU time 11.62 seconds
Started May 02 02:09:12 PM PDT 24
Finished May 02 02:09:26 PM PDT 24
Peak memory 216324 kb
Host smart-602d6679-a806-403c-a3a6-8b1c50b75020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225294301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3225294301
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.879366057
Short name T602
Test name
Test status
Simulation time 124133332 ps
CPU time 1.06 seconds
Started May 02 02:09:13 PM PDT 24
Finished May 02 02:09:16 PM PDT 24
Peak memory 207024 kb
Host smart-28a58c59-db28-4df9-853c-34a39378be50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879366057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.879366057
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1250255966
Short name T553
Test name
Test status
Simulation time 133702388 ps
CPU time 4.5 seconds
Started May 02 02:09:11 PM PDT 24
Finished May 02 02:09:17 PM PDT 24
Peak memory 216392 kb
Host smart-c1e18fc0-8120-479d-8a4c-e2f38fb07461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250255966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1250255966
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2977799849
Short name T603
Test name
Test status
Simulation time 430875235 ps
CPU time 0.87 seconds
Started May 02 02:09:14 PM PDT 24
Finished May 02 02:09:16 PM PDT 24
Peak memory 206264 kb
Host smart-fa9433a3-7938-47d0-9914-37a601ad5eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977799849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2977799849
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1108008958
Short name T31
Test name
Test status
Simulation time 12651705 ps
CPU time 0.73 seconds
Started May 02 02:09:27 PM PDT 24
Finished May 02 02:09:29 PM PDT 24
Peak memory 204888 kb
Host smart-9551980f-1999-4171-ae0f-24910a99c6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108008958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1108008958
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1697703724
Short name T700
Test name
Test status
Simulation time 3053134573 ps
CPU time 9.89 seconds
Started May 02 02:09:20 PM PDT 24
Finished May 02 02:09:32 PM PDT 24
Peak memory 224576 kb
Host smart-481142d6-675f-4bd6-a425-cf430f8191a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697703724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1697703724
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2086956535
Short name T500
Test name
Test status
Simulation time 19501422 ps
CPU time 0.77 seconds
Started May 02 02:09:20 PM PDT 24
Finished May 02 02:09:22 PM PDT 24
Peak memory 205972 kb
Host smart-b7e30019-9418-4bd9-802f-6060157cf7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086956535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2086956535
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3487729754
Short name T638
Test name
Test status
Simulation time 5945341613 ps
CPU time 25.1 seconds
Started May 02 02:09:21 PM PDT 24
Finished May 02 02:09:47 PM PDT 24
Peak memory 224540 kb
Host smart-d1ad1fce-17e8-4591-a335-67c35cf5e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487729754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3487729754
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1613224486
Short name T297
Test name
Test status
Simulation time 12416274444 ps
CPU time 19.55 seconds
Started May 02 02:09:18 PM PDT 24
Finished May 02 02:09:39 PM PDT 24
Peak memory 240868 kb
Host smart-d6335d89-65d7-4dc4-8a81-6b99fcda1ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613224486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1613224486
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.480518965
Short name T555
Test name
Test status
Simulation time 1068374040 ps
CPU time 4.04 seconds
Started May 02 02:09:21 PM PDT 24
Finished May 02 02:09:27 PM PDT 24
Peak memory 220608 kb
Host smart-a65341c5-95e9-454c-af6f-c0d4650c0bd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=480518965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.480518965
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3155258510
Short name T536
Test name
Test status
Simulation time 21859595782 ps
CPU time 14.39 seconds
Started May 02 02:09:19 PM PDT 24
Finished May 02 02:09:35 PM PDT 24
Peak memory 216376 kb
Host smart-f9745379-c979-4fc4-a56b-aea43d7b52dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155258510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3155258510
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2687086035
Short name T424
Test name
Test status
Simulation time 133332567 ps
CPU time 1.84 seconds
Started May 02 02:09:19 PM PDT 24
Finished May 02 02:09:22 PM PDT 24
Peak memory 216268 kb
Host smart-1c08c279-c4e8-4ef2-aca5-f07c53d2b84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687086035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2687086035
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.651922710
Short name T21
Test name
Test status
Simulation time 45201118 ps
CPU time 0.85 seconds
Started May 02 02:09:21 PM PDT 24
Finished May 02 02:09:23 PM PDT 24
Peak memory 205764 kb
Host smart-3207b3ba-7fe3-44fa-a643-00d49334e624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651922710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.651922710
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2218786573
Short name T325
Test name
Test status
Simulation time 1420351127 ps
CPU time 2.96 seconds
Started May 02 02:09:21 PM PDT 24
Finished May 02 02:09:25 PM PDT 24
Peak memory 220812 kb
Host smart-9cd78703-c96c-4429-a504-81b7cbfcd86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218786573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2218786573
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2239009189
Short name T174
Test name
Test status
Simulation time 123350330 ps
CPU time 0.73 seconds
Started May 02 02:09:26 PM PDT 24
Finished May 02 02:09:28 PM PDT 24
Peak memory 205696 kb
Host smart-41333e9d-bbe1-45f0-a09e-d91266bbb282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239009189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2239009189
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1540493481
Short name T530
Test name
Test status
Simulation time 48984774 ps
CPU time 0.76 seconds
Started May 02 02:09:27 PM PDT 24
Finished May 02 02:09:30 PM PDT 24
Peak memory 205572 kb
Host smart-2db339a8-a006-4fb9-a87c-4469e0bdc98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540493481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1540493481
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3799982128
Short name T456
Test name
Test status
Simulation time 179412323 ps
CPU time 2.79 seconds
Started May 02 02:09:28 PM PDT 24
Finished May 02 02:09:32 PM PDT 24
Peak memory 222696 kb
Host smart-46636503-396e-408d-803a-dcf2e6eae0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799982128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3799982128
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2473008915
Short name T5
Test name
Test status
Simulation time 37145833 ps
CPU time 2.33 seconds
Started May 02 02:09:28 PM PDT 24
Finished May 02 02:09:32 PM PDT 24
Peak memory 222888 kb
Host smart-a639564a-a890-4ead-ae12-1ff6f670a8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473008915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2473008915
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1274169878
Short name T198
Test name
Test status
Simulation time 15858032758 ps
CPU time 20.16 seconds
Started May 02 02:09:27 PM PDT 24
Finished May 02 02:09:49 PM PDT 24
Peak memory 232488 kb
Host smart-73caa71b-0c7c-4b5a-9b64-7bcdb39d2ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274169878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1274169878
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2587883928
Short name T88
Test name
Test status
Simulation time 1633389241 ps
CPU time 8.47 seconds
Started May 02 02:09:27 PM PDT 24
Finished May 02 02:09:38 PM PDT 24
Peak memory 223072 kb
Host smart-8c0168d2-6410-471b-9959-504c26f3d741
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2587883928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2587883928
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2779177682
Short name T20
Test name
Test status
Simulation time 51626971 ps
CPU time 0.99 seconds
Started May 02 02:09:28 PM PDT 24
Finished May 02 02:09:30 PM PDT 24
Peak memory 207116 kb
Host smart-a8e6c89c-5190-48eb-bfcb-19bb7a5152b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779177682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2779177682
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.458243869
Short name T416
Test name
Test status
Simulation time 4077516387 ps
CPU time 14.82 seconds
Started May 02 02:09:29 PM PDT 24
Finished May 02 02:09:45 PM PDT 24
Peak memory 216440 kb
Host smart-24ffbb1f-f427-4432-a88a-7159d3e242e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458243869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.458243869
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.328482695
Short name T559
Test name
Test status
Simulation time 557702102 ps
CPU time 2.91 seconds
Started May 02 02:09:26 PM PDT 24
Finished May 02 02:09:31 PM PDT 24
Peak memory 216248 kb
Host smart-191f1e3e-2cc9-4e4c-93dd-c83033ea5288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328482695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.328482695
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2195302435
Short name T62
Test name
Test status
Simulation time 82761973 ps
CPU time 1.32 seconds
Started May 02 02:09:29 PM PDT 24
Finished May 02 02:09:31 PM PDT 24
Peak memory 216260 kb
Host smart-733c631e-511e-4fbb-90c5-135e68660763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195302435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2195302435
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1454123205
Short name T14
Test name
Test status
Simulation time 176807129 ps
CPU time 1.07 seconds
Started May 02 02:09:27 PM PDT 24
Finished May 02 02:09:29 PM PDT 24
Peak memory 205800 kb
Host smart-c609a297-67fa-4e9e-b50b-bf2aba9a8770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454123205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1454123205
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.238430752
Short name T699
Test name
Test status
Simulation time 42105858 ps
CPU time 0.75 seconds
Started May 02 02:09:33 PM PDT 24
Finished May 02 02:09:35 PM PDT 24
Peak memory 205436 kb
Host smart-efc5af74-da51-4d12-8def-f04a0d186f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238430752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.238430752
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3700455737
Short name T593
Test name
Test status
Simulation time 21491515 ps
CPU time 0.84 seconds
Started May 02 02:09:27 PM PDT 24
Finished May 02 02:09:29 PM PDT 24
Peak memory 206624 kb
Host smart-ed469af7-a4e3-4d59-8886-3af4bef33249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700455737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3700455737
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3758733034
Short name T469
Test name
Test status
Simulation time 502326076 ps
CPU time 4.49 seconds
Started May 02 02:09:38 PM PDT 24
Finished May 02 02:09:44 PM PDT 24
Peak memory 219180 kb
Host smart-2651c969-ea09-4cad-abba-86a74d103a8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3758733034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3758733034
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.816530511
Short name T404
Test name
Test status
Simulation time 1743304254 ps
CPU time 20.09 seconds
Started May 02 02:09:30 PM PDT 24
Finished May 02 02:09:51 PM PDT 24
Peak memory 216164 kb
Host smart-9969898d-59e7-4726-99a8-865c017654fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816530511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.816530511
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1717090706
Short name T600
Test name
Test status
Simulation time 16191492753 ps
CPU time 13.75 seconds
Started May 02 02:09:29 PM PDT 24
Finished May 02 02:09:44 PM PDT 24
Peak memory 216360 kb
Host smart-5e229d74-e342-4d8e-9a94-fa335179b2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717090706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1717090706
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.217591378
Short name T418
Test name
Test status
Simulation time 1120888534 ps
CPU time 4.22 seconds
Started May 02 02:09:36 PM PDT 24
Finished May 02 02:09:42 PM PDT 24
Peak memory 216388 kb
Host smart-043e29a8-1f9c-4ab6-94ee-37f4a8af3ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217591378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.217591378
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2193913950
Short name T108
Test name
Test status
Simulation time 178263044 ps
CPU time 1.07 seconds
Started May 02 02:09:35 PM PDT 24
Finished May 02 02:09:37 PM PDT 24
Peak memory 206784 kb
Host smart-71904301-a134-452c-8048-22f65f91c5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193913950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2193913950
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2881640403
Short name T670
Test name
Test status
Simulation time 20145712 ps
CPU time 0.69 seconds
Started May 02 02:09:41 PM PDT 24
Finished May 02 02:09:43 PM PDT 24
Peak memory 205448 kb
Host smart-0a25a2f2-3bf5-4fb7-be21-141d1cc4244f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881640403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2881640403
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1652190545
Short name T588
Test name
Test status
Simulation time 589104389 ps
CPU time 3.34 seconds
Started May 02 02:09:37 PM PDT 24
Finished May 02 02:09:42 PM PDT 24
Peak memory 219040 kb
Host smart-8884a84e-eecb-4503-99ba-578a799516de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652190545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1652190545
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1187095559
Short name T613
Test name
Test status
Simulation time 63159251 ps
CPU time 0.74 seconds
Started May 02 02:09:36 PM PDT 24
Finished May 02 02:09:38 PM PDT 24
Peak memory 205992 kb
Host smart-797f416d-6130-4d75-b794-1f87e842afaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187095559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1187095559
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.456155062
Short name T650
Test name
Test status
Simulation time 4093550436 ps
CPU time 43.04 seconds
Started May 02 02:09:39 PM PDT 24
Finished May 02 02:10:23 PM PDT 24
Peak memory 235788 kb
Host smart-4dc90ca1-84d9-4334-95a0-ff12f0459029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456155062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.456155062
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3380611454
Short name T11
Test name
Test status
Simulation time 6451668926 ps
CPU time 19.8 seconds
Started May 02 02:09:33 PM PDT 24
Finished May 02 02:09:54 PM PDT 24
Peak memory 226928 kb
Host smart-e84fb547-2029-4e1d-8534-e40f6e5e2621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380611454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3380611454
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3933875771
Short name T505
Test name
Test status
Simulation time 6999248534 ps
CPU time 10.71 seconds
Started May 02 02:09:42 PM PDT 24
Finished May 02 02:09:54 PM PDT 24
Peak memory 223000 kb
Host smart-cb65aa7a-540f-4323-bb3b-7b2e4dd0f95f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3933875771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3933875771
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.483207957
Short name T490
Test name
Test status
Simulation time 1740220385 ps
CPU time 5.42 seconds
Started May 02 02:09:43 PM PDT 24
Finished May 02 02:09:51 PM PDT 24
Peak memory 216340 kb
Host smart-c1a468f0-aa5f-413b-a34d-33ae9808dc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483207957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.483207957
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3322432883
Short name T544
Test name
Test status
Simulation time 1023015200 ps
CPU time 3.15 seconds
Started May 02 02:09:34 PM PDT 24
Finished May 02 02:09:38 PM PDT 24
Peak memory 216280 kb
Host smart-8e1c9c26-85d5-4503-99a8-164e89b1a652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322432883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3322432883
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3078915631
Short name T727
Test name
Test status
Simulation time 752400019 ps
CPU time 0.94 seconds
Started May 02 02:09:38 PM PDT 24
Finished May 02 02:09:40 PM PDT 24
Peak memory 206800 kb
Host smart-261044da-c7eb-49bd-b3be-60b6fe7d4131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078915631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3078915631
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3989781798
Short name T652
Test name
Test status
Simulation time 4082605875 ps
CPU time 10.92 seconds
Started May 02 02:09:38 PM PDT 24
Finished May 02 02:09:50 PM PDT 24
Peak memory 224472 kb
Host smart-1274a964-68c0-4b7a-b0a2-d43231e1c11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989781798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3989781798
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4098895277
Short name T703
Test name
Test status
Simulation time 12799093 ps
CPU time 0.72 seconds
Started May 02 02:06:58 PM PDT 24
Finished May 02 02:07:01 PM PDT 24
Peak memory 205408 kb
Host smart-8e34748e-884d-4e3d-852e-9de4144d375b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098895277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
098895277
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1050364082
Short name T713
Test name
Test status
Simulation time 300077284 ps
CPU time 5.99 seconds
Started May 02 02:06:53 PM PDT 24
Finished May 02 02:07:00 PM PDT 24
Peak memory 218740 kb
Host smart-59196a8f-c18d-4c8e-b898-dcd45ff4f1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050364082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1050364082
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.758813148
Short name T172
Test name
Test status
Simulation time 51673777 ps
CPU time 0.77 seconds
Started May 02 02:06:50 PM PDT 24
Finished May 02 02:06:52 PM PDT 24
Peak memory 206696 kb
Host smart-6e990c14-d899-4431-95c2-488bbb8cd415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758813148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.758813148
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1321661071
Short name T374
Test name
Test status
Simulation time 1028598056 ps
CPU time 7.35 seconds
Started May 02 02:06:57 PM PDT 24
Finished May 02 02:07:06 PM PDT 24
Peak memory 224428 kb
Host smart-1bbfff67-588d-4698-9842-ab819349c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321661071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1321661071
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2913823674
Short name T46
Test name
Test status
Simulation time 1216676701 ps
CPU time 9.19 seconds
Started May 02 02:06:49 PM PDT 24
Finished May 02 02:06:59 PM PDT 24
Peak memory 232484 kb
Host smart-16250fe8-1523-442a-859e-229dd9d3caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913823674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2913823674
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.647991355
Short name T336
Test name
Test status
Simulation time 3967599778 ps
CPU time 10.03 seconds
Started May 02 02:06:51 PM PDT 24
Finished May 02 02:07:02 PM PDT 24
Peak memory 239832 kb
Host smart-8aa4ea58-343f-4619-98ce-906404496c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647991355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.647991355
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2910533268
Short name T2
Test name
Test status
Simulation time 774873115 ps
CPU time 7.46 seconds
Started May 02 02:06:56 PM PDT 24
Finished May 02 02:07:05 PM PDT 24
Peak memory 223284 kb
Host smart-21e59990-047b-4333-acbc-2b623e3334e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2910533268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2910533268
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2251556805
Short name T50
Test name
Test status
Simulation time 124688359 ps
CPU time 0.96 seconds
Started May 02 02:06:55 PM PDT 24
Finished May 02 02:06:58 PM PDT 24
Peak memory 235048 kb
Host smart-418bf21b-ff43-412e-94bc-68a2490e0ad7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251556805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2251556805
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1718138778
Short name T641
Test name
Test status
Simulation time 1787423928 ps
CPU time 6.14 seconds
Started May 02 02:06:49 PM PDT 24
Finished May 02 02:06:56 PM PDT 24
Peak memory 216324 kb
Host smart-335ea64a-1783-437b-a110-c853d35ebfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718138778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1718138778
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3973405756
Short name T688
Test name
Test status
Simulation time 502640533 ps
CPU time 8.18 seconds
Started May 02 02:06:48 PM PDT 24
Finished May 02 02:06:57 PM PDT 24
Peak memory 216400 kb
Host smart-b8f2cd04-f08b-4215-8a33-10a6cda9f8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973405756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3973405756
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3665340018
Short name T496
Test name
Test status
Simulation time 38020113 ps
CPU time 0.87 seconds
Started May 02 02:06:49 PM PDT 24
Finished May 02 02:06:51 PM PDT 24
Peak memory 206864 kb
Host smart-63713666-cd13-4a89-b9fd-add1006a6df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665340018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3665340018
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1926832021
Short name T235
Test name
Test status
Simulation time 42731542 ps
CPU time 2.71 seconds
Started May 02 02:06:59 PM PDT 24
Finished May 02 02:07:04 PM PDT 24
Peak memory 222848 kb
Host smart-b776bbe5-ca7f-4cc5-b630-5f3fc2c94487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926832021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1926832021
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3659997356
Short name T678
Test name
Test status
Simulation time 73069510 ps
CPU time 0.7 seconds
Started May 02 02:09:51 PM PDT 24
Finished May 02 02:09:54 PM PDT 24
Peak memory 205396 kb
Host smart-a67a5015-bfcd-4909-bc99-bcc700257a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659997356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3659997356
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1175909442
Short name T622
Test name
Test status
Simulation time 62723733 ps
CPU time 0.78 seconds
Started May 02 02:09:40 PM PDT 24
Finished May 02 02:09:43 PM PDT 24
Peak memory 205932 kb
Host smart-7f6c3c51-8bad-44cc-91b9-9ca9aa1b10fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175909442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1175909442
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3531801530
Short name T155
Test name
Test status
Simulation time 1142872489 ps
CPU time 24.6 seconds
Started May 02 02:09:52 PM PDT 24
Finished May 02 02:10:18 PM PDT 24
Peak memory 248440 kb
Host smart-0d01e64e-9a0c-4c83-a5be-e11df5ede614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531801530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3531801530
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1541411089
Short name T177
Test name
Test status
Simulation time 535095746 ps
CPU time 3.39 seconds
Started May 02 02:09:51 PM PDT 24
Finished May 02 02:09:55 PM PDT 24
Peak memory 222804 kb
Host smart-6ae413c4-8c2d-4570-92e4-a30694a295fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541411089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1541411089
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3750941062
Short name T269
Test name
Test status
Simulation time 3846443973 ps
CPU time 11.95 seconds
Started May 02 02:09:53 PM PDT 24
Finished May 02 02:10:06 PM PDT 24
Peak memory 222840 kb
Host smart-61152fff-0b2e-42e9-87cf-5b1d58e4c645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750941062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3750941062
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.386625290
Short name T83
Test name
Test status
Simulation time 10920847705 ps
CPU time 31.63 seconds
Started May 02 02:09:43 PM PDT 24
Finished May 02 02:10:17 PM PDT 24
Peak memory 234140 kb
Host smart-9d3abc62-6739-4f43-a1b0-e4d52da28dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386625290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.386625290
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1516985687
Short name T684
Test name
Test status
Simulation time 172825771 ps
CPU time 4.67 seconds
Started May 02 02:09:52 PM PDT 24
Finished May 02 02:09:59 PM PDT 24
Peak memory 222888 kb
Host smart-1cfcd1e9-a7a9-423c-a1c1-d024d98abc5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1516985687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1516985687
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.428290121
Short name T643
Test name
Test status
Simulation time 184571727092 ps
CPU time 60.1 seconds
Started May 02 02:09:42 PM PDT 24
Finished May 02 02:10:45 PM PDT 24
Peak memory 216396 kb
Host smart-2564c04d-8f36-4716-ae09-17358f0ee8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428290121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.428290121
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3251008805
Short name T709
Test name
Test status
Simulation time 2131798329 ps
CPU time 4.55 seconds
Started May 02 02:09:43 PM PDT 24
Finished May 02 02:09:49 PM PDT 24
Peak memory 216312 kb
Host smart-62a57b8f-e82c-47da-93e5-ec44f7e3834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251008805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3251008805
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.639537999
Short name T421
Test name
Test status
Simulation time 23782273 ps
CPU time 0.91 seconds
Started May 02 02:09:43 PM PDT 24
Finished May 02 02:09:46 PM PDT 24
Peak memory 206444 kb
Host smart-cfa47771-b577-4277-bd7a-89c7542a5b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639537999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.639537999
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2364534369
Short name T610
Test name
Test status
Simulation time 161469013 ps
CPU time 1.01 seconds
Started May 02 02:09:42 PM PDT 24
Finished May 02 02:09:45 PM PDT 24
Peak memory 206796 kb
Host smart-ad71e818-6e1a-423b-90ef-74303429dc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364534369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2364534369
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3413667334
Short name T438
Test name
Test status
Simulation time 15034679 ps
CPU time 0.74 seconds
Started May 02 02:10:03 PM PDT 24
Finished May 02 02:10:06 PM PDT 24
Peak memory 205392 kb
Host smart-c211e5d0-c2a3-4a43-9722-c5729a0dee29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413667334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3413667334
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3391686572
Short name T243
Test name
Test status
Simulation time 1216432973 ps
CPU time 5.96 seconds
Started May 02 02:09:51 PM PDT 24
Finished May 02 02:09:59 PM PDT 24
Peak memory 218932 kb
Host smart-c139a4c7-b3be-4b82-b46f-deaa576701cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391686572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3391686572
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3906199571
Short name T596
Test name
Test status
Simulation time 17689705 ps
CPU time 0.76 seconds
Started May 02 02:10:06 PM PDT 24
Finished May 02 02:10:09 PM PDT 24
Peak memory 205976 kb
Host smart-6f763e71-4858-4d8a-9cd6-27c0e7143b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906199571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3906199571
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.998715511
Short name T538
Test name
Test status
Simulation time 5785696532 ps
CPU time 16.94 seconds
Started May 02 02:09:51 PM PDT 24
Finished May 02 02:10:09 PM PDT 24
Peak memory 236688 kb
Host smart-c4e099fc-793b-4da9-89e6-b717d6b7db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998715511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.998715511
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1873224427
Short name T319
Test name
Test status
Simulation time 9025303307 ps
CPU time 22.46 seconds
Started May 02 02:09:51 PM PDT 24
Finished May 02 02:10:15 PM PDT 24
Peak memory 217424 kb
Host smart-80af5ffe-8b62-47db-9ec2-87c73f01b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873224427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1873224427
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4002944921
Short name T173
Test name
Test status
Simulation time 2987781389 ps
CPU time 9.01 seconds
Started May 02 02:10:02 PM PDT 24
Finished May 02 02:10:13 PM PDT 24
Peak memory 222980 kb
Host smart-0b64d7c4-2724-42e7-90a1-40cd2d699f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002944921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4002944921
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3897448687
Short name T629
Test name
Test status
Simulation time 1773015008 ps
CPU time 7.73 seconds
Started May 02 02:09:52 PM PDT 24
Finished May 02 02:10:01 PM PDT 24
Peak memory 221828 kb
Host smart-0667edb0-d205-4cf5-86dc-9ae3e6e1fff2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3897448687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3897448687
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3008910459
Short name T639
Test name
Test status
Simulation time 5948191399 ps
CPU time 34.8 seconds
Started May 02 02:09:53 PM PDT 24
Finished May 02 02:10:29 PM PDT 24
Peak memory 216340 kb
Host smart-b4c9e07f-82f8-4068-8939-ae9aea1d1d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008910459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3008910459
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.863493621
Short name T685
Test name
Test status
Simulation time 10618270670 ps
CPU time 8.61 seconds
Started May 02 02:09:53 PM PDT 24
Finished May 02 02:10:03 PM PDT 24
Peak memory 216320 kb
Host smart-817a1bc2-9deb-4555-8790-86b52a56739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863493621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.863493621
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1618856635
Short name T415
Test name
Test status
Simulation time 13243759 ps
CPU time 0.79 seconds
Started May 02 02:09:52 PM PDT 24
Finished May 02 02:09:54 PM PDT 24
Peak memory 205832 kb
Host smart-4ec91161-11c0-42f3-b4e2-72304f45fef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618856635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1618856635
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2159336948
Short name T589
Test name
Test status
Simulation time 199237263 ps
CPU time 1.06 seconds
Started May 02 02:09:53 PM PDT 24
Finished May 02 02:09:55 PM PDT 24
Peak memory 206860 kb
Host smart-bb22d6e7-4c49-4c93-bc51-e447e3d3ec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159336948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2159336948
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3527811289
Short name T668
Test name
Test status
Simulation time 59665083 ps
CPU time 0.69 seconds
Started May 02 02:10:04 PM PDT 24
Finished May 02 02:10:07 PM PDT 24
Peak memory 205696 kb
Host smart-76fcc46c-424e-434a-8f6c-c51e50da24e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527811289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3527811289
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3586625281
Short name T24
Test name
Test status
Simulation time 843803051 ps
CPU time 4.33 seconds
Started May 02 02:10:03 PM PDT 24
Finished May 02 02:10:10 PM PDT 24
Peak memory 218748 kb
Host smart-9c331484-255c-4b56-85d9-424ad003bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586625281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3586625281
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1483167393
Short name T495
Test name
Test status
Simulation time 29361990 ps
CPU time 0.78 seconds
Started May 02 02:10:04 PM PDT 24
Finished May 02 02:10:07 PM PDT 24
Peak memory 206684 kb
Host smart-0ce50627-f581-4031-ab42-9fe34ea3b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483167393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1483167393
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3261772000
Short name T317
Test name
Test status
Simulation time 9322442995 ps
CPU time 25.85 seconds
Started May 02 02:10:04 PM PDT 24
Finished May 02 02:10:33 PM PDT 24
Peak memory 240964 kb
Host smart-e97d3222-75fc-41da-ae77-67fd5011ffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261772000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3261772000
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4025680160
Short name T202
Test name
Test status
Simulation time 364478423 ps
CPU time 6.68 seconds
Started May 02 02:10:04 PM PDT 24
Finished May 02 02:10:13 PM PDT 24
Peak memory 224380 kb
Host smart-6be50e75-73e7-43cd-ad87-ce00837a8854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025680160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4025680160
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3601650439
Short name T249
Test name
Test status
Simulation time 4085257268 ps
CPU time 35.18 seconds
Started May 02 02:10:05 PM PDT 24
Finished May 02 02:10:42 PM PDT 24
Peak memory 235152 kb
Host smart-dd7b5ad1-2100-43c8-b482-5ffb3447026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601650439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3601650439
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3465347956
Short name T245
Test name
Test status
Simulation time 132778384 ps
CPU time 2.78 seconds
Started May 02 02:10:05 PM PDT 24
Finished May 02 02:10:11 PM PDT 24
Peak memory 222404 kb
Host smart-5275ad1d-6b0a-4c89-bbd1-610723d5e60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465347956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3465347956
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2650999194
Short name T508
Test name
Test status
Simulation time 3164841554 ps
CPU time 5.67 seconds
Started May 02 02:10:04 PM PDT 24
Finished May 02 02:10:12 PM PDT 24
Peak memory 220504 kb
Host smart-034e6a2c-1bbf-44b0-9023-c14c2173212b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2650999194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2650999194
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2240873599
Short name T417
Test name
Test status
Simulation time 94832375427 ps
CPU time 73.34 seconds
Started May 02 02:10:04 PM PDT 24
Finished May 02 02:11:20 PM PDT 24
Peak memory 216392 kb
Host smart-069bc18f-47be-484f-86c5-067b9568526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240873599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2240873599
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1781594715
Short name T532
Test name
Test status
Simulation time 6708006905 ps
CPU time 22.18 seconds
Started May 02 02:10:03 PM PDT 24
Finished May 02 02:10:27 PM PDT 24
Peak memory 216408 kb
Host smart-59511a87-51c0-4df6-ad5f-ad2dd9345d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781594715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1781594715
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1127794477
Short name T521
Test name
Test status
Simulation time 185918956 ps
CPU time 3.89 seconds
Started May 02 02:10:08 PM PDT 24
Finished May 02 02:10:13 PM PDT 24
Peak memory 216328 kb
Host smart-fb5cedff-57c3-46d0-9507-54752d956bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127794477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1127794477
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3475258228
Short name T56
Test name
Test status
Simulation time 105301837 ps
CPU time 1.1 seconds
Started May 02 02:10:01 PM PDT 24
Finished May 02 02:10:04 PM PDT 24
Peak memory 206752 kb
Host smart-37d832f8-c0b2-4426-b5e8-63c4af415711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475258228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3475258228
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.818919863
Short name T229
Test name
Test status
Simulation time 5534460067 ps
CPU time 17.17 seconds
Started May 02 02:10:08 PM PDT 24
Finished May 02 02:10:27 PM PDT 24
Peak memory 217748 kb
Host smart-427e14f1-aafb-406e-8190-cda83572c4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818919863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.818919863
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2134996294
Short name T486
Test name
Test status
Simulation time 12957104 ps
CPU time 0.8 seconds
Started May 02 02:10:14 PM PDT 24
Finished May 02 02:10:16 PM PDT 24
Peak memory 205428 kb
Host smart-560058d0-261a-4319-961c-7a454a450dee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134996294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2134996294
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2424292147
Short name T217
Test name
Test status
Simulation time 103654848 ps
CPU time 2.89 seconds
Started May 02 02:10:14 PM PDT 24
Finished May 02 02:10:18 PM PDT 24
Peak memory 223004 kb
Host smart-fb2dfc42-85dc-42a9-9e1e-089a6edcd468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424292147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2424292147
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.814425308
Short name T494
Test name
Test status
Simulation time 112088382 ps
CPU time 0.75 seconds
Started May 02 02:10:03 PM PDT 24
Finished May 02 02:10:06 PM PDT 24
Peak memory 206700 kb
Host smart-2d72d326-fa0e-4c23-8d15-61b91df1e50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814425308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.814425308
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2913076298
Short name T377
Test name
Test status
Simulation time 8317855321 ps
CPU time 60.44 seconds
Started May 02 02:10:10 PM PDT 24
Finished May 02 02:11:12 PM PDT 24
Peak memory 239084 kb
Host smart-c91237fb-64ce-45d2-98e7-445bf0b030c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913076298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2913076298
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1398648694
Short name T236
Test name
Test status
Simulation time 498820982 ps
CPU time 2.6 seconds
Started May 02 02:10:14 PM PDT 24
Finished May 02 02:10:18 PM PDT 24
Peak memory 218616 kb
Host smart-c5de57bf-6bbd-4b89-9172-475a8a52073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398648694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1398648694
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1920152596
Short name T283
Test name
Test status
Simulation time 23676102081 ps
CPU time 15.53 seconds
Started May 02 02:10:03 PM PDT 24
Finished May 02 02:10:21 PM PDT 24
Peak memory 220880 kb
Host smart-43777b71-5940-4935-bdbe-2c5ca824aa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920152596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1920152596
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1380503458
Short name T535
Test name
Test status
Simulation time 2676700314 ps
CPU time 4.46 seconds
Started May 02 02:10:14 PM PDT 24
Finished May 02 02:10:20 PM PDT 24
Peak memory 219348 kb
Host smart-b2dd6235-7fe0-46e2-bd97-a3f6873b2052
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1380503458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1380503458
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2511056497
Short name T564
Test name
Test status
Simulation time 10465421076 ps
CPU time 24.07 seconds
Started May 02 02:10:03 PM PDT 24
Finished May 02 02:10:29 PM PDT 24
Peak memory 216300 kb
Host smart-5ee8762b-66f7-47da-8b15-3f698b6d18d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511056497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2511056497
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1020578768
Short name T673
Test name
Test status
Simulation time 17888514 ps
CPU time 0.84 seconds
Started May 02 02:10:05 PM PDT 24
Finished May 02 02:10:09 PM PDT 24
Peak memory 205768 kb
Host smart-b278ee4d-b232-4cc1-a481-c5ed3801366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020578768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1020578768
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.497719538
Short name T720
Test name
Test status
Simulation time 54505611 ps
CPU time 0.88 seconds
Started May 02 02:10:06 PM PDT 24
Finished May 02 02:10:09 PM PDT 24
Peak memory 206840 kb
Host smart-20259a23-4495-4dad-a330-6c0d105c80a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497719538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.497719538
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2317241281
Short name T369
Test name
Test status
Simulation time 23478432489 ps
CPU time 7.95 seconds
Started May 02 02:10:16 PM PDT 24
Finished May 02 02:10:26 PM PDT 24
Peak memory 224588 kb
Host smart-fa2ad736-e7b0-4c0f-9cd7-91fd800477f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317241281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2317241281
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3782170545
Short name T502
Test name
Test status
Simulation time 21017280 ps
CPU time 0.72 seconds
Started May 02 02:10:15 PM PDT 24
Finished May 02 02:10:17 PM PDT 24
Peak memory 204760 kb
Host smart-336161a4-227f-419f-abcc-b66e2f21c70b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782170545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3782170545
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3450731025
Short name T457
Test name
Test status
Simulation time 70928244 ps
CPU time 0.8 seconds
Started May 02 02:10:13 PM PDT 24
Finished May 02 02:10:15 PM PDT 24
Peak memory 206688 kb
Host smart-fd6a294d-c89a-433f-b168-87d9d24c69b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450731025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3450731025
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3830115934
Short name T186
Test name
Test status
Simulation time 7663525468 ps
CPU time 14.13 seconds
Started May 02 02:10:13 PM PDT 24
Finished May 02 02:10:28 PM PDT 24
Peak memory 222888 kb
Host smart-5427d691-f3b1-425d-bfb3-7459d4c46a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830115934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3830115934
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.304721985
Short name T6
Test name
Test status
Simulation time 99100174758 ps
CPU time 73.89 seconds
Started May 02 02:10:13 PM PDT 24
Finished May 02 02:11:28 PM PDT 24
Peak memory 229924 kb
Host smart-1b43aa02-7952-46dd-a925-98c97f87aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304721985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.304721985
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1601292943
Short name T190
Test name
Test status
Simulation time 14867366464 ps
CPU time 20.97 seconds
Started May 02 02:10:13 PM PDT 24
Finished May 02 02:10:35 PM PDT 24
Peak memory 230028 kb
Host smart-0d146379-b31e-4cad-9d39-86df657aa695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601292943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1601292943
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1465305914
Short name T580
Test name
Test status
Simulation time 802171947 ps
CPU time 8.7 seconds
Started May 02 02:10:14 PM PDT 24
Finished May 02 02:10:24 PM PDT 24
Peak memory 222504 kb
Host smart-913aff5a-30d8-4c0b-9c80-4e0cad56a8db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1465305914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1465305914
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2489369528
Short name T435
Test name
Test status
Simulation time 4916764859 ps
CPU time 6.1 seconds
Started May 02 02:10:15 PM PDT 24
Finished May 02 02:10:23 PM PDT 24
Peak memory 216420 kb
Host smart-fba24c71-ec10-4773-8762-573418417ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489369528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2489369528
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1488829637
Short name T425
Test name
Test status
Simulation time 2868378987 ps
CPU time 2.37 seconds
Started May 02 02:10:15 PM PDT 24
Finished May 02 02:10:19 PM PDT 24
Peak memory 216376 kb
Host smart-056f7cfb-9625-4825-8e8e-8ee2008e1db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488829637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1488829637
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3752715841
Short name T481
Test name
Test status
Simulation time 28726621 ps
CPU time 0.82 seconds
Started May 02 02:10:17 PM PDT 24
Finished May 02 02:10:19 PM PDT 24
Peak memory 205776 kb
Host smart-f6e9eab6-f9e0-49b0-8860-564125611bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752715841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3752715841
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.127427429
Short name T329
Test name
Test status
Simulation time 116353799 ps
CPU time 3.84 seconds
Started May 02 02:10:12 PM PDT 24
Finished May 02 02:10:16 PM PDT 24
Peak memory 222520 kb
Host smart-06a4eec1-18e6-4d83-9765-351de8c7b91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127427429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.127427429
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.910296974
Short name T513
Test name
Test status
Simulation time 44378780 ps
CPU time 0.73 seconds
Started May 02 02:10:23 PM PDT 24
Finished May 02 02:10:25 PM PDT 24
Peak memory 205732 kb
Host smart-6c7075f5-06b2-4c9b-9567-b82897a3a8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910296974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.910296974
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1066052846
Short name T576
Test name
Test status
Simulation time 108665351 ps
CPU time 0.75 seconds
Started May 02 02:10:15 PM PDT 24
Finished May 02 02:10:17 PM PDT 24
Peak memory 205628 kb
Host smart-d8b2739f-9599-4836-8fc5-8c6e002e3be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066052846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1066052846
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1149352454
Short name T285
Test name
Test status
Simulation time 1324221120 ps
CPU time 6.58 seconds
Started May 02 02:10:19 PM PDT 24
Finished May 02 02:10:26 PM PDT 24
Peak memory 224236 kb
Host smart-06eb125f-db4f-490d-b0e9-0fd9cbd555f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149352454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1149352454
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3728266908
Short name T268
Test name
Test status
Simulation time 440498235 ps
CPU time 8.18 seconds
Started May 02 02:10:14 PM PDT 24
Finished May 02 02:10:24 PM PDT 24
Peak memory 240404 kb
Host smart-287afafe-2cc7-4aa6-bad7-e3d99dc059dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728266908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3728266908
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.153987461
Short name T54
Test name
Test status
Simulation time 962043257 ps
CPU time 4.38 seconds
Started May 02 02:10:19 PM PDT 24
Finished May 02 02:10:24 PM PDT 24
Peak memory 220116 kb
Host smart-aea92d4f-e1bf-47cf-82b0-ccc47a14ae08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=153987461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.153987461
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2815358812
Short name T84
Test name
Test status
Simulation time 9014933735 ps
CPU time 45.63 seconds
Started May 02 02:10:15 PM PDT 24
Finished May 02 02:11:02 PM PDT 24
Peak memory 216428 kb
Host smart-78a26ce9-441e-494e-830a-a991a45dd08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815358812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2815358812
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.207582776
Short name T437
Test name
Test status
Simulation time 3556299175 ps
CPU time 7.89 seconds
Started May 02 02:10:15 PM PDT 24
Finished May 02 02:10:24 PM PDT 24
Peak memory 216312 kb
Host smart-7376f17e-d15a-4767-a0bf-9cd863630d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207582776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.207582776
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3237137427
Short name T646
Test name
Test status
Simulation time 145452381 ps
CPU time 5.36 seconds
Started May 02 02:10:15 PM PDT 24
Finished May 02 02:10:21 PM PDT 24
Peak memory 216332 kb
Host smart-9a8a2687-9eef-4789-8423-25c8f31d8e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237137427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3237137427
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.258095117
Short name T679
Test name
Test status
Simulation time 122884553 ps
CPU time 0.9 seconds
Started May 02 02:10:14 PM PDT 24
Finished May 02 02:10:16 PM PDT 24
Peak memory 206776 kb
Host smart-4a53d63b-ba66-4385-9259-f045d3d67d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258095117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.258095117
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2391399961
Short name T474
Test name
Test status
Simulation time 11147771 ps
CPU time 0.69 seconds
Started May 02 02:10:29 PM PDT 24
Finished May 02 02:10:31 PM PDT 24
Peak memory 205416 kb
Host smart-80e81915-a7f1-4531-9bb6-d283d36dacca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391399961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2391399961
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1252371959
Short name T577
Test name
Test status
Simulation time 30885533 ps
CPU time 0.84 seconds
Started May 02 02:10:21 PM PDT 24
Finished May 02 02:10:23 PM PDT 24
Peak memory 206704 kb
Host smart-1579c774-354b-4f5b-b491-e36cd529f1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252371959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1252371959
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.955876294
Short name T380
Test name
Test status
Simulation time 20553090080 ps
CPU time 32.9 seconds
Started May 02 02:10:29 PM PDT 24
Finished May 02 02:11:03 PM PDT 24
Peak memory 240984 kb
Host smart-51c5274e-d4ce-4f72-85c4-1dbcd06ba87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955876294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.955876294
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.566316453
Short name T654
Test name
Test status
Simulation time 345767384 ps
CPU time 5.01 seconds
Started May 02 02:10:30 PM PDT 24
Finished May 02 02:10:36 PM PDT 24
Peak memory 222928 kb
Host smart-0cc21b85-d123-42e9-b12c-e71967bb159f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=566316453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.566316453
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1020809718
Short name T612
Test name
Test status
Simulation time 2930682031 ps
CPU time 36.62 seconds
Started May 02 02:10:24 PM PDT 24
Finished May 02 02:11:01 PM PDT 24
Peak memory 221172 kb
Host smart-e2d25b16-1909-437e-9090-f2ef9ffe7744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020809718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1020809718
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.481800522
Short name T658
Test name
Test status
Simulation time 5495622901 ps
CPU time 9.35 seconds
Started May 02 02:10:23 PM PDT 24
Finished May 02 02:10:34 PM PDT 24
Peak memory 216388 kb
Host smart-64df05f0-52c1-4291-aa83-1068e13b54f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481800522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.481800522
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1201778071
Short name T563
Test name
Test status
Simulation time 1099943467 ps
CPU time 3.88 seconds
Started May 02 02:10:18 PM PDT 24
Finished May 02 02:10:23 PM PDT 24
Peak memory 216304 kb
Host smart-432709ad-2c35-451f-b596-dc8194c90544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201778071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1201778071
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2668313186
Short name T57
Test name
Test status
Simulation time 34382092 ps
CPU time 0.86 seconds
Started May 02 02:10:25 PM PDT 24
Finished May 02 02:10:27 PM PDT 24
Peak memory 206344 kb
Host smart-7d23b28f-f345-4c99-8ebd-23b4dcb7804b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668313186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2668313186
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2301376735
Short name T175
Test name
Test status
Simulation time 20426455817 ps
CPU time 17.56 seconds
Started May 02 02:10:22 PM PDT 24
Finished May 02 02:10:40 PM PDT 24
Peak memory 230248 kb
Host smart-39cfc778-eb5e-444b-bf8e-b8d33c621484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301376735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2301376735
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3908017511
Short name T479
Test name
Test status
Simulation time 13167333 ps
CPU time 0.73 seconds
Started May 02 02:10:35 PM PDT 24
Finished May 02 02:10:37 PM PDT 24
Peak memory 205400 kb
Host smart-8e1263b5-4e71-4b79-bbc4-9fad6410fd29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908017511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3908017511
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2421320192
Short name T274
Test name
Test status
Simulation time 1987344221 ps
CPU time 12.04 seconds
Started May 02 02:10:34 PM PDT 24
Finished May 02 02:10:47 PM PDT 24
Peak memory 223600 kb
Host smart-df1dd5d2-172a-439a-81ce-9a79da899ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421320192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2421320192
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1331857102
Short name T572
Test name
Test status
Simulation time 38366139 ps
CPU time 0.78 seconds
Started May 02 02:10:37 PM PDT 24
Finished May 02 02:10:38 PM PDT 24
Peak memory 206680 kb
Host smart-f9f19bb1-0fe4-4c4d-a6d3-f49169d108a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331857102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1331857102
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.443022653
Short name T312
Test name
Test status
Simulation time 387941396 ps
CPU time 15.55 seconds
Started May 02 02:10:38 PM PDT 24
Finished May 02 02:10:55 PM PDT 24
Peak memory 234856 kb
Host smart-668b1551-3396-4cd4-86c8-0c85e4ec1763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443022653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.443022653
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1167331633
Short name T224
Test name
Test status
Simulation time 934499372 ps
CPU time 4.36 seconds
Started May 02 02:10:29 PM PDT 24
Finished May 02 02:10:34 PM PDT 24
Peak memory 223372 kb
Host smart-e6d7be21-5846-42e7-a0b6-ebc4abecfdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167331633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1167331633
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3484288085
Short name T250
Test name
Test status
Simulation time 4409104624 ps
CPU time 17.71 seconds
Started May 02 02:10:33 PM PDT 24
Finished May 02 02:10:51 PM PDT 24
Peak memory 237520 kb
Host smart-1b8db807-1fad-4ee3-8284-031dedad906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484288085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3484288085
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4140917131
Short name T361
Test name
Test status
Simulation time 3792770724 ps
CPU time 15.71 seconds
Started May 02 02:10:36 PM PDT 24
Finished May 02 02:10:53 PM PDT 24
Peak memory 222916 kb
Host smart-42d29cfc-1a7f-4e94-badf-58296158b192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140917131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4140917131
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3025769979
Short name T333
Test name
Test status
Simulation time 2542884257 ps
CPU time 12.42 seconds
Started May 02 02:10:33 PM PDT 24
Finished May 02 02:10:46 PM PDT 24
Peak memory 229360 kb
Host smart-ba96dcd5-6e29-49a3-b446-f6d1bcc11c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025769979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3025769979
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3327718396
Short name T702
Test name
Test status
Simulation time 904032744 ps
CPU time 3.21 seconds
Started May 02 02:10:35 PM PDT 24
Finished May 02 02:10:39 PM PDT 24
Peak memory 219288 kb
Host smart-b252730f-4f45-4738-9dbb-93712a845bea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3327718396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3327718396
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2073819846
Short name T64
Test name
Test status
Simulation time 186227166 ps
CPU time 2.97 seconds
Started May 02 02:10:30 PM PDT 24
Finished May 02 02:10:34 PM PDT 24
Peak memory 216488 kb
Host smart-d1caa90a-8483-4744-8263-456194075d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073819846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2073819846
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1500214972
Short name T682
Test name
Test status
Simulation time 919676416 ps
CPU time 5.22 seconds
Started May 02 02:10:30 PM PDT 24
Finished May 02 02:10:36 PM PDT 24
Peak memory 216332 kb
Host smart-ec82a6d9-fef2-42fa-8940-215425476949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500214972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1500214972
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.796311167
Short name T426
Test name
Test status
Simulation time 85814452 ps
CPU time 2.08 seconds
Started May 02 02:10:29 PM PDT 24
Finished May 02 02:10:32 PM PDT 24
Peak memory 216216 kb
Host smart-e26ce597-1311-45f2-b5d6-1e9a7447dd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796311167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.796311167
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.157521635
Short name T534
Test name
Test status
Simulation time 117553329 ps
CPU time 1.11 seconds
Started May 02 02:10:29 PM PDT 24
Finished May 02 02:10:31 PM PDT 24
Peak memory 206832 kb
Host smart-26bf15be-6eb4-4bed-80a0-99c147677349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157521635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.157521635
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2943172972
Short name T598
Test name
Test status
Simulation time 45731993 ps
CPU time 0.72 seconds
Started May 02 02:10:41 PM PDT 24
Finished May 02 02:10:43 PM PDT 24
Peak memory 205752 kb
Host smart-a0610a66-743f-4ab4-98b8-22a2ed19ed3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943172972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2943172972
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.60290744
Short name T440
Test name
Test status
Simulation time 111004167 ps
CPU time 0.75 seconds
Started May 02 02:10:35 PM PDT 24
Finished May 02 02:10:37 PM PDT 24
Peak memory 206584 kb
Host smart-ad418d30-6d9d-4048-8d41-8855b6995d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60290744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.60290744
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1274455618
Short name T376
Test name
Test status
Simulation time 512372813 ps
CPU time 14.38 seconds
Started May 02 02:10:41 PM PDT 24
Finished May 02 02:10:56 PM PDT 24
Peak memory 249392 kb
Host smart-d2f5e514-0a92-4063-b272-7dbdaf7c2933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274455618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1274455618
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3636580070
Short name T7
Test name
Test status
Simulation time 608658678 ps
CPU time 7.27 seconds
Started May 02 02:10:42 PM PDT 24
Finished May 02 02:10:50 PM PDT 24
Peak memory 220356 kb
Host smart-08ded2f6-7817-44cf-8a7e-bb467bda386d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3636580070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3636580070
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.536268411
Short name T543
Test name
Test status
Simulation time 7165701400 ps
CPU time 7.4 seconds
Started May 02 02:10:35 PM PDT 24
Finished May 02 02:10:44 PM PDT 24
Peak memory 216236 kb
Host smart-db094b4e-34bf-4698-9fc2-73833f4f9036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536268411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.536268411
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1184302814
Short name T12
Test name
Test status
Simulation time 983604288 ps
CPU time 13.87 seconds
Started May 02 02:10:35 PM PDT 24
Finished May 02 02:10:50 PM PDT 24
Peak memory 216212 kb
Host smart-cae32d05-ab03-4d47-b0c9-fd8da3278258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184302814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1184302814
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2252868580
Short name T531
Test name
Test status
Simulation time 68181554 ps
CPU time 0.9 seconds
Started May 02 02:10:35 PM PDT 24
Finished May 02 02:10:37 PM PDT 24
Peak memory 205780 kb
Host smart-97cda799-841a-4abd-b27b-d8b1831931d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252868580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2252868580
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1462002772
Short name T453
Test name
Test status
Simulation time 21150384 ps
CPU time 0.77 seconds
Started May 02 02:10:52 PM PDT 24
Finished May 02 02:10:54 PM PDT 24
Peak memory 205420 kb
Host smart-c39ac738-dead-4979-b9dc-548c23232500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462002772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1462002772
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3192118356
Short name T605
Test name
Test status
Simulation time 36504446 ps
CPU time 0.75 seconds
Started May 02 02:10:40 PM PDT 24
Finished May 02 02:10:43 PM PDT 24
Peak memory 206672 kb
Host smart-b8639b95-8fc7-4384-a534-61523f0d2c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192118356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3192118356
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.602809555
Short name T315
Test name
Test status
Simulation time 21024360392 ps
CPU time 83.88 seconds
Started May 02 02:10:53 PM PDT 24
Finished May 02 02:12:18 PM PDT 24
Peak memory 240844 kb
Host smart-91e4ec81-03e8-4a02-aa0f-6d1c2d57197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602809555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.602809555
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2382295681
Short name T196
Test name
Test status
Simulation time 1994139572 ps
CPU time 11.53 seconds
Started May 02 02:10:52 PM PDT 24
Finished May 02 02:11:05 PM PDT 24
Peak memory 218464 kb
Host smart-6d792403-31d1-4b29-a520-d93afbcf5645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382295681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2382295681
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.329450141
Short name T120
Test name
Test status
Simulation time 2835944578 ps
CPU time 37.93 seconds
Started May 02 02:10:54 PM PDT 24
Finished May 02 02:11:33 PM PDT 24
Peak memory 230012 kb
Host smart-e62ce9bb-81ea-4266-973b-71cfa3d6195a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329450141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.329450141
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.937883980
Short name T337
Test name
Test status
Simulation time 8834763032 ps
CPU time 17.67 seconds
Started May 02 02:10:50 PM PDT 24
Finished May 02 02:11:09 PM PDT 24
Peak memory 232948 kb
Host smart-ce94440b-6b3e-49be-ad16-1489a2516c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937883980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.937883980
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1164426697
Short name T574
Test name
Test status
Simulation time 1779914801 ps
CPU time 20.16 seconds
Started May 02 02:10:51 PM PDT 24
Finished May 02 02:11:12 PM PDT 24
Peak memory 220528 kb
Host smart-0359c972-6fd4-4c7a-b665-c4565d8e36d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1164426697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1164426697
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4197294911
Short name T476
Test name
Test status
Simulation time 193448148 ps
CPU time 1.85 seconds
Started May 02 02:10:51 PM PDT 24
Finished May 02 02:10:54 PM PDT 24
Peak memory 207048 kb
Host smart-70520346-73b4-4ca6-9952-689cce7e7883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197294911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4197294911
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1704833368
Short name T422
Test name
Test status
Simulation time 757630143 ps
CPU time 10.47 seconds
Started May 02 02:10:57 PM PDT 24
Finished May 02 02:11:09 PM PDT 24
Peak memory 216356 kb
Host smart-1cc8a4e4-8415-483f-b312-c6827dcf157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704833368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1704833368
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1164587068
Short name T636
Test name
Test status
Simulation time 245815693 ps
CPU time 0.82 seconds
Started May 02 02:10:57 PM PDT 24
Finished May 02 02:10:59 PM PDT 24
Peak memory 205812 kb
Host smart-af681de1-bf1f-4547-8e2c-bbebc4a67dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164587068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1164587068
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3205407751
Short name T277
Test name
Test status
Simulation time 6491929172 ps
CPU time 21.09 seconds
Started May 02 02:10:50 PM PDT 24
Finished May 02 02:11:13 PM PDT 24
Peak memory 234892 kb
Host smart-fc06719d-2f5c-41db-9e2f-c0e825c6167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205407751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3205407751
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1988010529
Short name T433
Test name
Test status
Simulation time 92029120 ps
CPU time 0.73 seconds
Started May 02 02:07:15 PM PDT 24
Finished May 02 02:07:17 PM PDT 24
Peak memory 205432 kb
Host smart-d49dd747-e67d-456e-8fc8-ef0a59795455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988010529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
988010529
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.554281327
Short name T669
Test name
Test status
Simulation time 34895310 ps
CPU time 0.82 seconds
Started May 02 02:06:57 PM PDT 24
Finished May 02 02:06:59 PM PDT 24
Peak memory 206660 kb
Host smart-22c7c90e-e501-4e98-b17f-d461e38ec1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554281327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.554281327
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3623899449
Short name T233
Test name
Test status
Simulation time 44703041822 ps
CPU time 93.35 seconds
Started May 02 02:07:03 PM PDT 24
Finished May 02 02:08:38 PM PDT 24
Peak memory 229676 kb
Host smart-d092f119-46ae-40b6-bebd-310cbb131df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623899449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3623899449
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3750933481
Short name T267
Test name
Test status
Simulation time 4447802923 ps
CPU time 16.44 seconds
Started May 02 02:07:05 PM PDT 24
Finished May 02 02:07:22 PM PDT 24
Peak memory 234472 kb
Host smart-02d32568-df8a-4fc3-bac4-548035c2eab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750933481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3750933481
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1987913351
Short name T158
Test name
Test status
Simulation time 120371483 ps
CPU time 3.22 seconds
Started May 02 02:07:05 PM PDT 24
Finished May 02 02:07:10 PM PDT 24
Peak memory 220008 kb
Host smart-d058d099-f266-431d-802f-63bd0bcf22e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1987913351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1987913351
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2261845169
Short name T34
Test name
Test status
Simulation time 64037373 ps
CPU time 0.96 seconds
Started May 02 02:07:04 PM PDT 24
Finished May 02 02:07:06 PM PDT 24
Peak memory 235124 kb
Host smart-7153ee72-e57a-4e72-8773-fa638826c6b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261845169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2261845169
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3003335500
Short name T523
Test name
Test status
Simulation time 9032052472 ps
CPU time 22.84 seconds
Started May 02 02:06:55 PM PDT 24
Finished May 02 02:07:20 PM PDT 24
Peak memory 216336 kb
Host smart-7a76f524-544b-4a4b-bf1d-c47f70c542c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003335500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3003335500
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.148549579
Short name T420
Test name
Test status
Simulation time 227857132 ps
CPU time 2.68 seconds
Started May 02 02:07:03 PM PDT 24
Finished May 02 02:07:07 PM PDT 24
Peak memory 216296 kb
Host smart-ce93776d-f217-464a-802a-ef3d66db1ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148549579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.148549579
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.997595394
Short name T482
Test name
Test status
Simulation time 130623726 ps
CPU time 0.81 seconds
Started May 02 02:07:03 PM PDT 24
Finished May 02 02:07:05 PM PDT 24
Peak memory 205788 kb
Host smart-86c81595-45f1-4ac7-8920-7a0179feb558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997595394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.997595394
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2559436506
Short name T321
Test name
Test status
Simulation time 4384567344 ps
CPU time 3.29 seconds
Started May 02 02:07:06 PM PDT 24
Finished May 02 02:07:10 PM PDT 24
Peak memory 223648 kb
Host smart-e6d3028a-1a1f-4235-948d-312415e37e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559436506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2559436506
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4192269040
Short name T571
Test name
Test status
Simulation time 13684116 ps
CPU time 0.75 seconds
Started May 02 02:10:59 PM PDT 24
Finished May 02 02:11:00 PM PDT 24
Peak memory 205444 kb
Host smart-637e313a-4d6a-409a-a67a-c88061143dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192269040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4192269040
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3361604559
Short name T322
Test name
Test status
Simulation time 271933203 ps
CPU time 6.11 seconds
Started May 02 02:11:01 PM PDT 24
Finished May 02 02:11:08 PM PDT 24
Peak memory 232724 kb
Host smart-2480983c-4b90-42c1-a04e-e8d5e1abc45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361604559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3361604559
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.39381567
Short name T607
Test name
Test status
Simulation time 15716597 ps
CPU time 0.77 seconds
Started May 02 02:10:51 PM PDT 24
Finished May 02 02:10:53 PM PDT 24
Peak memory 206656 kb
Host smart-eae3d3b1-7d63-42b8-82fb-ac13bb6b8513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39381567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.39381567
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1653730472
Short name T303
Test name
Test status
Simulation time 2929738204 ps
CPU time 16.61 seconds
Started May 02 02:11:00 PM PDT 24
Finished May 02 02:11:19 PM PDT 24
Peak memory 249168 kb
Host smart-7ec76fcc-6c18-4bac-9a46-6f8a25221d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653730472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1653730472
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2179331992
Short name T372
Test name
Test status
Simulation time 882909193 ps
CPU time 13.72 seconds
Started May 02 02:10:58 PM PDT 24
Finished May 02 02:11:12 PM PDT 24
Peak memory 232572 kb
Host smart-bcfb4237-3494-4387-9d72-1c1ae9212d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179331992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2179331992
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1455353065
Short name T392
Test name
Test status
Simulation time 8252845569 ps
CPU time 23.45 seconds
Started May 02 02:11:00 PM PDT 24
Finished May 02 02:11:25 PM PDT 24
Peak memory 235848 kb
Host smart-228298e5-c616-40c8-ba22-3bb710414aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455353065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1455353065
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1223292984
Short name T624
Test name
Test status
Simulation time 179794669 ps
CPU time 4.84 seconds
Started May 02 02:11:01 PM PDT 24
Finished May 02 02:11:07 PM PDT 24
Peak memory 222916 kb
Host smart-ab347fc4-ba58-41c7-876f-57e8e4630358
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1223292984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1223292984
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3715010340
Short name T397
Test name
Test status
Simulation time 9692625810 ps
CPU time 27.15 seconds
Started May 02 02:11:06 PM PDT 24
Finished May 02 02:11:34 PM PDT 24
Peak memory 221876 kb
Host smart-5caa8853-6f46-4f6b-80f0-990ad2cbd234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715010340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3715010340
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2051902079
Short name T718
Test name
Test status
Simulation time 3521498720 ps
CPU time 11.98 seconds
Started May 02 02:11:00 PM PDT 24
Finished May 02 02:11:13 PM PDT 24
Peak memory 216268 kb
Host smart-a4268a78-acc6-4d0f-97b9-79a4633843d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051902079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2051902079
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.643965682
Short name T716
Test name
Test status
Simulation time 271845788 ps
CPU time 3.47 seconds
Started May 02 02:11:00 PM PDT 24
Finished May 02 02:11:04 PM PDT 24
Peak memory 216292 kb
Host smart-ee3c85e6-eac9-491c-8278-cc02a642539c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643965682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.643965682
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.156047806
Short name T518
Test name
Test status
Simulation time 310328980 ps
CPU time 0.94 seconds
Started May 02 02:11:02 PM PDT 24
Finished May 02 02:11:05 PM PDT 24
Peak memory 206820 kb
Host smart-56e2107f-ebd0-496f-86ad-38e70c92b802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156047806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.156047806
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3442028662
Short name T568
Test name
Test status
Simulation time 38762191 ps
CPU time 0.72 seconds
Started May 02 02:11:18 PM PDT 24
Finished May 02 02:11:20 PM PDT 24
Peak memory 204832 kb
Host smart-7fcec6d5-eac8-454b-8556-b5b6cd96c4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442028662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3442028662
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3013096605
Short name T608
Test name
Test status
Simulation time 43443066 ps
CPU time 0.77 seconds
Started May 02 02:11:03 PM PDT 24
Finished May 02 02:11:05 PM PDT 24
Peak memory 205680 kb
Host smart-95979769-8bb5-4f34-b34c-5c2ba0a76fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013096605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3013096605
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2001637159
Short name T316
Test name
Test status
Simulation time 6376842711 ps
CPU time 92.81 seconds
Started May 02 02:11:08 PM PDT 24
Finished May 02 02:12:42 PM PDT 24
Peak memory 240952 kb
Host smart-3aadfa3b-572b-4c00-bee3-21fa6c9b6bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001637159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2001637159
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1830783991
Short name T630
Test name
Test status
Simulation time 859208942 ps
CPU time 3.45 seconds
Started May 02 02:11:01 PM PDT 24
Finished May 02 02:11:06 PM PDT 24
Peak memory 223040 kb
Host smart-d52a7aaa-760a-4de1-97f8-46abcfd1bedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830783991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1830783991
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1964229824
Short name T358
Test name
Test status
Simulation time 12334052789 ps
CPU time 8.18 seconds
Started May 02 02:11:00 PM PDT 24
Finished May 02 02:11:10 PM PDT 24
Peak memory 216720 kb
Host smart-b927b622-244f-41ae-8e90-d90776e7b1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964229824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1964229824
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1972772793
Short name T393
Test name
Test status
Simulation time 2443740273 ps
CPU time 7.89 seconds
Started May 02 02:11:01 PM PDT 24
Finished May 02 02:11:10 PM PDT 24
Peak memory 226832 kb
Host smart-14eb4ddc-64dc-46ef-a150-6a5fd4eca2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972772793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1972772793
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4250835341
Short name T711
Test name
Test status
Simulation time 1001686048 ps
CPU time 10.26 seconds
Started May 02 02:11:07 PM PDT 24
Finished May 02 02:11:19 PM PDT 24
Peak memory 221728 kb
Host smart-cd357b2c-e422-4a5a-97db-57f841ca4870
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4250835341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4250835341
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1287730769
Short name T61
Test name
Test status
Simulation time 2970474128 ps
CPU time 7.12 seconds
Started May 02 02:10:59 PM PDT 24
Finished May 02 02:11:07 PM PDT 24
Peak memory 216356 kb
Host smart-17d686bd-3bbd-4cc7-9592-51f4e83202b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287730769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1287730769
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3689267413
Short name T601
Test name
Test status
Simulation time 5607832888 ps
CPU time 10.32 seconds
Started May 02 02:10:59 PM PDT 24
Finished May 02 02:11:11 PM PDT 24
Peak memory 216316 kb
Host smart-8c5f150f-ec1c-47f1-992a-704220dc2a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689267413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3689267413
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3134978424
Short name T60
Test name
Test status
Simulation time 482480784 ps
CPU time 5.64 seconds
Started May 02 02:11:01 PM PDT 24
Finished May 02 02:11:08 PM PDT 24
Peak memory 216344 kb
Host smart-4fd575d2-9020-4484-b48a-b34b2c2f496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134978424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3134978424
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.868024309
Short name T528
Test name
Test status
Simulation time 126105538 ps
CPU time 0.89 seconds
Started May 02 02:11:01 PM PDT 24
Finished May 02 02:11:03 PM PDT 24
Peak memory 206800 kb
Host smart-7fd25a86-1565-40e4-a1f7-9701a5151d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868024309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.868024309
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3202464521
Short name T586
Test name
Test status
Simulation time 23478241 ps
CPU time 0.7 seconds
Started May 02 02:11:08 PM PDT 24
Finished May 02 02:11:10 PM PDT 24
Peak memory 205352 kb
Host smart-878b6fb7-9a54-44d0-abda-e3a51c150ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202464521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3202464521
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4178939297
Short name T346
Test name
Test status
Simulation time 5897545416 ps
CPU time 15.73 seconds
Started May 02 02:11:07 PM PDT 24
Finished May 02 02:11:24 PM PDT 24
Peak memory 218616 kb
Host smart-967f5dbe-0beb-45fb-a3be-9614d1556e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178939297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4178939297
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.731111223
Short name T450
Test name
Test status
Simulation time 15365592 ps
CPU time 0.74 seconds
Started May 02 02:11:09 PM PDT 24
Finished May 02 02:11:11 PM PDT 24
Peak memory 207028 kb
Host smart-e7b4aba3-d978-4ac8-a53c-b9128073ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731111223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.731111223
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2357339598
Short name T251
Test name
Test status
Simulation time 871593568 ps
CPU time 3.98 seconds
Started May 02 02:11:09 PM PDT 24
Finished May 02 02:11:15 PM PDT 24
Peak memory 216804 kb
Host smart-2ae83026-9545-43cd-9dba-a396993bca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357339598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2357339598
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.971230584
Short name T558
Test name
Test status
Simulation time 402476795 ps
CPU time 4.06 seconds
Started May 02 02:11:08 PM PDT 24
Finished May 02 02:11:14 PM PDT 24
Peak memory 223032 kb
Host smart-ec8c2d5e-44db-4542-b006-a4c11bfe0d45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=971230584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.971230584
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3167401652
Short name T42
Test name
Test status
Simulation time 40112066 ps
CPU time 0.97 seconds
Started May 02 02:11:08 PM PDT 24
Finished May 02 02:11:11 PM PDT 24
Peak memory 207048 kb
Host smart-f19fd3a1-a9dd-410a-85e3-1223b2532073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167401652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3167401652
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.400073581
Short name T411
Test name
Test status
Simulation time 37888973499 ps
CPU time 51.63 seconds
Started May 02 02:11:13 PM PDT 24
Finished May 02 02:12:06 PM PDT 24
Peak memory 216360 kb
Host smart-6acdc30a-2d59-4539-8a45-64688befb7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400073581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.400073581
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3422655421
Short name T466
Test name
Test status
Simulation time 102033785644 ps
CPU time 17.42 seconds
Started May 02 02:11:12 PM PDT 24
Finished May 02 02:11:30 PM PDT 24
Peak memory 216344 kb
Host smart-066f1469-8612-484f-9857-b7e08ed59e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422655421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3422655421
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.10108430
Short name T428
Test name
Test status
Simulation time 520627791 ps
CPU time 2.32 seconds
Started May 02 02:11:07 PM PDT 24
Finished May 02 02:11:11 PM PDT 24
Peak memory 216316 kb
Host smart-db3ba01c-c5bb-40af-88cb-593ca1af7449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10108430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.10108430
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.256755945
Short name T616
Test name
Test status
Simulation time 79691030 ps
CPU time 0.86 seconds
Started May 02 02:11:12 PM PDT 24
Finished May 02 02:11:14 PM PDT 24
Peak memory 205744 kb
Host smart-2ae4b16a-5119-4cd3-92e5-0e09de6cc211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256755945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.256755945
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.711043436
Short name T509
Test name
Test status
Simulation time 48679342 ps
CPU time 0.73 seconds
Started May 02 02:11:15 PM PDT 24
Finished May 02 02:11:17 PM PDT 24
Peak memory 204876 kb
Host smart-ef0fe845-fa93-42d2-a3c1-ba983f7098e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711043436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.711043436
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1369194286
Short name T671
Test name
Test status
Simulation time 13396414 ps
CPU time 0.77 seconds
Started May 02 02:11:06 PM PDT 24
Finished May 02 02:11:08 PM PDT 24
Peak memory 205192 kb
Host smart-17241ef4-6251-4b97-97d7-92d24ffa5158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369194286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1369194286
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2839910433
Short name T375
Test name
Test status
Simulation time 3901108949 ps
CPU time 19.24 seconds
Started May 02 02:11:15 PM PDT 24
Finished May 02 02:11:36 PM PDT 24
Peak memory 234504 kb
Host smart-d2ba346f-1c9c-4a48-881f-27d45127f07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839910433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2839910433
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2822220749
Short name T228
Test name
Test status
Simulation time 248026758 ps
CPU time 4.43 seconds
Started May 02 02:11:22 PM PDT 24
Finished May 02 02:11:28 PM PDT 24
Peak memory 232364 kb
Host smart-a2045b48-ef6e-45d0-ae03-1931585f5ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822220749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2822220749
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2527793786
Short name T260
Test name
Test status
Simulation time 6487173187 ps
CPU time 66.52 seconds
Started May 02 02:11:15 PM PDT 24
Finished May 02 02:12:22 PM PDT 24
Peak memory 248560 kb
Host smart-e4acc87a-95cf-4c26-9c48-6408f53e477d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527793786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2527793786
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4112794518
Short name T219
Test name
Test status
Simulation time 1634103617 ps
CPU time 4.31 seconds
Started May 02 02:11:16 PM PDT 24
Finished May 02 02:11:22 PM PDT 24
Peak memory 218372 kb
Host smart-40c7099d-8fc1-43f2-9290-db2333c58070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112794518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4112794518
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3420853399
Short name T503
Test name
Test status
Simulation time 243318321 ps
CPU time 5.16 seconds
Started May 02 02:11:17 PM PDT 24
Finished May 02 02:11:24 PM PDT 24
Peak memory 220424 kb
Host smart-1a2c6c1f-b3ae-465a-a649-53c680f1526a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3420853399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3420853399
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2544133708
Short name T714
Test name
Test status
Simulation time 6321818509 ps
CPU time 33.33 seconds
Started May 02 02:11:14 PM PDT 24
Finished May 02 02:11:48 PM PDT 24
Peak memory 216280 kb
Host smart-5d8d70bc-e109-45a3-84cb-772bb31dae71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544133708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2544133708
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2205089340
Short name T554
Test name
Test status
Simulation time 3227774125 ps
CPU time 12.4 seconds
Started May 02 02:11:07 PM PDT 24
Finished May 02 02:11:21 PM PDT 24
Peak memory 216412 kb
Host smart-b718bf0d-6c5d-4bde-8553-2d3219c3fefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205089340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2205089340
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.998319759
Short name T640
Test name
Test status
Simulation time 272312143 ps
CPU time 2.31 seconds
Started May 02 02:11:23 PM PDT 24
Finished May 02 02:11:27 PM PDT 24
Peak memory 216224 kb
Host smart-f2076570-6bf8-4282-b419-fcf5675deb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998319759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.998319759
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1553351130
Short name T447
Test name
Test status
Simulation time 524651171 ps
CPU time 1.17 seconds
Started May 02 02:11:09 PM PDT 24
Finished May 02 02:11:11 PM PDT 24
Peak memory 206848 kb
Host smart-21354741-896b-468f-89de-b3a51524e1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553351130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1553351130
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2088071255
Short name T332
Test name
Test status
Simulation time 20154081707 ps
CPU time 8.9 seconds
Started May 02 02:11:23 PM PDT 24
Finished May 02 02:11:33 PM PDT 24
Peak memory 234424 kb
Host smart-8c812b5c-de52-4703-90a3-9935df85a859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088071255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2088071255
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3700497969
Short name T533
Test name
Test status
Simulation time 44991351 ps
CPU time 0.78 seconds
Started May 02 02:11:25 PM PDT 24
Finished May 02 02:11:27 PM PDT 24
Peak memory 204892 kb
Host smart-a398c20f-7088-419a-bbac-351fda4acea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700497969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3700497969
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2443722617
Short name T674
Test name
Test status
Simulation time 27920703 ps
CPU time 0.79 seconds
Started May 02 02:11:16 PM PDT 24
Finished May 02 02:11:18 PM PDT 24
Peak memory 206624 kb
Host smart-f167cca3-050a-4f15-9b56-e4dd6ae1e7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443722617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2443722617
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1585819189
Short name T288
Test name
Test status
Simulation time 6776174488 ps
CPU time 15.06 seconds
Started May 02 02:11:18 PM PDT 24
Finished May 02 02:11:35 PM PDT 24
Peak memory 218664 kb
Host smart-4bc362ed-3b3f-4d61-8205-7cd019df35ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585819189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1585819189
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3129498281
Short name T592
Test name
Test status
Simulation time 215435337 ps
CPU time 5.53 seconds
Started May 02 02:11:22 PM PDT 24
Finished May 02 02:11:29 PM PDT 24
Peak memory 222888 kb
Host smart-196f7fdf-092b-4250-a537-3cab55dd88a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3129498281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3129498281
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.512333455
Short name T396
Test name
Test status
Simulation time 37041495455 ps
CPU time 47.66 seconds
Started May 02 02:11:16 PM PDT 24
Finished May 02 02:12:06 PM PDT 24
Peak memory 216584 kb
Host smart-0e0267c4-197a-4bc6-acdd-1e6e9d140b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512333455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.512333455
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3903439357
Short name T497
Test name
Test status
Simulation time 31681999891 ps
CPU time 28.27 seconds
Started May 02 02:11:23 PM PDT 24
Finished May 02 02:11:53 PM PDT 24
Peak memory 216364 kb
Host smart-f77877dd-51d3-49e8-9b91-895163279feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903439357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3903439357
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3437878647
Short name T19
Test name
Test status
Simulation time 160646705 ps
CPU time 1.54 seconds
Started May 02 02:11:15 PM PDT 24
Finished May 02 02:11:18 PM PDT 24
Peak memory 216316 kb
Host smart-553991e5-7d24-408a-ab1c-366f30b99ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437878647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3437878647
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1806307512
Short name T591
Test name
Test status
Simulation time 110432803 ps
CPU time 1.06 seconds
Started May 02 02:11:17 PM PDT 24
Finished May 02 02:11:20 PM PDT 24
Peak memory 206772 kb
Host smart-37342f42-1bc0-4655-a944-88999d072703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806307512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1806307512
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.941611127
Short name T69
Test name
Test status
Simulation time 161303711 ps
CPU time 3.77 seconds
Started May 02 02:11:22 PM PDT 24
Finished May 02 02:11:27 PM PDT 24
Peak memory 218588 kb
Host smart-1e22a7a5-3640-432a-93f4-6bafda160642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941611127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.941611127
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3247085010
Short name T483
Test name
Test status
Simulation time 15427703 ps
CPU time 0.74 seconds
Started May 02 02:11:33 PM PDT 24
Finished May 02 02:11:35 PM PDT 24
Peak memory 205348 kb
Host smart-da9c5154-69a2-4b8e-83e1-2d95062129ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247085010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3247085010
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3420212707
Short name T478
Test name
Test status
Simulation time 17326802 ps
CPU time 0.76 seconds
Started May 02 02:11:24 PM PDT 24
Finished May 02 02:11:26 PM PDT 24
Peak memory 205936 kb
Host smart-d8c2943a-8e37-4c43-bcf5-af1b0001b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420212707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3420212707
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.401311264
Short name T154
Test name
Test status
Simulation time 15012218618 ps
CPU time 103.57 seconds
Started May 02 02:11:36 PM PDT 24
Finished May 02 02:13:21 PM PDT 24
Peak memory 237420 kb
Host smart-af74f35c-1ab4-4663-af1f-09e0c68b5d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401311264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.401311264
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1740400932
Short name T355
Test name
Test status
Simulation time 454823579 ps
CPU time 8.59 seconds
Started May 02 02:11:34 PM PDT 24
Finished May 02 02:11:43 PM PDT 24
Peak memory 224428 kb
Host smart-980d8a03-0b14-4b79-b7c6-74201a722973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740400932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1740400932
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1799130894
Short name T460
Test name
Test status
Simulation time 172974270 ps
CPU time 3.61 seconds
Started May 02 02:11:33 PM PDT 24
Finished May 02 02:11:37 PM PDT 24
Peak memory 219124 kb
Host smart-06477313-7bda-424b-a3e3-0d9d116dc52a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1799130894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1799130894
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.542639057
Short name T41
Test name
Test status
Simulation time 73389834 ps
CPU time 1.1 seconds
Started May 02 02:11:32 PM PDT 24
Finished May 02 02:11:34 PM PDT 24
Peak memory 207376 kb
Host smart-55ea45d4-9ada-492d-8024-388edfbb1c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542639057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.542639057
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1256919491
Short name T408
Test name
Test status
Simulation time 25439117254 ps
CPU time 34.83 seconds
Started May 02 02:11:22 PM PDT 24
Finished May 02 02:11:58 PM PDT 24
Peak memory 216348 kb
Host smart-af5f586a-963e-4be1-bb22-e3c0d02e5df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256919491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1256919491
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3154042601
Short name T722
Test name
Test status
Simulation time 887725140 ps
CPU time 1.99 seconds
Started May 02 02:11:27 PM PDT 24
Finished May 02 02:11:30 PM PDT 24
Peak memory 207800 kb
Host smart-73632eb1-ec12-4488-81c8-613f152abf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154042601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3154042601
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2133506713
Short name T414
Test name
Test status
Simulation time 185927299 ps
CPU time 5.82 seconds
Started May 02 02:11:35 PM PDT 24
Finished May 02 02:11:42 PM PDT 24
Peak memory 216432 kb
Host smart-3d485078-0a5f-410f-975c-2b5289bdf708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133506713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2133506713
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3929447593
Short name T501
Test name
Test status
Simulation time 75645443 ps
CPU time 0.79 seconds
Started May 02 02:11:24 PM PDT 24
Finished May 02 02:11:26 PM PDT 24
Peak memory 205708 kb
Host smart-b7f8eb37-28fa-40fc-9eec-c47c0f88a45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929447593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3929447593
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.276763997
Short name T371
Test name
Test status
Simulation time 5449214525 ps
CPU time 5.79 seconds
Started May 02 02:11:34 PM PDT 24
Finished May 02 02:11:41 PM PDT 24
Peak memory 222908 kb
Host smart-71b156d1-ab16-46fa-90e1-080cbdd0ae24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276763997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.276763997
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.998652862
Short name T627
Test name
Test status
Simulation time 11756856 ps
CPU time 0.72 seconds
Started May 02 02:11:44 PM PDT 24
Finished May 02 02:11:46 PM PDT 24
Peak memory 205432 kb
Host smart-8097622b-2174-4573-9ea1-b63e85a5184f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998652862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.998652862
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.86219069
Short name T23
Test name
Test status
Simulation time 57868150 ps
CPU time 0.76 seconds
Started May 02 02:11:32 PM PDT 24
Finished May 02 02:11:34 PM PDT 24
Peak memory 207004 kb
Host smart-563c2aaf-5f0c-447f-8cf5-c64c99d273a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86219069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.86219069
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1422809828
Short name T365
Test name
Test status
Simulation time 8694361499 ps
CPU time 82.3 seconds
Started May 02 02:11:42 PM PDT 24
Finished May 02 02:13:06 PM PDT 24
Peak memory 232716 kb
Host smart-8d42f7de-ea5e-4fff-80dd-caa04a0f2f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422809828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1422809828
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.608701881
Short name T565
Test name
Test status
Simulation time 442224102 ps
CPU time 5.36 seconds
Started May 02 02:11:42 PM PDT 24
Finished May 02 02:11:49 PM PDT 24
Peak memory 222868 kb
Host smart-ad40173e-cc74-4c44-911b-9d52bfb6fdd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=608701881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.608701881
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.743390819
Short name T406
Test name
Test status
Simulation time 6269391573 ps
CPU time 26.3 seconds
Started May 02 02:11:43 PM PDT 24
Finished May 02 02:12:11 PM PDT 24
Peak memory 215820 kb
Host smart-5dac3cb5-c041-458e-8cd7-16502e587dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743390819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.743390819
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2853463045
Short name T512
Test name
Test status
Simulation time 2822082857 ps
CPU time 7.37 seconds
Started May 02 02:11:34 PM PDT 24
Finished May 02 02:11:43 PM PDT 24
Peak memory 216320 kb
Host smart-76dd72e7-aa46-4346-bafb-919b48889cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853463045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2853463045
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2405778327
Short name T683
Test name
Test status
Simulation time 20625923 ps
CPU time 0.89 seconds
Started May 02 02:11:42 PM PDT 24
Finished May 02 02:11:44 PM PDT 24
Peak memory 206824 kb
Host smart-2207ea86-50c9-4a93-b6c0-d46d2ede2417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405778327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2405778327
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2281875753
Short name T527
Test name
Test status
Simulation time 155984671 ps
CPU time 0.95 seconds
Started May 02 02:11:43 PM PDT 24
Finished May 02 02:11:45 PM PDT 24
Peak memory 205712 kb
Host smart-5008535e-cad4-4351-a8a1-f98beb1234e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281875753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2281875753
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1374762817
Short name T432
Test name
Test status
Simulation time 12460526 ps
CPU time 0.77 seconds
Started May 02 02:11:50 PM PDT 24
Finished May 02 02:11:53 PM PDT 24
Peak memory 205372 kb
Host smart-49da1ca2-fb0a-4a8d-9c04-23d6cc574639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374762817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1374762817
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2878735666
Short name T29
Test name
Test status
Simulation time 903922682 ps
CPU time 6.51 seconds
Started May 02 02:11:52 PM PDT 24
Finished May 02 02:12:00 PM PDT 24
Peak memory 224168 kb
Host smart-61d65cdb-06e2-4ffb-92b7-13ac544bc86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878735666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2878735666
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1581225433
Short name T458
Test name
Test status
Simulation time 17520734 ps
CPU time 0.76 seconds
Started May 02 02:11:45 PM PDT 24
Finished May 02 02:11:47 PM PDT 24
Peak memory 205616 kb
Host smart-5497bf1a-b112-4da8-b6c4-59ba81847a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581225433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1581225433
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2203654628
Short name T306
Test name
Test status
Simulation time 23247902591 ps
CPU time 28.41 seconds
Started May 02 02:11:49 PM PDT 24
Finished May 02 02:12:19 PM PDT 24
Peak memory 249124 kb
Host smart-5e67c6a8-76f4-4147-b33c-96973e85e0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203654628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2203654628
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4253523689
Short name T473
Test name
Test status
Simulation time 780819860 ps
CPU time 11.65 seconds
Started May 02 02:11:51 PM PDT 24
Finished May 02 02:12:04 PM PDT 24
Peak memory 219152 kb
Host smart-e1f7f0a5-2985-42d0-a0cb-9fc24205ee4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4253523689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4253523689
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4171499941
Short name T697
Test name
Test status
Simulation time 2407833251 ps
CPU time 13.55 seconds
Started May 02 02:11:41 PM PDT 24
Finished May 02 02:11:56 PM PDT 24
Peak memory 216364 kb
Host smart-cbdc3f30-3760-4f8b-b5bb-c1032209c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171499941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4171499941
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1788465296
Short name T477
Test name
Test status
Simulation time 21953052214 ps
CPU time 13.85 seconds
Started May 02 02:11:41 PM PDT 24
Finished May 02 02:11:57 PM PDT 24
Peak memory 216352 kb
Host smart-bf27c3a4-280d-4051-9a94-02c54a971bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788465296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1788465296
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2855870218
Short name T431
Test name
Test status
Simulation time 29415671 ps
CPU time 1.06 seconds
Started May 02 02:11:49 PM PDT 24
Finished May 02 02:11:52 PM PDT 24
Peak memory 216068 kb
Host smart-6b814123-9274-4bbb-97a4-92d24a7d98e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855870218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2855870218
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.24562351
Short name T504
Test name
Test status
Simulation time 46661245 ps
CPU time 0.89 seconds
Started May 02 02:11:50 PM PDT 24
Finished May 02 02:11:53 PM PDT 24
Peak memory 206796 kb
Host smart-733a5b95-bd43-486e-8481-965e633fb2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24562351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.24562351
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.387607760
Short name T30
Test name
Test status
Simulation time 24188144 ps
CPU time 0.75 seconds
Started May 02 02:11:59 PM PDT 24
Finished May 02 02:12:02 PM PDT 24
Peak memory 205380 kb
Host smart-cec831ff-d8f2-4d14-8802-299947cb5ea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387607760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.387607760
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.652498395
Short name T723
Test name
Test status
Simulation time 51363610 ps
CPU time 0.77 seconds
Started May 02 02:11:49 PM PDT 24
Finished May 02 02:11:52 PM PDT 24
Peak memory 206952 kb
Host smart-37c79e98-7aac-43bd-ad21-895019db97f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652498395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.652498395
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2517289375
Short name T91
Test name
Test status
Simulation time 1885575495 ps
CPU time 21.8 seconds
Started May 02 02:11:49 PM PDT 24
Finished May 02 02:12:13 PM PDT 24
Peak memory 250300 kb
Host smart-b7395803-90dd-406b-8bbb-d9f1f2420b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517289375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2517289375
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1103103179
Short name T342
Test name
Test status
Simulation time 701062192 ps
CPU time 7.53 seconds
Started May 02 02:11:55 PM PDT 24
Finished May 02 02:12:04 PM PDT 24
Peak memory 223384 kb
Host smart-31654cdf-055d-4a24-8eed-c07cc5cfa2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103103179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1103103179
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1317703420
Short name T121
Test name
Test status
Simulation time 3294811751 ps
CPU time 17.24 seconds
Started May 02 02:11:48 PM PDT 24
Finished May 02 02:12:07 PM PDT 24
Peak memory 218844 kb
Host smart-d9383286-ff88-4665-b1ec-b5fd596bb744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317703420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1317703420
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3648400988
Short name T475
Test name
Test status
Simulation time 238184560 ps
CPU time 2.31 seconds
Started May 02 02:11:48 PM PDT 24
Finished May 02 02:11:52 PM PDT 24
Peak memory 218704 kb
Host smart-246e13d8-1b8e-4609-a2f3-4c0e8efde0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648400988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3648400988
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.123951724
Short name T241
Test name
Test status
Simulation time 2942957921 ps
CPU time 12.08 seconds
Started May 02 02:11:50 PM PDT 24
Finished May 02 02:12:04 PM PDT 24
Peak memory 216908 kb
Host smart-66887c52-4fa6-469b-9fed-423ae2f00751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123951724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.123951724
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1988539733
Short name T620
Test name
Test status
Simulation time 2391483309 ps
CPU time 10.43 seconds
Started May 02 02:11:51 PM PDT 24
Finished May 02 02:12:03 PM PDT 24
Peak memory 223172 kb
Host smart-06541dab-8ea3-4f11-af6a-c65c89cb246a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1988539733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1988539733
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2520808550
Short name T560
Test name
Test status
Simulation time 1639866534 ps
CPU time 18.61 seconds
Started May 02 02:11:49 PM PDT 24
Finished May 02 02:12:10 PM PDT 24
Peak memory 216564 kb
Host smart-f3d04985-eb4d-4688-84c2-46c18a816403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520808550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2520808550
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3910928192
Short name T583
Test name
Test status
Simulation time 3449964109 ps
CPU time 6.09 seconds
Started May 02 02:11:49 PM PDT 24
Finished May 02 02:11:57 PM PDT 24
Peak memory 216412 kb
Host smart-25aea5be-628c-4b8b-9ed0-536874c6c8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910928192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3910928192
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2847419223
Short name T419
Test name
Test status
Simulation time 44010804 ps
CPU time 1.03 seconds
Started May 02 02:11:52 PM PDT 24
Finished May 02 02:11:55 PM PDT 24
Peak memory 206948 kb
Host smart-93d34ae9-aff7-43c5-9657-88c12d3cf9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847419223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2847419223
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2986951936
Short name T661
Test name
Test status
Simulation time 65494918 ps
CPU time 0.96 seconds
Started May 02 02:11:49 PM PDT 24
Finished May 02 02:11:52 PM PDT 24
Peak memory 206844 kb
Host smart-63999532-353e-495f-ac89-a375d8e31af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986951936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2986951936
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.149107741
Short name T507
Test name
Test status
Simulation time 11049569 ps
CPU time 0.73 seconds
Started May 02 02:12:04 PM PDT 24
Finished May 02 02:12:06 PM PDT 24
Peak memory 205412 kb
Host smart-2834cc7b-e350-465c-a017-80c226969605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149107741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.149107741
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.115807922
Short name T499
Test name
Test status
Simulation time 49084835 ps
CPU time 0.77 seconds
Started May 02 02:11:59 PM PDT 24
Finished May 02 02:12:02 PM PDT 24
Peak memory 205604 kb
Host smart-61bc1da2-98c0-48d4-a41e-5a6b17600a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115807922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.115807922
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3553476998
Short name T379
Test name
Test status
Simulation time 31311494964 ps
CPU time 101.81 seconds
Started May 02 02:12:00 PM PDT 24
Finished May 02 02:13:44 PM PDT 24
Peak memory 235660 kb
Host smart-89b25625-b0d8-4808-a9ed-4650806ccb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553476998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3553476998
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2658561565
Short name T338
Test name
Test status
Simulation time 2839458879 ps
CPU time 14.99 seconds
Started May 02 02:11:58 PM PDT 24
Finished May 02 02:12:14 PM PDT 24
Peak memory 232572 kb
Host smart-feed3b11-4985-48b0-a8e6-54e87f34f351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658561565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2658561565
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3028627476
Short name T253
Test name
Test status
Simulation time 500346868 ps
CPU time 7.08 seconds
Started May 02 02:11:58 PM PDT 24
Finished May 02 02:12:06 PM PDT 24
Peak memory 224580 kb
Host smart-6eb1703c-5e3d-4660-ad0b-32278cc37853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028627476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3028627476
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.885719690
Short name T677
Test name
Test status
Simulation time 998125365 ps
CPU time 8.01 seconds
Started May 02 02:11:59 PM PDT 24
Finished May 02 02:12:09 PM PDT 24
Peak memory 220632 kb
Host smart-bde8d3fc-792c-466c-b2ae-74fc070aef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885719690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.885719690
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.586758017
Short name T573
Test name
Test status
Simulation time 1116638415 ps
CPU time 8.64 seconds
Started May 02 02:11:59 PM PDT 24
Finished May 02 02:12:09 PM PDT 24
Peak memory 223084 kb
Host smart-f6eb4fba-1578-472b-bfa6-b582256f59d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=586758017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.586758017
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2750190530
Short name T65
Test name
Test status
Simulation time 26474774447 ps
CPU time 44.48 seconds
Started May 02 02:12:04 PM PDT 24
Finished May 02 02:12:50 PM PDT 24
Peak memory 216300 kb
Host smart-9d089278-8e0f-4ec2-b4a1-62376f852253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750190530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2750190530
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.493682322
Short name T485
Test name
Test status
Simulation time 27890692393 ps
CPU time 30.6 seconds
Started May 02 02:11:59 PM PDT 24
Finished May 02 02:12:32 PM PDT 24
Peak memory 216336 kb
Host smart-939a8ef1-7ec1-4f3e-afc9-0f4ca4997543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493682322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.493682322
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3795942729
Short name T606
Test name
Test status
Simulation time 50660330 ps
CPU time 3.2 seconds
Started May 02 02:11:59 PM PDT 24
Finished May 02 02:12:05 PM PDT 24
Peak memory 216312 kb
Host smart-b6648f59-50d6-4dc0-a0f9-263fb9e63aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795942729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3795942729
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2302320885
Short name T660
Test name
Test status
Simulation time 89940812 ps
CPU time 0.97 seconds
Started May 02 02:11:58 PM PDT 24
Finished May 02 02:12:00 PM PDT 24
Peak memory 205828 kb
Host smart-ade223c5-ff9b-4ccc-a179-d3aaad49f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302320885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2302320885
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3511433891
Short name T252
Test name
Test status
Simulation time 2297781036 ps
CPU time 5.65 seconds
Started May 02 02:11:59 PM PDT 24
Finished May 02 02:12:07 PM PDT 24
Peak memory 216392 kb
Host smart-15fb7fd1-223f-4681-9c18-51c9cc791ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511433891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3511433891
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1392272811
Short name T659
Test name
Test status
Simulation time 13687276 ps
CPU time 0.81 seconds
Started May 02 02:07:11 PM PDT 24
Finished May 02 02:07:13 PM PDT 24
Peak memory 205456 kb
Host smart-a0634b25-4272-4f13-a96a-d18eed76a513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392272811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
392272811
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1844699383
Short name T626
Test name
Test status
Simulation time 19926918 ps
CPU time 0.82 seconds
Started May 02 02:07:12 PM PDT 24
Finished May 02 02:07:14 PM PDT 24
Peak memory 206676 kb
Host smart-a856769a-d215-46eb-baff-0e5c347bb221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844699383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1844699383
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1694132815
Short name T90
Test name
Test status
Simulation time 35662128980 ps
CPU time 44.09 seconds
Started May 02 02:07:11 PM PDT 24
Finished May 02 02:07:57 PM PDT 24
Peak memory 232692 kb
Host smart-c816a1be-0360-4242-8b13-8b2a712913a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694132815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1694132815
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2647829982
Short name T258
Test name
Test status
Simulation time 2973231118 ps
CPU time 9.85 seconds
Started May 02 02:07:11 PM PDT 24
Finished May 02 02:07:23 PM PDT 24
Peak memory 232320 kb
Host smart-eda0df96-2a60-4c33-a60b-b3bbb3a73690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647829982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2647829982
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2071185439
Short name T529
Test name
Test status
Simulation time 3170439600 ps
CPU time 10.33 seconds
Started May 02 02:07:23 PM PDT 24
Finished May 02 02:07:35 PM PDT 24
Peak memory 220180 kb
Host smart-baed4f22-7cd2-46b9-9940-3b9d8fa740d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071185439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2071185439
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3361502792
Short name T617
Test name
Test status
Simulation time 7628906375 ps
CPU time 19.63 seconds
Started May 02 02:07:12 PM PDT 24
Finished May 02 02:07:33 PM PDT 24
Peak memory 216316 kb
Host smart-e0492145-6790-45a3-ac37-62981e5e7667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361502792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3361502792
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3036763297
Short name T109
Test name
Test status
Simulation time 5711398504 ps
CPU time 20.32 seconds
Started May 02 02:07:13 PM PDT 24
Finished May 02 02:07:35 PM PDT 24
Peak memory 216380 kb
Host smart-78d2ead8-8e54-431f-aa54-aabb27dbe84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036763297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3036763297
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3166866240
Short name T413
Test name
Test status
Simulation time 380508291 ps
CPU time 10.3 seconds
Started May 02 02:07:11 PM PDT 24
Finished May 02 02:07:22 PM PDT 24
Peak memory 216324 kb
Host smart-b961c5e2-6bb8-4514-9bcc-5e3c214f09ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166866240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3166866240
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2429287303
Short name T653
Test name
Test status
Simulation time 432728149 ps
CPU time 0.74 seconds
Started May 02 02:07:12 PM PDT 24
Finished May 02 02:07:14 PM PDT 24
Peak memory 205784 kb
Host smart-89d2f5a9-7099-4a28-905b-67bbf410bbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429287303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2429287303
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.493989775
Short name T221
Test name
Test status
Simulation time 1010114631 ps
CPU time 5.81 seconds
Started May 02 02:07:13 PM PDT 24
Finished May 02 02:07:20 PM PDT 24
Peak memory 223156 kb
Host smart-b6e42b11-28d4-479e-92f3-3548c9725088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493989775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.493989775
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1675874361
Short name T32
Test name
Test status
Simulation time 18553632 ps
CPU time 0.74 seconds
Started May 02 02:07:24 PM PDT 24
Finished May 02 02:07:26 PM PDT 24
Peak memory 205396 kb
Host smart-7f60cf87-9d53-4dc9-8ee1-f96c26fd9f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675874361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
675874361
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1525652547
Short name T667
Test name
Test status
Simulation time 1294152843 ps
CPU time 6.58 seconds
Started May 02 02:07:23 PM PDT 24
Finished May 02 02:07:31 PM PDT 24
Peak memory 224408 kb
Host smart-0c05a3f9-5d1a-4363-b03f-1af6a7e7168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525652547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1525652547
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3352506929
Short name T455
Test name
Test status
Simulation time 20098098 ps
CPU time 0.8 seconds
Started May 02 02:07:15 PM PDT 24
Finished May 02 02:07:16 PM PDT 24
Peak memory 206752 kb
Host smart-96060997-5e9e-43f8-93ef-82317f5011e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352506929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3352506929
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2782185403
Short name T111
Test name
Test status
Simulation time 7413648452 ps
CPU time 34.34 seconds
Started May 02 02:07:28 PM PDT 24
Finished May 02 02:08:03 PM PDT 24
Peak memory 240964 kb
Host smart-4f21716f-03fa-4423-8ae7-4aee7c755a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782185403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2782185403
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2311455721
Short name T352
Test name
Test status
Simulation time 2082505349 ps
CPU time 23.05 seconds
Started May 02 02:07:22 PM PDT 24
Finished May 02 02:07:47 PM PDT 24
Peak memory 218516 kb
Host smart-af2e2375-1f7e-4cf8-9bef-0ee9081dfe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311455721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2311455721
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3751256651
Short name T222
Test name
Test status
Simulation time 25477839544 ps
CPU time 94.03 seconds
Started May 02 02:07:21 PM PDT 24
Finished May 02 02:08:56 PM PDT 24
Peak memory 231204 kb
Host smart-98514364-bc9d-4ce8-a259-b4c1333ee955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751256651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3751256651
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2406278890
Short name T266
Test name
Test status
Simulation time 23851242678 ps
CPU time 9.86 seconds
Started May 02 02:07:23 PM PDT 24
Finished May 02 02:07:34 PM PDT 24
Peak memory 232696 kb
Host smart-3390859e-23eb-4ebc-b2b2-b3c76e84374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406278890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2406278890
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3695613913
Short name T634
Test name
Test status
Simulation time 737342103 ps
CPU time 4.75 seconds
Started May 02 02:07:23 PM PDT 24
Finished May 02 02:07:29 PM PDT 24
Peak memory 223080 kb
Host smart-8cc8ccec-ad13-4213-a924-c216b1719329
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3695613913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3695613913
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2388718111
Short name T721
Test name
Test status
Simulation time 2353177158 ps
CPU time 26.46 seconds
Started May 02 02:07:29 PM PDT 24
Finished May 02 02:07:57 PM PDT 24
Peak memory 216348 kb
Host smart-b3a0d5d7-8fc1-469c-80c8-c0a2c553a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388718111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2388718111
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4070415411
Short name T539
Test name
Test status
Simulation time 7974782383 ps
CPU time 6.53 seconds
Started May 02 02:07:13 PM PDT 24
Finished May 02 02:07:21 PM PDT 24
Peak memory 216392 kb
Host smart-681882c1-766d-48f9-b533-69fff9ae1e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070415411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4070415411
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2118928206
Short name T663
Test name
Test status
Simulation time 50003959 ps
CPU time 1.03 seconds
Started May 02 02:07:24 PM PDT 24
Finished May 02 02:07:26 PM PDT 24
Peak memory 207164 kb
Host smart-e1d9e21e-ff04-42b7-9670-12d8e5a19b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118928206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2118928206
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2852098777
Short name T701
Test name
Test status
Simulation time 52433159 ps
CPU time 0.82 seconds
Started May 02 02:07:23 PM PDT 24
Finished May 02 02:07:25 PM PDT 24
Peak memory 205772 kb
Host smart-3ce44eea-397f-4446-8d91-ce494c6f3179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852098777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2852098777
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.751632771
Short name T492
Test name
Test status
Simulation time 15475178 ps
CPU time 0.73 seconds
Started May 02 02:07:32 PM PDT 24
Finished May 02 02:07:34 PM PDT 24
Peak memory 205396 kb
Host smart-1349a645-285a-4b1e-b4f0-a024cb5391d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751632771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.751632771
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2842947620
Short name T237
Test name
Test status
Simulation time 755145266 ps
CPU time 3.16 seconds
Started May 02 02:07:27 PM PDT 24
Finished May 02 02:07:31 PM PDT 24
Peak memory 218460 kb
Host smart-2c79798b-9d76-4647-b7b8-fb1b40cfa2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842947620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2842947620
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2432977236
Short name T459
Test name
Test status
Simulation time 53494048 ps
CPU time 0.87 seconds
Started May 02 02:07:22 PM PDT 24
Finished May 02 02:07:24 PM PDT 24
Peak memory 206668 kb
Host smart-7a214de5-2b24-4f38-8e1a-c8f1dfbc1c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432977236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2432977236
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.329573555
Short name T308
Test name
Test status
Simulation time 37682569855 ps
CPU time 75.19 seconds
Started May 02 02:07:31 PM PDT 24
Finished May 02 02:08:47 PM PDT 24
Peak memory 242932 kb
Host smart-54e4a962-1cb7-4d7f-99c6-b7fce8b93822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329573555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.329573555
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1910935080
Short name T206
Test name
Test status
Simulation time 4007395709 ps
CPU time 18.66 seconds
Started May 02 02:07:30 PM PDT 24
Finished May 02 02:07:51 PM PDT 24
Peak memory 223856 kb
Host smart-da6d0e01-5f2c-44a8-9459-46fc3945bd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910935080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1910935080
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.522133040
Short name T255
Test name
Test status
Simulation time 1592753165 ps
CPU time 11.11 seconds
Started May 02 02:07:27 PM PDT 24
Finished May 02 02:07:40 PM PDT 24
Peak memory 233516 kb
Host smart-2d55bf2b-e082-45d9-8888-a980e98e5902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522133040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.522133040
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.335785758
Short name T298
Test name
Test status
Simulation time 397145518 ps
CPU time 6.92 seconds
Started May 02 02:07:32 PM PDT 24
Finished May 02 02:07:41 PM PDT 24
Peak memory 234332 kb
Host smart-e7b69a64-03b0-408a-b8e4-b9cf09bde649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335785758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.335785758
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1841000021
Short name T112
Test name
Test status
Simulation time 1709794574 ps
CPU time 11.32 seconds
Started May 02 02:07:28 PM PDT 24
Finished May 02 02:07:41 PM PDT 24
Peak memory 222468 kb
Host smart-005dd59e-0a50-4ca3-96e0-70f50db1e4c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1841000021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1841000021
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4236169613
Short name T412
Test name
Test status
Simulation time 26675388202 ps
CPU time 19.11 seconds
Started May 02 02:07:26 PM PDT 24
Finished May 02 02:07:46 PM PDT 24
Peak memory 216356 kb
Host smart-cb6f8174-3480-48ab-b981-e0ddec93700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236169613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4236169613
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.878000735
Short name T584
Test name
Test status
Simulation time 3709873852 ps
CPU time 12.86 seconds
Started May 02 02:07:21 PM PDT 24
Finished May 02 02:07:35 PM PDT 24
Peak memory 216256 kb
Host smart-f41c9913-8847-43e2-8fef-1709e235b812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878000735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.878000735
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4092058105
Short name T546
Test name
Test status
Simulation time 136450433 ps
CPU time 1.25 seconds
Started May 02 02:07:28 PM PDT 24
Finished May 02 02:07:31 PM PDT 24
Peak memory 216260 kb
Host smart-1f1767c2-bef3-4f84-aac1-0d6c565db65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092058105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4092058105
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3834346369
Short name T728
Test name
Test status
Simulation time 494719319 ps
CPU time 1.12 seconds
Started May 02 02:07:28 PM PDT 24
Finished May 02 02:07:30 PM PDT 24
Peak memory 206828 kb
Host smart-b4b7f6e1-43b4-4c69-8d0b-0c302cf7cd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834346369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3834346369
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3134552971
Short name T436
Test name
Test status
Simulation time 52254379 ps
CPU time 0.7 seconds
Started May 02 02:07:37 PM PDT 24
Finished May 02 02:07:39 PM PDT 24
Peak memory 204876 kb
Host smart-fd6b3a35-b411-46de-aa65-e94f0486c4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134552971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
134552971
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1623163950
Short name T725
Test name
Test status
Simulation time 38145823 ps
CPU time 0.77 seconds
Started May 02 02:07:30 PM PDT 24
Finished May 02 02:07:33 PM PDT 24
Peak memory 206712 kb
Host smart-6449bd66-2e3c-43e6-b2e3-4cd1e963fbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623163950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1623163950
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3661978623
Short name T156
Test name
Test status
Simulation time 6750402078 ps
CPU time 95.98 seconds
Started May 02 02:07:38 PM PDT 24
Finished May 02 02:09:15 PM PDT 24
Peak memory 238052 kb
Host smart-7dc0c721-bfec-4c05-910d-84c3f0f6b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661978623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3661978623
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3699564430
Short name T334
Test name
Test status
Simulation time 2423211960 ps
CPU time 20.31 seconds
Started May 02 02:07:29 PM PDT 24
Finished May 02 02:07:51 PM PDT 24
Peak memory 224048 kb
Host smart-524e5fea-20d5-4ac2-b356-365d17b7ff8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699564430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3699564430
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2347433905
Short name T276
Test name
Test status
Simulation time 59152806922 ps
CPU time 28.48 seconds
Started May 02 02:07:27 PM PDT 24
Finished May 02 02:07:57 PM PDT 24
Peak memory 221744 kb
Host smart-e2c8685a-089d-4c48-acc9-4051d4bc565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347433905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2347433905
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3908269052
Short name T712
Test name
Test status
Simulation time 545689989 ps
CPU time 6.98 seconds
Started May 02 02:07:36 PM PDT 24
Finished May 02 02:07:44 PM PDT 24
Peak memory 223032 kb
Host smart-59d05c83-1c26-426f-9212-eec0d850bba4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3908269052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3908269052
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1319997905
Short name T410
Test name
Test status
Simulation time 5599371292 ps
CPU time 11.56 seconds
Started May 02 02:07:29 PM PDT 24
Finished May 02 02:07:42 PM PDT 24
Peak memory 216444 kb
Host smart-21012e09-60d6-4572-ae48-63585472c0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319997905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1319997905
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2101468309
Short name T524
Test name
Test status
Simulation time 21925011371 ps
CPU time 18.83 seconds
Started May 02 02:07:30 PM PDT 24
Finished May 02 02:07:50 PM PDT 24
Peak memory 216428 kb
Host smart-3f531ed5-bee9-40c4-bc01-c75633705311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101468309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2101468309
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2102914792
Short name T664
Test name
Test status
Simulation time 1522861865 ps
CPU time 3.26 seconds
Started May 02 02:07:30 PM PDT 24
Finished May 02 02:07:35 PM PDT 24
Peak memory 216348 kb
Host smart-05ef8f32-bf79-421c-b204-51e1e576761d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102914792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2102914792
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1164960810
Short name T579
Test name
Test status
Simulation time 19081403 ps
CPU time 0.74 seconds
Started May 02 02:07:26 PM PDT 24
Finished May 02 02:07:28 PM PDT 24
Peak memory 205780 kb
Host smart-d9249755-419b-4521-a954-815c7ee42166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164960810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1164960810
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.776032307
Short name T480
Test name
Test status
Simulation time 26313027 ps
CPU time 0.8 seconds
Started May 02 02:07:39 PM PDT 24
Finished May 02 02:07:41 PM PDT 24
Peak memory 204804 kb
Host smart-d8648c9f-4f79-4782-beaa-90bfcc05db9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776032307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.776032307
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.561572297
Short name T676
Test name
Test status
Simulation time 14228817 ps
CPU time 0.79 seconds
Started May 02 02:07:38 PM PDT 24
Finished May 02 02:07:40 PM PDT 24
Peak memory 206964 kb
Host smart-c17a5839-7238-41f8-97e1-6c8980318b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561572297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.561572297
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2002218527
Short name T311
Test name
Test status
Simulation time 1790189411 ps
CPU time 34.4 seconds
Started May 02 02:07:34 PM PDT 24
Finished May 02 02:08:10 PM PDT 24
Peak memory 232716 kb
Host smart-b1a3e7be-a894-4905-9027-003d85066e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002218527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2002218527
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2044266818
Short name T689
Test name
Test status
Simulation time 126584136 ps
CPU time 2.86 seconds
Started May 02 02:07:36 PM PDT 24
Finished May 02 02:07:40 PM PDT 24
Peak memory 222440 kb
Host smart-81f54161-e798-444b-a3b1-43daf28f0db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044266818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2044266818
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1858195471
Short name T708
Test name
Test status
Simulation time 92738890 ps
CPU time 3.12 seconds
Started May 02 02:07:34 PM PDT 24
Finished May 02 02:07:39 PM PDT 24
Peak memory 223968 kb
Host smart-e4b2410f-795f-4002-93f8-7ed1c9368d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858195471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1858195471
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2556555982
Short name T587
Test name
Test status
Simulation time 321765563 ps
CPU time 3.94 seconds
Started May 02 02:07:35 PM PDT 24
Finished May 02 02:07:41 PM PDT 24
Peak memory 222908 kb
Host smart-ca96ec68-2275-45c3-8276-77716b9e5b69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2556555982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2556555982
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2775606622
Short name T541
Test name
Test status
Simulation time 10896136646 ps
CPU time 28.05 seconds
Started May 02 02:07:36 PM PDT 24
Finished May 02 02:08:06 PM PDT 24
Peak memory 216460 kb
Host smart-6958964b-a52c-4f9d-a925-d0dbc97708e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775606622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2775606622
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.105514741
Short name T710
Test name
Test status
Simulation time 848762554 ps
CPU time 5.69 seconds
Started May 02 02:07:36 PM PDT 24
Finished May 02 02:07:43 PM PDT 24
Peak memory 216252 kb
Host smart-6f3db8d3-f39e-416e-b2cb-c4306f5ca597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105514741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.105514741
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.817042464
Short name T561
Test name
Test status
Simulation time 94696498 ps
CPU time 1.85 seconds
Started May 02 02:07:34 PM PDT 24
Finished May 02 02:07:38 PM PDT 24
Peak memory 216200 kb
Host smart-3be950f7-9acc-4178-9628-6b1f9045dac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817042464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.817042464
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.894559040
Short name T681
Test name
Test status
Simulation time 202956321 ps
CPU time 0.94 seconds
Started May 02 02:07:36 PM PDT 24
Finished May 02 02:07:38 PM PDT 24
Peak memory 206868 kb
Host smart-a462a9f2-c007-4bf3-ac67-f70e51cb148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894559040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.894559040
Directory /workspace/9.spi_device_tpm_sts_read/latest
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