Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	337656	1			T1	1		T2	1		T3	95
all_values[1]	337656	1			T1	1		T2	1		T3	95
all_values[2]	337656	1			T1	1		T2	1		T3	95
all_values[3]	337656	1			T1	1		T2	1		T3	95
all_values[4]	337656	1			T1	1		T2	1		T3	95
all_values[5]	337656	1			T1	1		T2	1		T3	95
all_values[6]	337656	1			T1	1		T2	1		T3	95
all_values[7]	337656	1			T1	1		T2	1		T3	95

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2698845

1

T1

8

T2

8

T3

760

auto[1]

2403

1

T33

86

T35

94

T42

100

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2699138

1

T1

8

T2

8

T3

757

auto[1]

2110

1

T3

3

T15

2

T16

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	337223	1			T1	1		T2	1		T3	95
all_values[0]	auto[0]	auto[1]	106	1			T33	5		T35	4		T42	2
all_values[0]	auto[1]	auto[0]	197	1			T33	8		T35	6		T42	8
all_values[0]	auto[1]	auto[1]	130	1			T33	3		T35	10		T42	4
all_values[1]	auto[0]	auto[0]	337246	1			T1	1		T2	1		T3	95
all_values[1]	auto[0]	auto[1]	113	1			T33	3		T35	4		T42	5
all_values[1]	auto[1]	auto[0]	177	1			T33	8		T35	4		T42	11
all_values[1]	auto[1]	auto[1]	120	1			T33	4		T35	7		T42	5
all_values[2]	auto[0]	auto[0]	337243	1			T1	1		T2	1		T3	95
all_values[2]	auto[0]	auto[1]	131	1			T33	3		T35	5		T42	9
all_values[2]	auto[1]	auto[0]	181	1			T33	3		T35	9		T42	1
all_values[2]	auto[1]	auto[1]	101	1			T33	2		T35	3		T42	3
all_values[3]	auto[0]	auto[0]	337242	1			T1	1		T2	1		T3	95
all_values[3]	auto[0]	auto[1]	143	1			T33	5		T162	4		T35	5
all_values[3]	auto[1]	auto[0]	169	1			T33	4		T35	7		T42	12
all_values[3]	auto[1]	auto[1]	102	1			T33	1		T35	3		T42	4
all_values[4]	auto[0]	auto[0]	337223	1			T1	1		T2	1		T3	95
all_values[4]	auto[0]	auto[1]	121	1			T33	1		T143	1		T303	7
all_values[4]	auto[1]	auto[0]	169	1			T33	12		T35	11		T42	7
all_values[4]	auto[1]	auto[1]	143	1			T33	3		T35	4		T42	7
all_values[5]	auto[0]	auto[0]	336995	1			T1	1		T2	1		T3	92
all_values[5]	auto[0]	auto[1]	353	1			T3	3		T15	2		T16	3
all_values[5]	auto[1]	auto[0]	211	1			T33	7		T35	7		T42	13
all_values[5]	auto[1]	auto[1]	97	1			T33	4		T42	2		T360	4
all_values[6]	auto[0]	auto[0]	337226	1			T1	1		T2	1		T3	95
all_values[6]	auto[0]	auto[1]	96	1			T33	1		T35	4		T42	4
all_values[6]	auto[1]	auto[0]	221	1			T33	10		T35	11		T42	8
all_values[6]	auto[1]	auto[1]	113	1			T33	6		T35	2		T42	8
all_values[7]	auto[0]	auto[0]	337253	1			T1	1		T2	1		T3	95
all_values[7]	auto[0]	auto[1]	131	1			T33	4		T35	1		T42	7
all_values[7]	auto[1]	auto[0]	162	1			T33	9		T35	6		T42	2
all_values[7]	auto[1]	auto[1]	110	1			T33	2		T35	4		T42	5