Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	32	52	61.90

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	3	33	91.67	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1092	1			T5	4		T6	10		T8	10
auto[SpiFlashAddrCfg]	758	1			T9	2		T11	5		T12	4
auto[SpiFlashAddr3b]	1028	1			T1	6		T4	8		T5	2
auto[SpiFlashAddr4b]	902	1			T1	2		T5	2		T6	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2928

1

T1

8

T4

8

T5

8

auto[1]

852

1

T6

12

T12

22

T66

32

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927

1

T1

2

T5

2

T6

4

auto[1]

1853

1

T1

6

T4

8

T5

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1475	1			T1	4		T5	4		T6	2
values[1]	84	1			T5	2		T9	2		T10	4
values[2]	161	1			T1	2		T9	2		T185	2
values[3]	166	1			T10	12		T185	4		T51	4
values[4]	164	1			T6	4		T25	2		T51	6
values[5]	181	1			T51	4		T52	4		T53	4
values[6]	157	1			T8	4		T9	2		T53	2
values[7]	211	1			T1	2		T4	8		T6	2
values[8]	1181	1			T5	2		T6	4		T8	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3180

1

T1

8

T5

8

T6

12

auto[1]

600

1

T4

8

T10

21

T11

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3650

1

T1

8

T4

8

T5

8

write

130

1

T9

2

T12

6

T66

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1672

1

T1

2

T4

8

T5

2

valids[0x1]

2108

1

T1

6

T5

6

T6

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	174	1			T5	2		T8	2		T12	2
internal_process_ops[0x5a]	184	1			T26	2		T68	2		T71	2
internal_process_ops[0x05]	214	1			T6	4		T26	2		T27	4
internal_process_ops[0x35]	222	1			T5	2		T6	2		T26	4
internal_process_ops[0x15]	188	1			T9	2		T12	2		T66	4
internal_process_ops[0x03]	222	1			T1	4		T9	2		T66	4
internal_process_ops[0x0b]	286	1			T1	2		T6	2		T10	4
internal_process_ops[0x3b]	227	1			T4	8		T8	2		T10	5
internal_process_ops[0x6b]	259	1			T8	2		T11	2		T12	2
internal_process_ops[0xbb]	265	1			T1	2		T5	2		T10	5
internal_process_ops[0xeb]	255	1			T5	2		T8	2		T10	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3720

1

T1

8

T4

8

T5

8

auto[1]

60

1

T12

6

T66

12

T67

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3780

1

T1

8

T4

8

T5

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

866

1

T5

4

T8

10

T9

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

206

1

T6

10

T12

4

T66

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

380

1

T9

2

T25

2

T68

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

146

1

T51

2

T53

4

T70

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

562

1

T1

6

T5

2

T8

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

210

1

T12

6

T66

4

T185

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

450

1

T1

2

T5

2

T8

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

230

1

T6

2

T12

6

T66

12

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

16

1

T9

2

T279

4

T223

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

4

1

T75

2

T78

2

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

30

1

T279

2

T223

4

T243

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

22

1

T12

4

T66

8

T74

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

14

1

T205

2

T262

4

T224

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

16

1

T73

2

T77

4

T264

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

10

1

T261

2

T256

2

T294

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

18

1

T12

2

T66

4

T67

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

180

1

T11

5

T82

5

T143

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

226

1

T4

8

T10

10

T82

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

194

1

T10

11

T143

3

T295

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	3	33	91.67	3

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	248	1			T8	8		T26	2		T68	6
auto[0]	values[0]	valids[0x1]	1168	1			T1	4		T5	4		T6	2
auto[0]	values[1]	valids[0x1]	78	1			T5	2		T9	2		T12	4
auto[0]	values[2]	valids[0x0]	60	1			T185	2		T186	2		T223	2
auto[0]	values[2]	valids[0x1]	54	1			T1	2		T9	2		T235	2
auto[0]	values[3]	valids[0x0]	58	1			T185	4		T51	4		T53	4
auto[0]	values[3]	valids[0x1]	52	1			T52	4		T69	2		T205	2
auto[0]	values[4]	valids[0x0]	68	1			T25	2		T51	6		T123	2
auto[0]	values[4]	valids[0x1]	58	1			T6	4		T74	6		T223	4
auto[0]	values[5]	valids[0x0]	70	1			T51	4		T52	4		T53	4
auto[0]	values[5]	valids[0x1]	60	1			T124	12		T253	2		T184	4
auto[0]	values[6]	valids[0x0]	72	1			T8	4		T189	2		T70	2
auto[0]	values[6]	valids[0x1]	62	1			T9	2		T53	2		T70	2
auto[0]	values[7]	valids[0x0]	62	1			T1	2		T12	2		T66	6
auto[0]	values[7]	valids[0x1]	76	1			T6	2		T12	2		T71	2
auto[0]	values[8]	valids[0x0]	612	1			T5	2		T8	6		T9	2
auto[0]	values[8]	valids[0x1]	322	1			T6	4		T66	4		T26	4
auto[1]	values[0]	valids[0x1]	59	1			T143	3		T295	7		T296	4
auto[1]	values[1]	valids[0x1]	6	1			T10	4		T297	2		-	-
auto[1]	values[2]	valids[0x0]	43	1			T298	4		T297	6		T296	7
auto[1]	values[2]	valids[0x1]	4	1			T299	4		-	-		-	-
auto[1]	values[3]	valids[0x0]	49	1			T10	12		T295	4		T300	3
auto[1]	values[3]	valids[0x1]	7	1			T301	3		T302	4		-	-
auto[1]	values[4]	valids[0x0]	28	1			T82	5		T295	3		T303	4
auto[1]	values[4]	valids[0x1]	10	1			T82	6		T304	4		-	-
auto[1]	values[5]	valids[0x0]	36	1			T298	4		T300	5		T305	3
auto[1]	values[5]	valids[0x1]	15	1			T305	4		T306	2		T307	4
auto[1]	values[6]	valids[0x0]	19	1			T308	5		T299	4		T309	3
auto[1]	values[6]	valids[0x1]	4	1			T303	4		-	-		-	-
auto[1]	values[7]	valids[0x0]	50	1			T4	8		T162	4		T310	3
auto[1]	values[7]	valids[0x1]	23	1			T295	2		T162	5		T298	5
auto[1]	values[8]	valids[0x0]	197	1			T10	5		T11	2		T82	4
auto[1]	values[8]	valids[0x1]	50	1			T11	3		T162	7		T297	2