Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1844905 1 T1 2261 T4 2735 T5 3389


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1690713 1 T1 2261 T4 2735 T5 2449
auto[1] 154192 1 T5 940 T26 1536 T27 9436


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 415308 1 T1 953 T4 170 T5 1174
auto[524288:1048575] 206492 1 T4 1172 T5 332 T10 8
auto[1048576:1572863] 229175 1 T1 9 T4 41 T5 631
auto[1572864:2097151] 214743 1 T1 298 T4 214 T5 130
auto[2097152:2621439] 191593 1 T1 32 T4 120 T5 384
auto[2621440:3145727] 178196 1 T1 201 T4 792 T5 268
auto[3145728:3670015] 190615 1 T1 768 T5 391 T10 1384
auto[3670016:4194303] 218783 1 T4 226 T5 79 T10 2650


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 168540 1 T1 25 T4 142 T5 1533
auto[1] 1676365 1 T1 2236 T4 2593 T5 1856


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1844905 1 T1 2261 T4 2735 T5 3389


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 309963 1 T1 953 T4 170 T5 275
auto[0] auto[0] auto[0:524287] auto[1] 105345 1 T5 899 T26 1536 T27 9436
auto[0] auto[0] auto[524288:1048575] auto[0] 200099 1 T4 1172 T5 332 T10 8
auto[0] auto[0] auto[524288:1048575] auto[1] 6393 1 T180 2 T181 2574 T113 655
auto[0] auto[0] auto[1048576:1572863] auto[0] 224051 1 T1 9 T4 41 T5 590
auto[0] auto[0] auto[1048576:1572863] auto[1] 5124 1 T5 41 T182 264 T86 1
auto[0] auto[0] auto[1572864:2097151] auto[0] 201489 1 T1 298 T4 214 T5 130
auto[0] auto[0] auto[1572864:2097151] auto[1] 13254 1 T86 1306 T180 256 T181 2598
auto[0] auto[0] auto[2097152:2621439] auto[0] 185961 1 T1 32 T4 120 T5 384
auto[0] auto[0] auto[2097152:2621439] auto[1] 5632 1 T86 472 T183 258 T113 20
auto[0] auto[0] auto[2621440:3145727] auto[0] 171140 1 T1 201 T4 792 T5 268
auto[0] auto[0] auto[2621440:3145727] auto[1] 7056 1 T182 2932 T184 255 T180 1
auto[0] auto[0] auto[3145728:3670015] auto[0] 184787 1 T1 768 T5 391 T10 1384
auto[0] auto[0] auto[3145728:3670015] auto[1] 5828 1 T182 2 T86 1 T180 1
auto[0] auto[0] auto[3670016:4194303] auto[0] 213223 1 T4 226 T5 79 T10 2650
auto[0] auto[0] auto[3670016:4194303] auto[1] 5560 1 T182 37 T86 850 T89 256


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 168540 1 T1 25 T4 142 T5 1533
auto[0] auto[0] auto[1] 1676365 1 T1 2236 T4 2593 T5 1856

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%