Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	31	97	75.78

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	31	97	75.78	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2328

1

T1

8

T5

8

T8

22

auto[1]

852

1

T6

12

T12

22

T66

32

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	402	1			T6	12		T79	14		T198	10
values[1]	292	1			T66	32		T205	10		T213	12
values[2]	436	1			T1	8		T12	22		T26	24
values[3]	308	1			T123	2		T189	4		T186	10
values[4]	300	1			T8	22		T86	10		T44	12
values[5]	724	1			T9	18		T27	14		T185	34
values[6]	442	1			T25	2		T68	22		T51	26
values[7]	276	1			T5	8		T70	20		T187	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	248	1			T26	24		T53	32		T189	4
values[1]	394	1			T5	8		T9	18		T51	26
values[2]	328	1			T6	12		T68	22		T28	26
values[3]	402	1			T1	8		T190	4		T22	20
values[4]	486	1			T70	20		T71	30		T67	26
values[5]	296	1			T123	2		T87	10		T184	16
values[6]	454	1			T12	22		T25	2		T253	18
values[7]	572	1			T8	22		T66	32		T27	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	31	97	75.78	31

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[4] , values[5]]	[values[0]]	--	--	2
[auto[0]]	[values[7]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[1]]	0	1	1
[auto[1]]	[values[0]]	[values[3]]	0	1	1
[auto[1]]	[values[0]]	[values[5]]	0	1	1
[auto[1]]	[values[1]]	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	6
[auto[1]]	[values[2]]	[values[1]]	0	1	1
[auto[1]]	[values[2]]	[values[5]]	0	1	1
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[2]]	0	1	1
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2]]	0	1	1
[auto[1]]	[values[6]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[2]]	0	1	1
[auto[1]]	[values[7]]	[values[5] , values[6]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	14	1			T79	14		-	-		-	-
auto[0]	values[0]	values[1]	28	1			T214	28		-	-		-	-
auto[0]	values[0]	values[2]	12	1			T276	12		-	-		-	-
auto[0]	values[0]	values[3]	62	1			T198	10		T241	10		T252	16
auto[0]	values[0]	values[4]	62	1			T218	2		T239	6		T173	2
auto[0]	values[0]	values[5]	54	1			T184	16		T273	28		T234	2
auto[0]	values[0]	values[6]	70	1			T262	26		T311	8		T312	36
auto[0]	values[0]	values[7]	14	1			T285	14		-	-		-	-
auto[0]	values[1]	values[0]	28	1			T195	10		T313	18		-	-
auto[0]	values[1]	values[1]	42	1			T219	14		T314	28		-	-
auto[0]	values[1]	values[2]	16	1			T213	12		T250	2		T315	2
auto[0]	values[1]	values[3]	42	1			T229	16		T316	26		-	-
auto[0]	values[1]	values[4]	4	1			T317	4		-	-		-	-
auto[0]	values[1]	values[5]	38	1			T210	10		T225	16		T318	12
auto[0]	values[1]	values[6]	28	1			T205	10		T199	2		T88	4
auto[0]	values[1]	values[7]	30	1			T319	2		T235	12		T320	12
auto[0]	values[2]	values[0]	24	1			T26	24		-	-		-	-
auto[0]	values[2]	values[1]	42	1			T321	20		T233	14		T322	2
auto[0]	values[2]	values[2]	2	1			T200	2		-	-		-	-
auto[0]	values[2]	values[3]	28	1			T1	8		T45	14		T216	6
auto[0]	values[2]	values[4]	30	1			T69	24		T270	6		-	-
auto[0]	values[2]	values[5]	10	1			T247	10		-	-		-	-
auto[0]	values[2]	values[6]	52	1			T181	8		T323	2		T282	32
auto[0]	values[2]	values[7]	56	1			T191	14		T202	6		T324	8
auto[0]	values[3]	values[0]	40	1			T189	4		T182	6		T113	12
auto[0]	values[3]	values[1]	22	1			T186	10		T325	12		-	-
auto[0]	values[3]	values[2]	100	1			T279	34		T251	6		T24	12
auto[0]	values[3]	values[3]	22	1			T201	22		-	-		-	-
auto[0]	values[3]	values[4]	10	1			T237	2		T326	8		-	-
auto[0]	values[3]	values[5]	34	1			T123	2		T284	6		T227	20
auto[0]	values[3]	values[6]	12	1			T327	4		T46	8		-	-
auto[0]	values[3]	values[7]	24	1			T328	24		-	-		-	-
auto[0]	values[4]	values[1]	76	1			T246	22		T294	24		T329	18
auto[0]	values[4]	values[2]	10	1			T254	6		T212	4		-	-
auto[0]	values[4]	values[3]	48	1			T86	10		T286	14		T330	22
auto[0]	values[4]	values[4]	14	1			T208	2		T226	4		T331	4
auto[0]	values[4]	values[5]	38	1			T44	12		T183	2		T89	10
auto[0]	values[4]	values[6]	8	1			T332	6		T222	2		-	-
auto[0]	values[4]	values[7]	64	1			T8	22		T85	4		T221	38
auto[0]	values[5]	values[1]	84	1			T9	18		T209	4		T23	4
auto[0]	values[5]	values[2]	16	1			T333	16		-	-		-	-
auto[0]	values[5]	values[3]	62	1			T22	20		T176	16		T334	26
auto[0]	values[5]	values[4]	42	1			T280	8		T274	12		T335	22
auto[0]	values[5]	values[5]	44	1			T87	10		T281	2		T336	4
auto[0]	values[5]	values[6]	116	1			T253	18		T192	22		T206	20
auto[0]	values[5]	values[7]	84	1			T27	14		T54	2		T56	10
auto[0]	values[6]	values[0]	26	1			T240	8		T337	18		-	-
auto[0]	values[6]	values[1]	12	1			T338	12		-	-		-	-
auto[0]	values[6]	values[2]	78	1			T68	22		T28	26		T180	8
auto[0]	values[6]	values[3]	22	1			T97	6		T339	16		-	-
auto[0]	values[6]	values[4]	82	1			T124	30		T340	4		T341	34
auto[0]	values[6]	values[5]	32	1			T81	16		T342	8		T289	8
auto[0]	values[6]	values[6]	56	1			T25	2		T243	30		T257	24
auto[0]	values[6]	values[7]	74	1			T52	8		T7	4		T80	8
auto[0]	values[7]	values[0]	22	1			T343	2		T260	20		-	-
auto[0]	values[7]	values[1]	30	1			T5	8		T187	4		T344	10
auto[0]	values[7]	values[2]	12	1			T116	12		-	-		-	-
auto[0]	values[7]	values[3]	4	1			T345	4		-	-		-	-
auto[0]	values[7]	values[4]	32	1			T171	16		T228	16		-	-
auto[0]	values[7]	values[6]	28	1			T346	28		-	-		-	-
auto[0]	values[7]	values[7]	60	1			T223	24		T272	10		T230	26
auto[1]	values[0]	values[0]	6	1			T207	6		-	-		-	-
auto[1]	values[0]	values[2]	30	1			T6	12		T347	18		-	-
auto[1]	values[0]	values[4]	26	1			T348	26		-	-		-	-
auto[1]	values[0]	values[6]	8	1			T75	8		-	-		-	-
auto[1]	values[0]	values[7]	16	1			T264	16		-	-		-	-
auto[1]	values[1]	values[0]	32	1			T349	32		-	-		-	-
auto[1]	values[1]	values[7]	32	1			T66	32		-	-		-	-
auto[1]	values[2]	values[0]	12	1			T245	12		-	-		-	-
auto[1]	values[2]	values[2]	52	1			T78	4		T291	16		T350	32
auto[1]	values[2]	values[3]	46	1			T77	28		T211	18		-	-
auto[1]	values[2]	values[4]	28	1			T67	26		T293	2		-	-
auto[1]	values[2]	values[6]	22	1			T12	22		-	-		-	-
auto[1]	values[2]	values[7]	32	1			T72	16		T193	16		-	-
auto[1]	values[3]	values[1]	2	1			T351	2		-	-		-	-
auto[1]	values[3]	values[4]	32	1			T71	30		T76	2		-	-
auto[1]	values[3]	values[6]	6	1			T217	6		-	-		-	-
auto[1]	values[3]	values[7]	4	1			T352	4		-	-		-	-
auto[1]	values[4]	values[3]	2	1			T203	2		-	-		-	-
auto[1]	values[4]	values[4]	20	1			T292	20		-	-		-	-
auto[1]	values[4]	values[5]	2	1			T267	2		-	-		-	-
auto[1]	values[4]	values[6]	18	1			T288	18		-	-		-	-
auto[1]	values[5]	values[0]	44	1			T53	32		T269	12		-	-
auto[1]	values[5]	values[1]	24	1			T231	24		-	-		-	-
auto[1]	values[5]	values[3]	40	1			T190	4		T188	18		T197	18
auto[1]	values[5]	values[4]	44	1			T74	12		T353	32		-	-
auto[1]	values[5]	values[5]	32	1			T290	32		-	-		-	-
auto[1]	values[5]	values[6]	30	1			T354	30		-	-		-	-
auto[1]	values[5]	values[7]	62	1			T185	34		T238	28		-	-
auto[1]	values[6]	values[1]	26	1			T51	26		-	-		-	-
auto[1]	values[6]	values[3]	4	1			T249	4		-	-		-	-
auto[1]	values[6]	values[4]	18	1			T73	6		T355	12		-	-
auto[1]	values[6]	values[5]	12	1			T259	12		-	-		-	-
auto[1]	values[7]	values[1]	6	1			T271	6		-	-		-	-
auto[1]	values[7]	values[3]	20	1			T248	20		-	-		-	-
auto[1]	values[7]	values[4]	42	1			T70	20		T356	22		-	-
auto[1]	values[7]	values[7]	20	1			T215	20		-	-		-	-