Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
dashboard | hierarchy | modlist | groups | tests | asserts


Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 66 0 66 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_filtered 2 0 2 100.00 100 1 1 2
cp_opcode 64 0 64 100.00 100 1 1 64


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_filtered

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_filtered

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1590 1 T1 4 T5 4 T6 6
auto[1] 2190 1 T1 4 T4 8 T5 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 64 0 64 100.00


Automatically Generated Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] 246 1 T1 4 T9 6 T66 4
auto[4:7] 260 1 T6 4 T9 2 T26 2
auto[8:11] 296 1 T1 2 T6 6 T10 4
auto[12:15] 14 1 T188 2 T76 2 T256 2
auto[16:19] 8 1 T321 2 T330 4 T294 2
auto[20:23] 192 1 T9 2 T12 2 T66 4
auto[24:27] 28 1 T66 8 T51 2 T71 6
auto[28:31] 20 1 T66 2 T70 6 T320 6
auto[32:35] 18 1 T75 2 T192 4 T238 4
auto[36:39] 20 1 T213 4 T244 6 T77 4
auto[40:43] 8 1 T29 4 T171 4 - -
auto[44:47] 22 1 T66 6 T69 8 T199 2
auto[48:51] 10 1 T243 2 T349 2 T272 2
auto[52:55] 240 1 T5 2 T6 2 T26 4
auto[56:59] 237 1 T4 8 T8 2 T10 5
auto[60:63] 20 1 T9 2 T53 2 T71 2
auto[64:67] 46 1 T12 2 T66 4 T68 2
auto[68:71] 22 1 T9 2 T190 2 T279 2
auto[72:75] 16 1 T70 2 T342 2 T349 4
auto[76:79] 10 1 T223 2 T294 4 T312 2
auto[80:83] 18 1 T56 4 T186 4 T75 2
auto[84:87] 16 1 T12 4 T124 2 T77 2
auto[88:91] 196 1 T26 2 T68 2 T71 2
auto[92:95] 10 1 T28 2 T78 2 T241 2
auto[96:99] 16 1 T8 2 T9 2 T7 2
auto[100:103] 6 1 T185 4 T53 2 - -
auto[104:107] 271 1 T8 2 T11 2 T12 2
auto[108:111] 18 1 T28 4 T74 2 T209 2
auto[112:115] 18 1 T12 4 T186 2 T273 4
auto[116:119] 28 1 T185 2 T70 2 T243 2
auto[120:123] 18 1 T9 2 T53 4 T225 8
auto[124:127] 14 1 T248 4 T279 4 T354 6
auto[128:131] 4 1 T261 2 T347 2 - -
auto[132:135] 28 1 T286 4 T77 8 T215 4
auto[136:139] 26 1 T124 2 T248 2 T243 6
auto[140:143] 22 1 T8 4 T69 2 T279 2
auto[144:147] 8 1 T123 2 T279 4 T335 2
auto[148:151] 16 1 T79 2 T213 2 T73 2
auto[152:155] 36 1 T53 4 T67 8 T74 2
auto[156:159] 190 1 T5 2 T8 2 T12 2
auto[160:163] 10 1 T221 6 T290 4 - -
auto[164:167] 14 1 T69 2 T262 2 T204 2
auto[168:171] 6 1 T227 4 T335 2 - -
auto[172:175] 26 1 T26 4 T192 2 T288 2
auto[176:179] 28 1 T25 2 T53 2 T248 4
auto[180:183] 102 1 T8 8 T26 2 T27 4
auto[184:187] 271 1 T1 2 T5 2 T10 5
auto[188:191] 34 1 T124 12 T279 4 T209 2
auto[192:195] 16 1 T12 4 T53 2 T213 2
auto[196:199] 8 1 T245 2 T193 4 T242 2
auto[200:203] 22 1 T68 2 T251 4 T249 2
auto[204:207] 10 1 T72 2 T213 2 T273 2
auto[208:211] 20 1 T79 2 T205 2 T279 2
auto[212:215] 22 1 T185 2 T273 8 T204 2
auto[216:219] 26 1 T51 4 T67 2 T223 4
auto[220:223] 34 1 T66 4 T53 2 T288 4
auto[224:227] 12 1 T53 2 T186 2 T253 2
auto[228:231] 28 1 T243 4 T259 4 T237 2
auto[232:235] 327 1 T5 2 T8 2 T10 7
auto[236:239] 26 1 T262 4 T217 2 T211 2
auto[240:243] 6 1 T264 2 T347 2 T268 2
auto[244:247] 18 1 T71 4 T73 2 T320 2
auto[248:251] 8 1 T72 2 T253 2 T73 2
auto[252:255] 14 1 T51 4 T262 2 T241 2



Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_opcodecp_filteredCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] auto[0] 86 1 T1 2 T9 3 T66 2
auto[0:3] auto[1] 160 1 T1 2 T9 3 T66 2
auto[4:7] auto[0] 130 1 T6 2 T9 1 T26 1
auto[4:7] auto[1] 130 1 T6 2 T9 1 T26 1
auto[8:11] auto[0] 96 1 T1 1 T6 3 T12 1
auto[8:11] auto[1] 200 1 T1 1 T6 3 T10 4
auto[12:15] auto[0] 7 1 T188 1 T76 1 T256 1
auto[12:15] auto[1] 7 1 T188 1 T76 1 T256 1
auto[16:19] auto[0] 4 1 T321 1 T330 2 T294 1
auto[16:19] auto[1] 4 1 T321 1 T330 2 T294 1
auto[20:23] auto[0] 96 1 T9 1 T12 1 T66 2
auto[20:23] auto[1] 96 1 T9 1 T12 1 T66 2
auto[24:27] auto[0] 14 1 T66 4 T51 1 T71 3
auto[24:27] auto[1] 14 1 T66 4 T51 1 T71 3
auto[28:31] auto[0] 10 1 T66 1 T70 3 T320 3
auto[28:31] auto[1] 10 1 T66 1 T70 3 T320 3
auto[32:35] auto[0] 9 1 T75 1 T192 2 T238 2
auto[32:35] auto[1] 9 1 T75 1 T192 2 T238 2
auto[36:39] auto[0] 10 1 T213 2 T244 3 T77 2
auto[36:39] auto[1] 10 1 T213 2 T244 3 T77 2
auto[40:43] auto[0] 4 1 T29 2 T171 2 - -
auto[40:43] auto[1] 4 1 T29 2 T171 2 - -
auto[44:47] auto[0] 11 1 T66 3 T69 4 T199 1
auto[44:47] auto[1] 11 1 T66 3 T69 4 T199 1
auto[48:51] auto[0] 5 1 T243 1 T349 1 T272 1
auto[48:51] auto[1] 5 1 T243 1 T349 1 T272 1
auto[52:55] auto[0] 120 1 T5 1 T6 1 T26 2
auto[52:55] auto[1] 120 1 T5 1 T6 1 T26 2
auto[56:59] auto[0] 66 1 T8 1 T53 1 T56 2
auto[56:59] auto[1] 171 1 T4 8 T8 1 T10 5
auto[60:63] auto[0] 10 1 T9 1 T53 1 T71 1
auto[60:63] auto[1] 10 1 T9 1 T53 1 T71 1
auto[64:67] auto[0] 23 1 T12 1 T66 2 T68 1
auto[64:67] auto[1] 23 1 T12 1 T66 2 T68 1
auto[68:71] auto[0] 11 1 T9 1 T190 1 T279 1
auto[68:71] auto[1] 11 1 T9 1 T190 1 T279 1
auto[72:75] auto[0] 8 1 T70 1 T342 1 T349 2
auto[72:75] auto[1] 8 1 T70 1 T342 1 T349 2
auto[76:79] auto[0] 5 1 T223 1 T294 2 T312 1
auto[76:79] auto[1] 5 1 T223 1 T294 2 T312 1
auto[80:83] auto[0] 9 1 T56 2 T186 2 T75 1
auto[80:83] auto[1] 9 1 T56 2 T186 2 T75 1
auto[84:87] auto[0] 8 1 T12 2 T124 1 T77 1
auto[84:87] auto[1] 8 1 T12 2 T124 1 T77 1
auto[88:91] auto[0] 98 1 T26 1 T68 1 T71 1
auto[88:91] auto[1] 98 1 T26 1 T68 1 T71 1
auto[92:95] auto[0] 5 1 T28 1 T78 1 T241 1
auto[92:95] auto[1] 5 1 T28 1 T78 1 T241 1
auto[96:99] auto[0] 8 1 T8 1 T9 1 T7 1
auto[96:99] auto[1] 8 1 T8 1 T9 1 T7 1
auto[100:103] auto[0] 3 1 T185 2 T53 1 - -
auto[100:103] auto[1] 3 1 T185 2 T53 1 - -
auto[104:107] auto[0] 87 1 T8 1 T12 1 T68 3
auto[104:107] auto[1] 184 1 T8 1 T11 2 T12 1
auto[108:111] auto[0] 9 1 T28 2 T74 1 T209 1
auto[108:111] auto[1] 9 1 T28 2 T74 1 T209 1
auto[112:115] auto[0] 9 1 T12 2 T186 1 T273 2
auto[112:115] auto[1] 9 1 T12 2 T186 1 T273 2
auto[116:119] auto[0] 14 1 T185 1 T70 1 T243 1
auto[116:119] auto[1] 14 1 T185 1 T70 1 T243 1
auto[120:123] auto[0] 9 1 T9 1 T53 2 T225 4
auto[120:123] auto[1] 9 1 T9 1 T53 2 T225 4
auto[124:127] auto[0] 7 1 T248 2 T279 2 T354 3
auto[124:127] auto[1] 7 1 T248 2 T279 2 T354 3
auto[128:131] auto[0] 2 1 T261 1 T347 1 - -
auto[128:131] auto[1] 2 1 T261 1 T347 1 - -
auto[132:135] auto[0] 14 1 T286 2 T77 4 T215 2
auto[132:135] auto[1] 14 1 T286 2 T77 4 T215 2
auto[136:139] auto[0] 13 1 T124 1 T248 1 T243 3
auto[136:139] auto[1] 13 1 T124 1 T248 1 T243 3
auto[140:143] auto[0] 11 1 T8 2 T69 1 T279 1
auto[140:143] auto[1] 11 1 T8 2 T69 1 T279 1
auto[144:147] auto[0] 4 1 T123 1 T279 2 T335 1
auto[144:147] auto[1] 4 1 T123 1 T279 2 T335 1
auto[148:151] auto[0] 8 1 T79 1 T213 1 T73 1
auto[148:151] auto[1] 8 1 T79 1 T213 1 T73 1
auto[152:155] auto[0] 18 1 T53 2 T67 4 T74 1
auto[152:155] auto[1] 18 1 T53 2 T67 4 T74 1
auto[156:159] auto[0] 95 1 T5 1 T8 1 T12 1
auto[156:159] auto[1] 95 1 T5 1 T8 1 T12 1
auto[160:163] auto[0] 5 1 T221 3 T290 2 - -
auto[160:163] auto[1] 5 1 T221 3 T290 2 - -
auto[164:167] auto[0] 7 1 T69 1 T262 1 T204 1
auto[164:167] auto[1] 7 1 T69 1 T262 1 T204 1
auto[168:171] auto[0] 3 1 T227 2 T335 1 - -
auto[168:171] auto[1] 3 1 T227 2 T335 1 - -
auto[172:175] auto[0] 13 1 T26 2 T192 1 T288 1
auto[172:175] auto[1] 13 1 T26 2 T192 1 T288 1
auto[176:179] auto[0] 14 1 T25 1 T53 1 T248 2
auto[176:179] auto[1] 14 1 T25 1 T53 1 T248 2
auto[180:183] auto[0] 51 1 T8 4 T26 1 T27 2
auto[180:183] auto[1] 51 1 T8 4 T26 1 T27 2
auto[184:187] auto[0] 71 1 T1 1 T5 1 T185 1
auto[184:187] auto[1] 200 1 T1 1 T5 1 T10 5
auto[188:191] auto[0] 17 1 T124 6 T279 2 T209 1
auto[188:191] auto[1] 17 1 T124 6 T279 2 T209 1
auto[192:195] auto[0] 8 1 T12 2 T53 1 T213 1
auto[192:195] auto[1] 8 1 T12 2 T53 1 T213 1
auto[196:199] auto[0] 4 1 T245 1 T193 2 T242 1
auto[196:199] auto[1] 4 1 T245 1 T193 2 T242 1
auto[200:203] auto[0] 11 1 T68 1 T251 2 T249 1
auto[200:203] auto[1] 11 1 T68 1 T251 2 T249 1
auto[204:207] auto[0] 5 1 T72 1 T213 1 T273 1
auto[204:207] auto[1] 5 1 T72 1 T213 1 T273 1
auto[208:211] auto[0] 10 1 T79 1 T205 1 T279 1
auto[208:211] auto[1] 10 1 T79 1 T205 1 T279 1
auto[212:215] auto[0] 11 1 T185 1 T273 4 T204 1
auto[212:215] auto[1] 11 1 T185 1 T273 4 T204 1
auto[216:219] auto[0] 13 1 T51 2 T67 1 T223 2
auto[216:219] auto[1] 13 1 T51 2 T67 1 T223 2
auto[220:223] auto[0] 17 1 T66 2 T53 1 T288 2
auto[220:223] auto[1] 17 1 T66 2 T53 1 T288 2
auto[224:227] auto[0] 6 1 T53 1 T186 1 T253 1
auto[224:227] auto[1] 6 1 T53 1 T186 1 T253 1
auto[228:231] auto[0] 14 1 T243 2 T259 2 T237 1
auto[228:231] auto[1] 14 1 T243 2 T259 2 T237 1
auto[232:235] auto[0] 118 1 T5 1 T8 1 T27 1
auto[232:235] auto[1] 209 1 T5 1 T8 1 T10 7
auto[236:239] auto[0] 13 1 T262 2 T217 1 T211 1
auto[236:239] auto[1] 13 1 T262 2 T217 1 T211 1
auto[240:243] auto[0] 3 1 T264 1 T347 1 T268 1
auto[240:243] auto[1] 3 1 T264 1 T347 1 T268 1
auto[244:247] auto[0] 9 1 T71 2 T73 1 T320 1
auto[244:247] auto[1] 9 1 T71 2 T73 1 T320 1
auto[248:251] auto[0] 4 1 T72 1 T253 1 T73 1
auto[248:251] auto[1] 4 1 T72 1 T253 1 T73 1
auto[252:255] auto[0] 7 1 T51 2 T262 1 T241 1
auto[252:255] auto[1] 7 1 T51 2 T262 1 T241 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%