Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	6	54	90.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	6	54	90.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	116	1			T1	2		T5	2		T52	2
auto[ReadAddrCrossIntoMailbox]	36	1			T81	4		T220	4		T357	4
auto[ReadAddrCrossOutOfMailbox]	30	1			T81	2		T220	4		T357	2
auto[ReadAddrCrossAllMailbox]	38	1			T52	4		T81	4		T357	2
auto[ReadAddrOutsideMailbox]	682	1			T1	6		T6	2		T8	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

451

1

T1

4

T5

1

T6

1

auto[1]

451

1

T1

4

T5

1

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	144	1			T1	4		T9	2		T66	4
read_ops[0x0b]	182	1			T1	2		T6	2		T12	2
read_ops[0x3b]	122	1			T8	2		T53	2		T56	4
read_ops[0x6b]	162	1			T8	2		T12	2		T68	4
read_ops[0xbb]	134	1			T1	2		T5	2		T185	2
read_ops[0xeb]	158	1			T8	2		T185	4		T51	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x03]]	[auto[ReadAddrCrossOutOfMailbox] , auto[ReadAddrCrossAllMailbox]]	*	--	--	4
[read_ops[0x3b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T246	3		T216	1		T266	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T246	3		T216	1		T266	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T216	1		T266	1		T358	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T216	1		T266	1		T358	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	61	1			T1	2		T9	1		T66	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T1	2		T9	1		T66	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	10	1			T52	1		T210	2		T246	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	10	1			T52	1		T210	2		T246	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T81	2		T220	1		T266	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T81	2		T220	1		T266	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T220	1		T278	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T220	1		T278	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T344	2		T196	3		T278	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T344	2		T196	3		T278	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	69	1			T1	1		T6	1		T12	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	69	1			T1	1		T6	1		T12	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T45	2		T195	1		T337	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T45	2		T195	1		T337	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T214	1		T194	1		T359	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T214	1		T194	1		T359	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T214	1		T359	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T214	1		T359	1		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	46	1			T8	1		T53	1		T56	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	46	1			T8	1		T53	1		T56	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	10	1			T220	2		T195	1		T214	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	10	1			T220	2		T195	1		T214	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T220	1		T214	1		T194	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T220	1		T214	1		T194	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T81	1		T214	1		T266	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T81	1		T214	1		T266	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T81	2		T194	1		T278	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T81	2		T194	1		T278	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	59	1			T8	1		T12	1		T68	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	59	1			T8	1		T12	1		T68	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T1	1		T5	1		T194	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T1	1		T5	1		T194	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T214	3		T194	1		T278	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T214	3		T194	1		T278	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T214	1		T194	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T214	1		T194	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T52	2		T357	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T52	2		T357	1		T214	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	48	1			T185	1		T70	1		T71	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	48	1			T185	1		T70	1		T71	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	15	1			T235	1		T239	1		T220	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	15	1			T235	1		T239	1		T220	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T357	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T357	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T220	1		T357	1		T266	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T220	1		T357	1		T266	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T266	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T266	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	58	1			T8	1		T185	2		T51	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	58	1			T8	1		T185	2		T51	1