Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	337656	1			T1	1		T2	1		T3	95
all_pins[1]	337656	1			T1	1		T2	1		T3	95
all_pins[2]	337656	1			T1	1		T2	1		T3	95
all_pins[3]	337656	1			T1	1		T2	1		T3	95
all_pins[4]	337656	1			T1	1		T2	1		T3	95
all_pins[5]	337656	1			T1	1		T2	1		T3	95
all_pins[6]	337656	1			T1	1		T2	1		T3	95
all_pins[7]	337656	1			T1	1		T2	1		T3	95

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2700332	1			T1	8		T2	8		T3	760
values[0x1]	916	1			T33	25		T35	33		T42	38
transitions[0x0=>0x1]	688	1			T33	20		T35	27		T42	27
transitions[0x1=>0x0]	700	1			T33	20		T35	27		T42	28

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	337526	1			T1	1		T2	1		T3	95
all_pins[0]	values[0x1]	130	1			T33	3		T35	10		T42	4
all_pins[0]	transitions[0x0=>0x1]	90	1			T33	1		T35	9		T42	3
all_pins[0]	transitions[0x1=>0x0]	80	1			T33	2		T35	6		T42	4
all_pins[1]	values[0x0]	337536	1			T1	1		T2	1		T3	95
all_pins[1]	values[0x1]	120	1			T33	4		T35	7		T42	5
all_pins[1]	transitions[0x0=>0x1]	91	1			T33	4		T35	7		T42	5
all_pins[1]	transitions[0x1=>0x0]	72	1			T33	2		T35	3		T42	3
all_pins[2]	values[0x0]	337555	1			T1	1		T2	1		T3	95
all_pins[2]	values[0x1]	101	1			T33	2		T35	3		T42	3
all_pins[2]	transitions[0x0=>0x1]	85	1			T33	2		T35	3		T42	2
all_pins[2]	transitions[0x1=>0x0]	86	1			T33	1		T35	3		T42	3
all_pins[3]	values[0x0]	337554	1			T1	1		T2	1		T3	95
all_pins[3]	values[0x1]	102	1			T33	1		T35	3		T42	4
all_pins[3]	transitions[0x0=>0x1]	70	1			T33	1		T35	1		T42	2
all_pins[3]	transitions[0x1=>0x0]	111	1			T33	3		T35	2		T42	5
all_pins[4]	values[0x0]	337513	1			T1	1		T2	1		T3	95
all_pins[4]	values[0x1]	143	1			T33	3		T35	4		T42	7
all_pins[4]	transitions[0x0=>0x1]	118	1			T33	3		T35	4		T42	6
all_pins[4]	transitions[0x1=>0x0]	72	1			T33	4		T42	1		T360	3
all_pins[5]	values[0x0]	337559	1			T1	1		T2	1		T3	95
all_pins[5]	values[0x1]	97	1			T33	4		T42	2		T360	4
all_pins[5]	transitions[0x0=>0x1]	78	1			T33	2		T360	3		T166	2
all_pins[5]	transitions[0x1=>0x0]	94	1			T33	4		T35	2		T42	6
all_pins[6]	values[0x0]	337543	1			T1	1		T2	1		T3	95
all_pins[6]	values[0x1]	113	1			T33	6		T35	2		T42	8
all_pins[6]	transitions[0x0=>0x1]	81	1			T33	5		T35	1		T42	6
all_pins[6]	transitions[0x1=>0x0]	78	1			T33	1		T35	3		T42	3
all_pins[7]	values[0x0]	337546	1			T1	1		T2	1		T3	95
all_pins[7]	values[0x1]	110	1			T33	2		T35	4		T42	5
all_pins[7]	transitions[0x0=>0x1]	75	1			T33	2		T35	2		T42	3
all_pins[7]	transitions[0x1=>0x0]	107	1			T33	3		T35	8		T42	3