Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
63.70	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	53	75	58.59

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	53	75	58.59	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	534	1			T68	22		T53	32		T56	10
values[1]	372	1			T71	30		T79	14		T182	6
values[2]	406	1			T25	2		T51	26		T54	2
values[3]	406	1			T1	8		T66	32		T124	30
values[4]	412	1			T5	8		T9	18		T26	24
values[5]	384	1			T6	12		T12	22		T185	34
values[6]	212	1			T186	10		T187	4		T7	4
values[7]	454	1			T8	22		T27	14		T70	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	394	1			T9	18		T25	2		T68	22
values[1]	432	1			T51	26		T54	2		T188	18
values[2]	390	1			T26	24		T52	8		T189	4
values[3]	364	1			T53	32		T56	10		T186	10
values[4]	376	1			T5	8		T12	22		T190	4
values[5]	420	1			T1	8		T6	12		T86	10
values[6]	470	1			T8	22		T27	14		T185	34
values[7]	334	1			T66	32		T70	20		T69	24

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3120

1

T1

8

T5

8

T6

12

auto[1]

60

1

T12

6

T66

12

T67

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	53	75	58.59	53

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1]]	*	--	--	8
[auto[1]]	[values[7]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[values[4]]	0	1	1
[auto[0]]	[values[3]]	[values[2]]	0	1	1
[auto[0]]	[values[4]]	[values[7]]	0	1	1
[auto[0]]	[values[6]]	[values[6]]	0	1	1
[auto[0]]	[values[7]]	[values[3]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	6
[auto[1]]	[values[2]]	[values[0]]	0	1	1
[auto[1]]	[values[2]]	[values[2] , values[3] , values[4] , values[5]]	--	--	4
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[3]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[4]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[4]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[5]]	[values[1]]	0	1	1
[auto[1]]	[values[5]]	[values[3]]	0	1	1
[auto[1]]	[values[5]]	[values[5]]	0	1	1
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[6]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	72	1			T68	22		T123	2		T191	14
auto[0]	values[0]	values[1]	60	1			T192	22		T193	16		T46	8
auto[0]	values[0]	values[2]	60	1			T97	6		T113	12		T194	24
auto[0]	values[0]	values[3]	108	1			T53	32		T56	10		T181	8
auto[0]	values[0]	values[4]	10	1			T195	10		-	-		-	-
auto[0]	values[0]	values[5]	42	1			T86	10		T196	14		T197	18
auto[0]	values[0]	values[6]	134	1			T72	14		T198	10		T88	4
auto[0]	values[0]	values[7]	42	1			T199	2		T77	24		T171	16
auto[0]	values[1]	values[0]	34	1			T87	10		T200	2		T201	22
auto[0]	values[1]	values[1]	52	1			T202	6		T203	2		T204	18
auto[0]	values[1]	values[2]	108	1			T205	10		T206	20		T207	6
auto[0]	values[1]	values[3]	60	1			T79	14		T208	2		T209	4
auto[0]	values[1]	values[5]	42	1			T210	10		T211	18		T212	4
auto[0]	values[1]	values[6]	36	1			T71	30		T182	6		-	-
auto[0]	values[1]	values[7]	40	1			T213	12		T214	28		-	-
auto[0]	values[2]	values[0]	46	1			T25	2		T215	20		T216	6
auto[0]	values[2]	values[1]	66	1			T51	26		T54	2		T217	6
auto[0]	values[2]	values[2]	16	1			T218	2		T219	14		-	-
auto[0]	values[2]	values[3]	72	1			T220	24		T221	38		T222	2
auto[0]	values[2]	values[4]	72	1			T223	24		T224	20		T225	16
auto[0]	values[2]	values[5]	48	1			T85	4		T226	4		T227	20
auto[0]	values[2]	values[6]	20	1			T73	4		T228	16		-	-
auto[0]	values[2]	values[7]	56	1			T78	2		T229	16		T230	26
auto[0]	values[3]	values[0]	28	1			T231	24		T232	4		-	-
auto[0]	values[3]	values[1]	20	1			T75	6		T233	14		-	-
auto[0]	values[3]	values[3]	2	1			T234	2		-	-		-	-
auto[0]	values[3]	values[4]	86	1			T28	26		T235	12		T236	12
auto[0]	values[3]	values[5]	100	1			T1	8		T237	2		T238	28
auto[0]	values[3]	values[6]	70	1			T124	30		T239	6		T240	8
auto[0]	values[3]	values[7]	84	1			T66	20		T241	10		T242	28
auto[0]	values[4]	values[0]	126	1			T9	18		T243	30		T244	30
auto[0]	values[4]	values[1]	106	1			T188	18		T245	10		T246	22
auto[0]	values[4]	values[2]	52	1			T26	24		T189	4		T247	10
auto[0]	values[4]	values[3]	26	1			T248	20		T249	4		T250	2
auto[0]	values[4]	values[4]	56	1			T5	8		T251	6		T252	16
auto[0]	values[4]	values[5]	14	1			T45	14		-	-		-	-
auto[0]	values[4]	values[6]	26	1			T253	18		T254	6		T255	2
auto[0]	values[5]	values[0]	42	1			T184	16		T74	10		T256	6
auto[0]	values[5]	values[1]	30	1			T257	24		T258	6		-	-
auto[0]	values[5]	values[2]	26	1			T52	8		T67	18		-	-
auto[0]	values[5]	values[3]	32	1			T259	12		T260	20		-	-
auto[0]	values[5]	values[4]	94	1			T12	16		T22	20		T261	6
auto[0]	values[5]	values[5]	46	1			T6	12		T262	26		T263	8
auto[0]	values[5]	values[6]	64	1			T185	34		T264	14		T265	8
auto[0]	values[5]	values[7]	30	1			T80	8		T266	18		T267	2
auto[0]	values[6]	values[0]	4	1			T187	4		-	-		-	-
auto[0]	values[6]	values[1]	24	1			T268	12		T269	12		-	-
auto[0]	values[6]	values[2]	30	1			T29	12		T270	6		T271	4
auto[0]	values[6]	values[3]	64	1			T186	10		T7	4		T44	12
auto[0]	values[6]	values[4]	10	1			T272	10		-	-		-	-
auto[0]	values[6]	values[5]	42	1			T273	28		T274	12		T275	2
auto[0]	values[6]	values[7]	36	1			T69	24		T276	12		-	-
auto[0]	values[7]	values[0]	38	1			T183	2		T277	16		T278	20
auto[0]	values[7]	values[1]	64	1			T279	34		T23	4		T280	8
auto[0]	values[7]	values[2]	88	1			T281	2		T282	32		T283	18
auto[0]	values[7]	values[4]	36	1			T190	4		T284	6		T285	14
auto[0]	values[7]	values[5]	86	1			T286	14		T89	10		T287	22
auto[0]	values[7]	values[6]	114	1			T8	22		T27	14		T288	18
auto[0]	values[7]	values[7]	28	1			T70	20		T289	8		-	-
auto[1]	values[0]	values[6]	2	1			T72	2		-	-		-	-
auto[1]	values[0]	values[7]	4	1			T77	4		-	-		-	-
auto[1]	values[2]	values[1]	6	1			T290	6		-	-		-	-
auto[1]	values[2]	values[6]	2	1			T73	2		-	-		-	-
auto[1]	values[2]	values[7]	2	1			T78	2		-	-		-	-
auto[1]	values[3]	values[1]	2	1			T75	2		-	-		-	-
auto[1]	values[3]	values[4]	2	1			T291	2		-	-		-	-
auto[1]	values[3]	values[7]	12	1			T66	12		-	-		-	-
auto[1]	values[4]	values[0]	2	1			T292	2		-	-		-	-
auto[1]	values[4]	values[1]	2	1			T245	2		-	-		-	-
auto[1]	values[4]	values[4]	2	1			T76	2		-	-		-	-
auto[1]	values[5]	values[0]	2	1			T74	2		-	-		-	-
auto[1]	values[5]	values[2]	8	1			T67	8		-	-		-	-
auto[1]	values[5]	values[4]	8	1			T12	6		T293	2		-	-
auto[1]	values[5]	values[6]	2	1			T264	2		-	-		-	-
auto[1]	values[6]	values[2]	2	1			T271	2		-	-		-	-