Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1485

1

T2

1

T14

25

T19

4

auto[1]

1421

1

T2

1

T14

17

T19

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

771

1

T19

8

T62

16

T63

1

auto[1]

2135

1

T2

2

T14

42

T21

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2602

1

T2

2

T14

42

T19

5

auto[1]

304

1

T19

3

T62

6

T57

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	595	1			T2	2		T14	14		T19	1
valid[1]	597	1			T14	5		T19	2		T61	5
valid[2]	529	1			T14	7		T19	2		T21	2
valid[3]	600	1			T14	10		T19	1		T61	10
valid[4]	585	1			T14	6		T19	2		T61	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	57	1			T57	1		T65	2		T103	3
auto[0]	auto[0]	valid[0]	auto[1]	209	1			T2	1		T14	7		T61	3
auto[0]	auto[0]	valid[1]	auto[0]	51	1			T19	1		T62	1		T63	1
auto[0]	auto[0]	valid[1]	auto[1]	219	1			T14	2		T61	2		T106	2
auto[0]	auto[0]	valid[2]	auto[0]	40	1			T19	2		T62	1		T65	1
auto[0]	auto[0]	valid[2]	auto[1]	212	1			T14	5		T21	2		T61	2
auto[0]	auto[0]	valid[3]	auto[0]	48	1			T57	2		T65	1		T100	1
auto[0]	auto[0]	valid[3]	auto[1]	230	1			T14	6		T61	7		T105	2
auto[0]	auto[0]	valid[4]	auto[0]	46	1			T62	1		T57	2		T100	3
auto[0]	auto[0]	valid[4]	auto[1]	215	1			T14	5		T61	2		T105	2
auto[0]	auto[1]	valid[0]	auto[0]	57	1			T62	1		T57	1		T100	1
auto[0]	auto[1]	valid[0]	auto[1]	207	1			T2	1		T14	7		T61	2
auto[0]	auto[1]	valid[1]	auto[0]	37	1			T19	1		T62	2		T57	1
auto[0]	auto[1]	valid[1]	auto[1]	223	1			T14	3		T61	3		T105	3
auto[0]	auto[1]	valid[2]	auto[0]	33	1			T57	1		T100	1		T392	2
auto[0]	auto[1]	valid[2]	auto[1]	191	1			T14	2		T61	3		T105	1
auto[0]	auto[1]	valid[3]	auto[0]	50	1			T19	1		T62	3		T57	3
auto[0]	auto[1]	valid[3]	auto[1]	215	1			T14	4		T61	3		T105	1
auto[0]	auto[1]	valid[4]	auto[0]	48	1			T62	1		T57	2		T65	1
auto[0]	auto[1]	valid[4]	auto[1]	214	1			T14	1		T61	4		T105	1
auto[1]	auto[0]	valid[0]	auto[0]	32	1			T57	1		T100	2		T103	2
auto[1]	auto[0]	valid[1]	auto[0]	37	1			T57	1		T392	1		T103	2
auto[1]	auto[0]	valid[2]	auto[0]	24	1			T100	1		T392	1		T103	1
auto[1]	auto[0]	valid[3]	auto[0]	28	1			T57	3		T98	1		T393	1
auto[1]	auto[0]	valid[4]	auto[0]	37	1			T19	1		T62	1		T65	1
auto[1]	auto[1]	valid[0]	auto[0]	33	1			T19	1		T62	1		T65	2
auto[1]	auto[1]	valid[1]	auto[0]	30	1			T62	2		T57	1		T100	2
auto[1]	auto[1]	valid[2]	auto[0]	29	1			T57	1		T392	1		T103	1
auto[1]	auto[1]	valid[3]	auto[0]	29	1			T62	2		T392	1		T98	3
auto[1]	auto[1]	valid[4]	auto[0]	25	1			T19	1		T57	1		T65	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal