Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19368

1

T3

4

T15

4

T16

4

auto[1]

20894

1

T2

2

T14

575

T19

26

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33201

1

T2

2

T3

3

T14

575

auto[1]

7061

1

T3

1

T15

2

T16

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	20852	1			T2	2		T3	1		T14	300
others[1]	3391	1			T14	44		T19	23		T21	6
others[2]	3376	1			T3	1		T14	53		T15	1
others[3]	3811	1			T3	1		T14	56		T16	1
interest[1]	2204	1			T14	29		T15	1		T16	1
interest[4]	13728	1			T2	2		T14	194		T15	1
interest[64]	6628	1			T3	1		T14	93		T19	54

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	6306	1			T3	1		T15	1		T16	1
auto[0]	auto[0]	others[1]	1030	1			T19	14		T60	1		T62	30
auto[0]	auto[0]	others[2]	1018	1			T15	1		T19	16		T62	26
auto[0]	auto[0]	others[3]	1178	1			T3	1		T16	1		T19	26
auto[0]	auto[0]	interest[1]	677	1			T16	1		T19	11		T62	18
auto[0]	auto[0]	interest[4]	4105	1			T15	1		T19	59		T62	121
auto[0]	auto[0]	interest[64]	2098	1			T3	1		T19	28		T60	1
auto[0]	auto[1]	others[0]	10922	1			T2	2		T14	300		T19	18
auto[0]	auto[1]	others[1]	1755	1			T14	44		T21	6		T61	30
auto[0]	auto[1]	others[2]	1771	1			T14	53		T19	2		T21	2
auto[0]	auto[1]	others[3]	1944	1			T14	56		T19	1		T21	2
auto[0]	auto[1]	interest[1]	1131	1			T14	29		T19	3		T21	1
auto[0]	auto[1]	interest[4]	7280	1			T2	2		T14	194		T19	8
auto[0]	auto[1]	interest[64]	3371	1			T14	93		T19	2		T21	8
auto[1]	auto[0]	others[0]	3624	1			T15	1		T19	62		T62	92
auto[1]	auto[0]	others[1]	606	1			T19	9		T60	1		T62	14
auto[1]	auto[0]	others[2]	587	1			T3	1		T16	1		T19	8
auto[1]	auto[0]	others[3]	689	1			T19	9		T62	19		T57	12
auto[1]	auto[0]	interest[1]	396	1			T15	1		T19	6		T62	12
auto[1]	auto[0]	interest[4]	2343	1			T19	43		T62	59		T55	2
auto[1]	auto[0]	interest[64]	1159	1			T19	24		T62	30		T55	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal