Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	513	1			T33	17		T35	21		T42	17
all_values[1]	513	1			T33	17		T35	21		T42	17
all_values[2]	513	1			T33	17		T35	21		T42	17
all_values[3]	513	1			T33	17		T35	21		T42	17
all_values[4]	513	1			T33	17		T35	21		T42	17
all_values[5]	513	1			T33	17		T35	21		T42	17
all_values[6]	513	1			T33	17		T35	21		T42	17
all_values[7]	513	1			T33	17		T35	21		T42	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2184

1

T33

76

T35

80

T42

72

auto[1]

1920

1

T33

60

T35

88

T42

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1687

1

T33

58

T35

84

T42

52

auto[1]

2417

1

T33

78

T35

84

T42

84

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2374

1

T33

78

T35

116

T42

86

auto[1]

1730

1

T33

58

T35

52

T42

50

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	94	1			T33	2		T35	2		T42	5
all_values[0]	auto[0]	auto[0]	auto[1]	45	1			T33	4		T35	1		T360	1
all_values[0]	auto[0]	auto[1]	auto[0]	93	1			T33	2		T35	3		T42	4
all_values[0]	auto[0]	auto[1]	auto[1]	50	1			T33	1		T35	4		T42	2
all_values[0]	auto[1]	auto[0]	auto[1]	111	1			T33	3		T35	3		T42	5
all_values[0]	auto[1]	auto[1]	auto[1]	120	1			T33	5		T35	8		T42	1
all_values[1]	auto[0]	auto[0]	auto[0]	115	1			T33	4		T35	6		T360	8
all_values[1]	auto[0]	auto[0]	auto[1]	50	1			T35	3		T42	2		T166	5
all_values[1]	auto[0]	auto[1]	auto[0]	80	1			T33	3		T35	1		T42	7
all_values[1]	auto[0]	auto[1]	auto[1]	52	1			T33	1		T35	2		T42	3
all_values[1]	auto[1]	auto[0]	auto[1]	111	1			T33	6		T35	4		T42	4
all_values[1]	auto[1]	auto[1]	auto[1]	105	1			T33	3		T35	5		T42	1
all_values[2]	auto[0]	auto[0]	auto[0]	104	1			T33	8		T35	5		T42	3
all_values[2]	auto[0]	auto[0]	auto[1]	46	1			T33	1		T35	2		T42	5
all_values[2]	auto[0]	auto[1]	auto[0]	99	1			T33	1		T35	5		T360	3
all_values[2]	auto[0]	auto[1]	auto[1]	45	1			T33	2		T35	1		T42	1
all_values[2]	auto[1]	auto[0]	auto[1]	131	1			T33	3		T35	4		T42	6
all_values[2]	auto[1]	auto[1]	auto[1]	88	1			T33	2		T35	4		T42	2
all_values[3]	auto[0]	auto[0]	auto[0]	116	1			T33	5		T35	4		T42	5
all_values[3]	auto[0]	auto[0]	auto[1]	54	1			T33	4		T35	2		T42	2
all_values[3]	auto[0]	auto[1]	auto[0]	87	1			T33	3		T35	7		T42	4
all_values[3]	auto[0]	auto[1]	auto[1]	34	1			T35	3		T42	2		T360	1
all_values[3]	auto[1]	auto[0]	auto[1]	126	1			T33	4		T35	3		T42	2
all_values[3]	auto[1]	auto[1]	auto[1]	96	1			T33	1		T35	2		T42	2
all_values[4]	auto[0]	auto[0]	auto[0]	97	1			T33	2		T35	2		T42	1
all_values[4]	auto[0]	auto[0]	auto[1]	43	1			T35	3		T42	2		T360	3
all_values[4]	auto[0]	auto[1]	auto[0]	82	1			T33	5		T35	7		T42	4
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T33	2		T35	3		T42	2
all_values[4]	auto[1]	auto[0]	auto[1]	108	1			T33	3		T35	3		T42	2
all_values[4]	auto[1]	auto[1]	auto[1]	115	1			T33	5		T35	3		T42	6
all_values[5]	auto[0]	auto[0]	auto[0]	169	1			T33	4		T35	14		T42	7
all_values[5]	auto[0]	auto[1]	auto[0]	138	1			T33	4		T35	4		T42	4
all_values[5]	auto[1]	auto[0]	auto[1]	113	1			T33	8		T35	2		T42	3
all_values[5]	auto[1]	auto[1]	auto[1]	93	1			T33	1		T35	1		T42	3
all_values[6]	auto[0]	auto[0]	auto[0]	105	1			T33	2		T35	4		T42	2
all_values[6]	auto[0]	auto[0]	auto[1]	48	1			T35	2		T42	2		T360	1
all_values[6]	auto[0]	auto[1]	auto[0]	116	1			T33	5		T35	8		T42	3
all_values[6]	auto[0]	auto[1]	auto[1]	45	1			T33	2		T35	2		T42	3
all_values[6]	auto[1]	auto[0]	auto[1]	103	1			T33	3		T35	2		T42	4
all_values[6]	auto[1]	auto[1]	auto[1]	96	1			T33	5		T35	3		T42	3
all_values[7]	auto[0]	auto[0]	auto[0]	110	1			T33	5		T35	6		T42	1
all_values[7]	auto[0]	auto[0]	auto[1]	58	1			T33	1		T35	1		T42	5
all_values[7]	auto[0]	auto[1]	auto[0]	82	1			T33	3		T35	6		T42	2
all_values[7]	auto[0]	auto[1]	auto[1]	49	1			T33	2		T35	3		T42	3
all_values[7]	auto[1]	auto[0]	auto[1]	127	1			T33	4		T35	2		T42	4
all_values[7]	auto[1]	auto[1]	auto[1]	87	1			T33	2		T35	3		T42	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal