Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	265397	1			T3	1		T4	1		T12	1
all_values[1]	265397	1			T3	1		T4	1		T12	1
all_values[2]	265397	1			T3	1		T4	1		T12	1
all_values[3]	265397	1			T3	1		T4	1		T12	1
all_values[4]	265397	1			T3	1		T4	1		T12	1
all_values[5]	265397	1			T3	1		T4	1		T12	1
all_values[6]	265397	1			T3	1		T4	1		T12	1
all_values[7]	265397	1			T3	1		T4	1		T12	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2120639

1

T3

8

T4

8

T12

8

auto[1]

2537

1

T13

145

T32

116

T40

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2120751

1

T3

8

T4

8

T12

8

auto[1]

2425

1

T13

125

T15

12

T16

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	264957	1			T3	1		T4	1		T12	1
all_values[0]	auto[0]	auto[1]	158	1			T13	12		T32	9		T40	2
all_values[0]	auto[1]	auto[0]	158	1			T13	10		T32	8		T39	4
all_values[0]	auto[1]	auto[1]	124	1			T13	6		T32	3		T39	3
all_values[1]	auto[0]	auto[0]	264937	1			T3	1		T4	1		T12	1
all_values[1]	auto[0]	auto[1]	127	1			T13	4		T32	8		T40	1
all_values[1]	auto[1]	auto[0]	198	1			T13	15		T32	7		T40	2
all_values[1]	auto[1]	auto[1]	135	1			T13	6		T32	5		T40	3
all_values[2]	auto[0]	auto[0]	264913	1			T3	1		T4	1		T12	1
all_values[2]	auto[0]	auto[1]	143	1			T13	11		T32	7		T40	2
all_values[2]	auto[1]	auto[0]	200	1			T13	8		T32	5		T40	2
all_values[2]	auto[1]	auto[1]	141	1			T13	10		T32	7		T39	4
all_values[3]	auto[0]	auto[0]	264928	1			T3	1		T4	1		T12	1
all_values[3]	auto[0]	auto[1]	150	1			T13	8		T32	6		T89	1
all_values[3]	auto[1]	auto[0]	197	1			T13	13		T32	6		T40	2
all_values[3]	auto[1]	auto[1]	122	1			T13	5		T32	10		T40	4
all_values[4]	auto[0]	auto[0]	264916	1			T3	1		T4	1		T12	1
all_values[4]	auto[0]	auto[1]	165	1			T13	9		T32	1		T128	5
all_values[4]	auto[1]	auto[0]	166	1			T13	12		T32	12		T40	2
all_values[4]	auto[1]	auto[1]	150	1			T13	8		T32	6		T40	2
all_values[5]	auto[0]	auto[0]	264724	1			T3	1		T4	1		T12	1
all_values[5]	auto[0]	auto[1]	353	1			T13	9		T15	12		T16	1
all_values[5]	auto[1]	auto[0]	195	1			T13	15		T32	10		T39	4
all_values[5]	auto[1]	auto[1]	125	1			T13	7		T32	5		T39	4
all_values[6]	auto[0]	auto[0]	264945	1			T3	1		T4	1		T12	1
all_values[6]	auto[0]	auto[1]	145	1			T13	7		T32	11		T39	5
all_values[6]	auto[1]	auto[0]	179	1			T13	9		T32	8		T40	2
all_values[6]	auto[1]	auto[1]	128	1			T13	5		T32	1		T39	11
all_values[7]	auto[0]	auto[0]	264957	1			T3	1		T4	1		T12	1
all_values[7]	auto[0]	auto[1]	121	1			T13	10		T32	3		T40	1
all_values[7]	auto[1]	auto[0]	181	1			T13	8		T32	15		T40	2
all_values[7]	auto[1]	auto[1]	138	1			T13	8		T32	8		T40	3