Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	31	53	63.10

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	3	33	91.67	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	991	1			T4	8		T8	4		T9	2
auto[SpiFlashAddrCfg]	766	1			T4	4		T5	4		T8	2
auto[SpiFlashAddr3b]	1052	1			T3	2		T4	10		T5	8
auto[SpiFlashAddr4b]	851	1			T3	2		T4	6		T9	8

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2836

1

T3

4

T5

12

T9

14

auto[1]

824

1

T4

28

T8

12

T71

22

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1792

1

T3

4

T4

18

T5

10

auto[1]

1868

1

T4

10

T5

2

T8

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1446	1			T3	2		T4	8		T8	6
values[1]	94	1			T4	4		T96	2		T43	2
values[2]	159	1			T68	4		T96	2		T43	4
values[3]	121	1			T71	2		T102	2		T74	4
values[4]	170	1			T10	2		T187	2		T202	2
values[5]	179	1			T4	4		T5	2		T8	2
values[6]	166	1			T4	4		T9	4		T68	2
values[7]	180	1			T4	2		T5	3		T10	2
values[8]	1145	1			T3	2		T4	6		T5	7

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3106

1

T3

4

T4

28

T8

12

auto[1]

554

1

T5

12

T69

18

T87

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3528

1

T3

4

T4

22

T5

12

write

132

1

T4

6

T9

4

T68

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1703

1

T3

2

T4

10

T5

9

valids[0x1]

1957

1

T3

2

T4

18

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	148	1			T42	4		T44	2		T97	6
internal_process_ops[0x5a]	246	1			T8	2		T68	4		T42	2
internal_process_ops[0x05]	160	1			T43	6		T102	4		T44	6
internal_process_ops[0x35]	188	1			T11	4		T42	2		T96	2
internal_process_ops[0x15]	206	1			T4	2		T11	4		T68	2
internal_process_ops[0x03]	208	1			T4	2		T8	2		T68	2
internal_process_ops[0x0b]	257	1			T3	2		T5	3		T9	4
internal_process_ops[0x3b]	276	1			T3	2		T4	2		T5	3
internal_process_ops[0x6b]	279	1			T68	2		T69	2		T87	7
internal_process_ops[0xbb]	258	1			T5	2		T10	2		T69	6
internal_process_ops[0xeb]	222	1			T5	4		T9	2		T43	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3614

1

T3

4

T4

22

T5

12

auto[1]

46

1

T4

6

T72

4

T73

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3660

1

T3

4

T4

28

T5

12

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

772

1

T10

4

T11

6

T68

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

182

1

T4

6

T8

4

T71

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

400

1

T9

2

T10

2

T11

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

152

1

T8

2

T71

2

T173

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

558

1

T3

2

T10

4

T68

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

262

1

T4

10

T8

6

T74

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

466

1

T3

2

T9

8

T10

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

182

1

T4

6

T71

8

T173

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

16

1

T9

2

T196

2

T185

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

14

1

T4

2

T72

4

T80

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

26

1

T9

2

T28

4

T284

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

6

1

T4

4

T82

2

-

-

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

36

1

T68

2

T97

12

T285

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

20

1

T78

10

T79

2

T83

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

8

1

T90

2

T286

2

T277

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

6

1

T73

2

T282

4

-

-

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7

1

T69

7

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

182

1

T5

4

T69

2

T87

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

176

1

T5

8

T69

9

T88

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

189

1

T87

7

T287

4

T89

5

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	3	33	91.67	3

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	250	1			T8	4		T10	4		T11	4
auto[0]	values[0]	valids[0x1]	1140	1			T3	2		T4	8		T8	2
auto[0]	values[1]	valids[0x1]	86	1			T4	4		T96	2		T43	2
auto[0]	values[2]	valids[0x0]	86	1			T96	2		T173	2		T103	2
auto[0]	values[2]	valids[0x1]	48	1			T68	4		T43	4		T72	8
auto[0]	values[3]	valids[0x0]	60	1			T71	2		T102	2		T74	4
auto[0]	values[3]	valids[0x1]	28	1			T197	2		T237	2		T75	2
auto[0]	values[4]	valids[0x0]	98	1			T10	2		T29	4		T28	2
auto[0]	values[4]	valids[0x1]	44	1			T187	2		T202	2		T288	2
auto[0]	values[5]	valids[0x0]	92	1			T4	4		T10	2		T68	2
auto[0]	values[5]	valids[0x1]	52	1			T8	2		T71	4		T202	4
auto[0]	values[6]	valids[0x0]	62	1			T196	2		T215	2		T53	10
auto[0]	values[6]	valids[0x1]	48	1			T4	4		T9	4		T68	2
auto[0]	values[7]	valids[0x0]	114	1			T10	2		T74	4		T97	12
auto[0]	values[7]	valids[0x1]	36	1			T4	2		T73	2		T231	6
auto[0]	values[8]	valids[0x0]	550	1			T3	2		T4	6		T9	6
auto[0]	values[8]	valids[0x1]	312	1			T8	4		T68	2		T42	2
auto[1]	values[0]	valids[0x1]	56	1			T88	7		T289	7		T290	4
auto[1]	values[1]	valids[0x1]	8	1			T128	4		T291	4		-	-
auto[1]	values[2]	valids[0x0]	16	1			T292	3		T293	3		T294	4
auto[1]	values[2]	valids[0x1]	9	1			T295	7		T296	2		-	-
auto[1]	values[3]	valids[0x0]	27	1			T287	4		T128	4		T297	5
auto[1]	values[3]	valids[0x1]	6	1			T298	6		-	-		-	-
auto[1]	values[4]	valids[0x0]	21	1			T299	4		T298	3		T300	5
auto[1]	values[4]	valids[0x1]	7	1			T89	5		T295	2		-	-
auto[1]	values[5]	valids[0x0]	27	1			T5	2		T89	8		T128	3
auto[1]	values[5]	valids[0x1]	8	1			T297	3		T301	5		-	-
auto[1]	values[6]	valids[0x0]	47	1			T69	3		T88	3		T302	3
auto[1]	values[6]	valids[0x1]	9	1			T303	6		T304	3		-	-
auto[1]	values[7]	valids[0x0]	23	1			T5	3		T69	2		T289	4
auto[1]	values[7]	valids[0x1]	7	1			T293	3		T294	4		-	-
auto[1]	values[8]	valids[0x0]	230	1			T5	4		T69	6		T87	18
auto[1]	values[8]	valids[0x1]	53	1			T5	3		T69	7		T287	2