Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1861254 1 T3 3708 T4 1 T5 5245


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1735816 1 T3 3708 T4 1 T5 5245
auto[1] 125438 1 T11 4914 T42 6 T43 8676


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 397106 1 T3 1 T4 1 T5 422
auto[524288:1048575] 190198 1 T3 37 T5 721 T69 341
auto[1048576:1572863] 178915 1 T3 1207 T5 75 T69 5
auto[1572864:2097151] 216226 1 T5 167 T69 4335 T27 1922
auto[2097152:2621439] 222550 1 T3 22 T5 822 T69 16
auto[2621440:3145727] 218795 1 T5 1087 T69 14580 T27 3036
auto[3145728:3670015] 215487 1 T3 16 T5 1147 T69 6439
auto[3670016:4194303] 221977 1 T3 2425 T5 804 T69 12


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 138253 1 T3 19 T4 1 T5 382
auto[1] 1723001 1 T3 3689 T5 4863 T69 25429


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1861254 1 T3 3708 T4 1 T5 5245


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 304492 1 T3 1 T4 1 T5 422
auto[0] auto[0] auto[0:524287] auto[1] 92614 1 T11 4914 T43 8676 T102 119
auto[0] auto[0] auto[524288:1048575] auto[0] 184110 1 T3 37 T5 721 T69 341
auto[0] auto[0] auto[524288:1048575] auto[1] 6088 1 T102 1 T44 524 T103 256
auto[0] auto[0] auto[1048576:1572863] auto[0] 175599 1 T3 1207 T5 75 T69 5
auto[0] auto[0] auto[1048576:1572863] auto[1] 3316 1 T102 12 T44 8 T172 2
auto[0] auto[0] auto[1572864:2097151] auto[0] 212732 1 T5 167 T69 4335 T27 1922
auto[0] auto[0] auto[1572864:2097151] auto[1] 3494 1 T102 1612 T103 128 T172 1
auto[0] auto[0] auto[2097152:2621439] auto[0] 220353 1 T3 22 T5 822 T69 16
auto[0] auto[0] auto[2097152:2621439] auto[1] 2197 1 T44 767 T103 127 T172 5
auto[0] auto[0] auto[2621440:3145727] auto[0] 217836 1 T5 1087 T69 14580 T27 3036
auto[0] auto[0] auto[2621440:3145727] auto[1] 959 1 T42 6 T102 108 T103 257
auto[0] auto[0] auto[3145728:3670015] auto[0] 207544 1 T3 16 T5 1147 T69 6439
auto[0] auto[0] auto[3145728:3670015] auto[1] 7943 1 T44 175 T172 685 T95 1
auto[0] auto[0] auto[3670016:4194303] auto[0] 213150 1 T3 2425 T5 804 T69 12
auto[0] auto[0] auto[3670016:4194303] auto[1] 8827 1 T102 2 T44 4 T172 3134


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 138253 1 T3 19 T4 1 T5 382
auto[0] auto[0] auto[1] 1723001 1 T3 3689 T5 4863 T69 25429

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