Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	31	97	75.78

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	31	97	75.78	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2282

1

T3

4

T9

14

T10

14

auto[1]

824

1

T4

28

T8

12

T71

22

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	354	1			T68	30		T96	26		T44	10
values[1]	382	1			T10	14		T43	28		T97	36
values[2]	414	1			T11	12		T74	20		T90	2
values[3]	466	1			T4	28		T187	28		T175	18
values[4]	290	1			T8	12		T174	26		T91	2
values[5]	390	1			T3	4		T9	14		T42	8
values[6]	448	1			T27	6		T71	22		T102	10
values[7]	362	1			T76	2		T196	18		T172	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	342	1			T8	12		T96	26		T174	26
values[1]	492	1			T42	8		T43	28		T102	10
values[2]	408	1			T10	14		T71	22		T77	4
values[3]	324	1			T28	38		T197	2		T263	10
values[4]	284	1			T27	6		T76	2		T172	8
values[5]	446	1			T4	28		T9	14		T68	30
values[6]	434	1			T3	4		T11	12		T173	18
values[7]	376	1			T187	28		T180	8		T204	12

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	31	97	75.78	31

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[6]]	0	1	1
[auto[0]]	[values[4]]	[values[3]]	0	1	1
[auto[0]]	[values[7]]	[values[2]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[1]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[2]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[3]]	[values[4]]	0	1	1
[auto[1]]	[values[4]]	[values[1] , values[2] , values[3] , values[4]]	--	--	4
[auto[1]]	[values[4]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[5]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[5]]	[values[5]]	0	1	1
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[6]]	0	1	1
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	70	1			T96	26		T203	30		T273	14
auto[0]	values[0]	values[1]	32	1			T272	22		T305	8		T243	2
auto[0]	values[0]	values[2]	14	1			T44	10		T306	4		-	-
auto[0]	values[0]	values[3]	16	1			T242	4		T101	12		-	-
auto[0]	values[0]	values[4]	12	1			T239	4		T191	8		-	-
auto[0]	values[0]	values[5]	56	1			T68	30		T209	16		T235	10
auto[0]	values[0]	values[7]	58	1			T204	12		T238	24		T190	20
auto[0]	values[1]	values[0]	86	1			T100	8		T75	34		T307	16
auto[0]	values[1]	values[1]	28	1			T43	28		-	-		-	-
auto[0]	values[1]	values[2]	74	1			T10	14		T97	36		T229	6
auto[0]	values[1]	values[3]	10	1			T276	10		-	-		-	-
auto[0]	values[1]	values[4]	16	1			T99	10		T208	6		-	-
auto[0]	values[1]	values[5]	26	1			T288	24		T281	2		-	-
auto[0]	values[1]	values[6]	12	1			T271	8		T275	2		T308	2
auto[0]	values[1]	values[7]	30	1			T117	8		T309	10		T310	4
auto[0]	values[2]	values[0]	16	1			T45	16		-	-		-	-
auto[0]	values[2]	values[1]	14	1			T90	2		T284	12		-	-
auto[0]	values[2]	values[2]	18	1			T311	14		T312	4		-	-
auto[0]	values[2]	values[3]	114	1			T28	38		T197	2		T263	10
auto[0]	values[2]	values[4]	4	1			T192	4		-	-		-	-
auto[0]	values[2]	values[5]	20	1			T285	20		-	-		-	-
auto[0]	values[2]	values[6]	72	1			T11	12		T198	14		T251	4
auto[0]	values[2]	values[7]	4	1			T246	2		T313	2		-	-
auto[0]	values[3]	values[0]	2	1			T224	2		-	-		-	-
auto[0]	values[3]	values[1]	40	1			T175	18		T94	18		T314	4
auto[0]	values[3]	values[2]	58	1			T194	34		T315	24		-	-
auto[0]	values[3]	values[3]	6	1			T233	6		-	-		-	-
auto[0]	values[3]	values[4]	30	1			T215	24		T316	6		-	-
auto[0]	values[3]	values[5]	36	1			T220	36		-	-		-	-
auto[0]	values[3]	values[6]	138	1			T29	32		T237	10		T317	22
auto[0]	values[3]	values[7]	62	1			T187	28		T180	8		T85	12
auto[0]	values[4]	values[0]	42	1			T174	26		T188	6		T225	4
auto[0]	values[4]	values[1]	80	1			T264	18		T266	2		T249	16
auto[0]	values[4]	values[2]	26	1			T199	26		-	-		-	-
auto[0]	values[4]	values[4]	22	1			T95	16		T214	6		-	-
auto[0]	values[4]	values[5]	40	1			T91	2		T219	2		T222	16
auto[0]	values[4]	values[6]	2	1			T207	2		-	-		-	-
auto[0]	values[4]	values[7]	42	1			T269	4		T241	16		T123	22
auto[0]	values[5]	values[0]	12	1			T318	12		-	-		-	-
auto[0]	values[5]	values[1]	98	1			T42	8		T195	10		T56	12
auto[0]	values[5]	values[2]	32	1			T319	32		-	-		-	-
auto[0]	values[5]	values[3]	30	1			T253	24		T320	2		T257	4
auto[0]	values[5]	values[4]	4	1			T245	4		-	-		-	-
auto[0]	values[5]	values[5]	80	1			T9	14		T256	12		T261	32
auto[0]	values[5]	values[6]	16	1			T3	4		T176	2		T181	10
auto[0]	values[5]	values[7]	16	1			T255	6		T248	10		-	-
auto[0]	values[6]	values[0]	22	1			T103	22		-	-		-	-
auto[0]	values[6]	values[1]	10	1			T102	10		-	-		-	-
auto[0]	values[6]	values[2]	92	1			T77	4		T177	2		T321	4
auto[0]	values[6]	values[3]	24	1			T286	6		T322	18		-	-
auto[0]	values[6]	values[4]	14	1			T27	6		T109	4		T185	4
auto[0]	values[6]	values[5]	54	1			T323	8		T122	30		T324	2
auto[0]	values[6]	values[6]	46	1			T262	20		T250	22		T267	4
auto[0]	values[6]	values[7]	32	1			T325	32		-	-		-	-
auto[0]	values[7]	values[0]	44	1			T196	18		T86	26		-	-
auto[0]	values[7]	values[1]	2	1			T240	2		-	-		-	-
auto[0]	values[7]	values[3]	54	1			T55	18		T121	16		T326	8
auto[0]	values[7]	values[4]	96	1			T76	2		T172	8		T129	4
auto[0]	values[7]	values[5]	12	1			T327	6		T178	6		-	-
auto[0]	values[7]	values[6]	46	1			T24	12		T179	34		-	-
auto[0]	values[7]	values[7]	18	1			T206	18		-	-		-	-
auto[1]	values[0]	values[1]	36	1			T72	36		-	-		-	-
auto[1]	values[0]	values[2]	28	1			T328	8		T265	20		-	-
auto[1]	values[0]	values[5]	14	1			T81	14		-	-		-	-
auto[1]	values[0]	values[6]	18	1			T234	18		-	-		-	-
auto[1]	values[1]	values[0]	32	1			T259	12		T200	20		-	-
auto[1]	values[1]	values[1]	14	1			T211	2		T212	12		-	-
auto[1]	values[1]	values[4]	22	1			T98	6		T201	16		-	-
auto[1]	values[1]	values[7]	32	1			T252	32		-	-		-	-
auto[1]	values[2]	values[1]	50	1			T74	20		T278	30		-	-
auto[1]	values[2]	values[2]	16	1			T329	16		-	-		-	-
auto[1]	values[2]	values[3]	20	1			T268	4		T84	16		-	-
auto[1]	values[2]	values[4]	4	1			T73	4		-	-		-	-
auto[1]	values[2]	values[5]	6	1			T254	6		-	-		-	-
auto[1]	values[2]	values[6]	28	1			T283	28		-	-		-	-
auto[1]	values[2]	values[7]	28	1			T83	28		-	-		-	-
auto[1]	values[3]	values[3]	24	1			T330	24		-	-		-	-
auto[1]	values[3]	values[5]	38	1			T4	28		T331	10		-	-
auto[1]	values[3]	values[6]	2	1			T182	2		-	-		-	-
auto[1]	values[3]	values[7]	30	1			T78	30		-	-		-	-
auto[1]	values[4]	values[0]	12	1			T8	12		-	-		-	-
auto[1]	values[4]	values[5]	24	1			T244	24		-	-		-	-
auto[1]	values[5]	values[0]	4	1			T332	4		-	-		-	-
auto[1]	values[5]	values[1]	40	1			T333	8		T280	6		T282	26
auto[1]	values[5]	values[4]	4	1			T236	4		-	-		-	-
auto[1]	values[5]	values[6]	54	1			T173	18		T334	20		T186	16
auto[1]	values[6]	values[1]	22	1			T231	22		-	-		-	-
auto[1]	values[6]	values[2]	40	1			T71	22		T230	18		-	-
auto[1]	values[6]	values[3]	8	1			T335	8		-	-		-	-
auto[1]	values[6]	values[4]	30	1			T216	2		T82	18		T205	10
auto[1]	values[6]	values[5]	30	1			T260	30		-	-		-	-
auto[1]	values[6]	values[7]	24	1			T79	24		-	-		-	-
auto[1]	values[7]	values[1]	26	1			T202	26		-	-		-	-
auto[1]	values[7]	values[2]	10	1			T336	10		-	-		-	-
auto[1]	values[7]	values[3]	18	1			T80	18		-	-		-	-
auto[1]	values[7]	values[4]	26	1			T53	26		-	-		-	-
auto[1]	values[7]	values[5]	10	1			T221	10		-	-		-	-