Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1553

1

T3

2

T4

14

T8

6

auto[1]

2107

1

T3

2

T4

14

T5

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	214	1			T4	2		T8	2		T68	2
auto[4:7]	234	1			T4	4		T43	6		T102	4
auto[8:11]	265	1			T3	2		T5	3		T9	4
auto[12:15]	24	1			T29	6		T28	2		T254	2
auto[16:19]	14	1			T9	4		T234	4		T220	4
auto[20:23]	220	1			T4	2		T11	4		T68	2
auto[24:27]	12	1			T247	4		T181	2		T330	2
auto[28:31]	2	1			T317	2		-	-		-	-
auto[32:35]	36	1			T71	6		T72	8		T260	2
auto[36:39]	18	1			T250	4		T183	6		T307	4
auto[40:43]	16	1			T334	2		T82	2		T210	2
auto[44:47]	8	1			T202	4		T78	2		T318	2
auto[48:51]	20	1			T215	4		T200	2		T182	2
auto[52:55]	204	1			T11	4		T42	2		T96	2
auto[56:59]	286	1			T3	2		T4	2		T5	3
auto[60:63]	16	1			T96	2		T317	6		T286	2
auto[64:67]	14	1			T8	2		T29	4		T247	2
auto[68:71]	32	1			T173	2		T202	4		T284	2
auto[72:75]	24	1			T4	4		T263	2		T79	2
auto[76:79]	18	1			T68	2		T215	2		T186	4
auto[80:83]	10	1			T9	2		T68	2		T231	4
auto[84:87]	14	1			T29	2		T80	2		T75	2
auto[88:91]	262	1			T8	2		T68	4		T42	2
auto[92:95]	8	1			T8	4		T238	2		T75	2
auto[96:99]	16	1			T43	2		T241	2		T201	4
auto[100:103]	26	1			T96	2		T28	4		T185	2
auto[104:107]	285	1			T68	2		T69	2		T87	7
auto[108:111]	22	1			T78	10		T221	2		T244	6
auto[112:115]	18	1			T10	2		T53	8		T244	8
auto[116:119]	14	1			T10	2		T68	4		T284	4
auto[120:123]	22	1			T29	2		T53	6		T329	6
auto[124:127]	20	1			T9	2		T247	2		T231	2
auto[128:131]	22	1			T11	2		T71	4		T219	2
auto[132:135]	28	1			T4	4		T72	2		T319	8
auto[136:139]	18	1			T259	2		T200	4		T278	2
auto[140:143]	20	1			T238	2		T319	4		T231	4
auto[144:147]	12	1			T10	2		T79	2		T255	2
auto[148:151]	20	1			T96	2		T247	4		T260	10
auto[152:155]	8	1			T53	2		T260	2		T82	2
auto[156:159]	164	1			T42	4		T44	2		T97	6
auto[160:163]	8	1			T84	6		T282	2		-	-
auto[164:167]	4	1			T364	2		T84	2		-	-
auto[168:171]	22	1			T173	2		T90	2		T202	2
auto[172:175]	12	1			T193	4		T80	2		T234	4
auto[176:179]	34	1			T332	2		T310	2		T234	4
auto[180:183]	62	1			T27	4		T109	4		T29	4
auto[184:187]	276	1			T5	2		T10	2		T69	6
auto[188:191]	6	1			T193	2		T325	4		-	-
auto[192:195]	20	1			T91	2		T175	2		T260	4
auto[196:199]	8	1			T248	4		T365	4		-	-
auto[200:203]	12	1			T4	2		T43	4		T249	2
auto[204:207]	28	1			T68	2		T185	2		T80	4
auto[208:211]	12	1			T73	2		T189	2		T82	2
auto[212:215]	18	1			T284	2		T334	2		T365	2
auto[216:219]	14	1			T68	2		T81	2		T260	4
auto[220:223]	22	1			T8	2		T11	2		T53	2
auto[224:227]	14	1			T4	4		T96	2		T259	2
auto[228:231]	16	1			T189	2		T309	2		T336	2
auto[232:235]	300	1			T5	4		T9	2		T10	4
auto[236:239]	12	1			T196	2		T72	4		T310	2
auto[240:243]	16	1			T4	4		T238	4		T241	2
auto[244:247]	48	1			T74	4		T72	8		T252	8
auto[248:251]	6	1			T263	2		T205	2		T194	2
auto[252:255]	4	1			T43	4		-	-		-	-

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	71	1			T4	1		T8	1		T68	1
auto[0:3]	auto[1]	143	1			T4	1		T8	1		T68	1
auto[4:7]	auto[0]	117	1			T4	2		T43	3		T102	2
auto[4:7]	auto[1]	117	1			T4	2		T43	3		T102	2
auto[8:11]	auto[0]	87	1			T3	1		T9	2		T96	4
auto[8:11]	auto[1]	178	1			T3	1		T5	3		T9	2
auto[12:15]	auto[0]	12	1			T29	3		T28	1		T254	1
auto[12:15]	auto[1]	12	1			T29	3		T28	1		T254	1
auto[16:19]	auto[0]	7	1			T9	2		T234	2		T220	2
auto[16:19]	auto[1]	7	1			T9	2		T234	2		T220	2
auto[20:23]	auto[0]	110	1			T4	1		T11	2		T68	1
auto[20:23]	auto[1]	110	1			T4	1		T11	2		T68	1
auto[24:27]	auto[0]	6	1			T247	2		T181	1		T330	1
auto[24:27]	auto[1]	6	1			T247	2		T181	1		T330	1
auto[28:31]	auto[0]	1	1			T317	1		-	-		-	-
auto[28:31]	auto[1]	1	1			T317	1		-	-		-	-
auto[32:35]	auto[0]	18	1			T71	3		T72	4		T260	1
auto[32:35]	auto[1]	18	1			T71	3		T72	4		T260	1
auto[36:39]	auto[0]	9	1			T250	2		T183	3		T307	2
auto[36:39]	auto[1]	9	1			T250	2		T183	3		T307	2
auto[40:43]	auto[0]	8	1			T334	1		T82	1		T210	1
auto[40:43]	auto[1]	8	1			T334	1		T82	1		T210	1
auto[44:47]	auto[0]	4	1			T202	2		T78	1		T318	1
auto[44:47]	auto[1]	4	1			T202	2		T78	1		T318	1
auto[48:51]	auto[0]	10	1			T215	2		T200	1		T182	1
auto[48:51]	auto[1]	10	1			T215	2		T200	1		T182	1
auto[52:55]	auto[0]	102	1			T11	2		T42	1		T96	1
auto[52:55]	auto[1]	102	1			T11	2		T42	1		T96	1
auto[56:59]	auto[0]	100	1			T3	1		T4	1		T10	1
auto[56:59]	auto[1]	186	1			T3	1		T4	1		T5	3
auto[60:63]	auto[0]	8	1			T96	1		T317	3		T286	1
auto[60:63]	auto[1]	8	1			T96	1		T317	3		T286	1
auto[64:67]	auto[0]	7	1			T8	1		T29	2		T247	1
auto[64:67]	auto[1]	7	1			T8	1		T29	2		T247	1
auto[68:71]	auto[0]	16	1			T173	1		T202	2		T284	1
auto[68:71]	auto[1]	16	1			T173	1		T202	2		T284	1
auto[72:75]	auto[0]	12	1			T4	2		T263	1		T79	1
auto[72:75]	auto[1]	12	1			T4	2		T263	1		T79	1
auto[76:79]	auto[0]	9	1			T68	1		T215	1		T186	2
auto[76:79]	auto[1]	9	1			T68	1		T215	1		T186	2
auto[80:83]	auto[0]	5	1			T9	1		T68	1		T231	2
auto[80:83]	auto[1]	5	1			T9	1		T68	1		T231	2
auto[84:87]	auto[0]	7	1			T29	1		T80	1		T75	1
auto[84:87]	auto[1]	7	1			T29	1		T80	1		T75	1
auto[88:91]	auto[0]	131	1			T8	1		T68	2		T42	1
auto[88:91]	auto[1]	131	1			T8	1		T68	2		T42	1
auto[92:95]	auto[0]	4	1			T8	2		T238	1		T75	1
auto[92:95]	auto[1]	4	1			T8	2		T238	1		T75	1
auto[96:99]	auto[0]	8	1			T43	1		T241	1		T201	2
auto[96:99]	auto[1]	8	1			T43	1		T241	1		T201	2
auto[100:103]	auto[0]	13	1			T96	1		T28	2		T185	1
auto[100:103]	auto[1]	13	1			T96	1		T28	2		T185	1
auto[104:107]	auto[0]	77	1			T68	1		T96	1		T43	1
auto[104:107]	auto[1]	208	1			T68	1		T69	2		T87	7
auto[108:111]	auto[0]	11	1			T78	5		T221	1		T244	3
auto[108:111]	auto[1]	11	1			T78	5		T221	1		T244	3
auto[112:115]	auto[0]	9	1			T10	1		T53	4		T244	4
auto[112:115]	auto[1]	9	1			T10	1		T53	4		T244	4
auto[116:119]	auto[0]	7	1			T10	1		T68	2		T284	2
auto[116:119]	auto[1]	7	1			T10	1		T68	2		T284	2
auto[120:123]	auto[0]	11	1			T29	1		T53	3		T329	3
auto[120:123]	auto[1]	11	1			T29	1		T53	3		T329	3
auto[124:127]	auto[0]	10	1			T9	1		T247	1		T231	1
auto[124:127]	auto[1]	10	1			T9	1		T247	1		T231	1
auto[128:131]	auto[0]	11	1			T11	1		T71	2		T219	1
auto[128:131]	auto[1]	11	1			T11	1		T71	2		T219	1
auto[132:135]	auto[0]	14	1			T4	2		T72	1		T319	4
auto[132:135]	auto[1]	14	1			T4	2		T72	1		T319	4
auto[136:139]	auto[0]	9	1			T259	1		T200	2		T278	1
auto[136:139]	auto[1]	9	1			T259	1		T200	2		T278	1
auto[140:143]	auto[0]	10	1			T238	1		T319	2		T231	2
auto[140:143]	auto[1]	10	1			T238	1		T319	2		T231	2
auto[144:147]	auto[0]	6	1			T10	1		T79	1		T255	1
auto[144:147]	auto[1]	6	1			T10	1		T79	1		T255	1
auto[148:151]	auto[0]	10	1			T96	1		T247	2		T260	5
auto[148:151]	auto[1]	10	1			T96	1		T247	2		T260	5
auto[152:155]	auto[0]	4	1			T53	1		T260	1		T82	1
auto[152:155]	auto[1]	4	1			T53	1		T260	1		T82	1
auto[156:159]	auto[0]	82	1			T42	2		T44	1		T97	3
auto[156:159]	auto[1]	82	1			T42	2		T44	1		T97	3
auto[160:163]	auto[0]	4	1			T84	3		T282	1		-	-
auto[160:163]	auto[1]	4	1			T84	3		T282	1		-	-
auto[164:167]	auto[0]	2	1			T364	1		T84	1		-	-
auto[164:167]	auto[1]	2	1			T364	1		T84	1		-	-
auto[168:171]	auto[0]	11	1			T173	1		T90	1		T202	1
auto[168:171]	auto[1]	11	1			T173	1		T90	1		T202	1
auto[172:175]	auto[0]	6	1			T193	2		T80	1		T234	2
auto[172:175]	auto[1]	6	1			T193	2		T80	1		T234	2
auto[176:179]	auto[0]	17	1			T332	1		T310	1		T234	2
auto[176:179]	auto[1]	17	1			T332	1		T310	1		T234	2
auto[180:183]	auto[0]	31	1			T27	2		T109	2		T29	2
auto[180:183]	auto[1]	31	1			T27	2		T109	2		T29	2
auto[184:187]	auto[0]	89	1			T10	1		T173	1		T103	1
auto[184:187]	auto[1]	187	1			T5	2		T10	1		T69	6
auto[188:191]	auto[0]	3	1			T193	1		T325	2		-	-
auto[188:191]	auto[1]	3	1			T193	1		T325	2		-	-
auto[192:195]	auto[0]	10	1			T91	1		T175	1		T260	2
auto[192:195]	auto[1]	10	1			T91	1		T175	1		T260	2
auto[196:199]	auto[0]	4	1			T248	2		T365	2		-	-
auto[196:199]	auto[1]	4	1			T248	2		T365	2		-	-
auto[200:203]	auto[0]	6	1			T4	1		T43	2		T249	1
auto[200:203]	auto[1]	6	1			T4	1		T43	2		T249	1
auto[204:207]	auto[0]	14	1			T68	1		T185	1		T80	2
auto[204:207]	auto[1]	14	1			T68	1		T185	1		T80	2
auto[208:211]	auto[0]	6	1			T73	1		T189	1		T82	1
auto[208:211]	auto[1]	6	1			T73	1		T189	1		T82	1
auto[212:215]	auto[0]	9	1			T284	1		T334	1		T365	1
auto[212:215]	auto[1]	9	1			T284	1		T334	1		T365	1
auto[216:219]	auto[0]	7	1			T68	1		T81	1		T260	2
auto[216:219]	auto[1]	7	1			T68	1		T81	1		T260	2
auto[220:223]	auto[0]	11	1			T8	1		T11	1		T53	1
auto[220:223]	auto[1]	11	1			T8	1		T11	1		T53	1
auto[224:227]	auto[0]	7	1			T4	2		T96	1		T259	1
auto[224:227]	auto[1]	7	1			T4	2		T96	1		T259	1
auto[228:231]	auto[0]	8	1			T189	1		T309	1		T336	1
auto[228:231]	auto[1]	8	1			T189	1		T309	1		T336	1
auto[232:235]	auto[0]	112	1			T9	1		T10	2		T27	1
auto[232:235]	auto[1]	188	1			T5	4		T9	1		T10	2
auto[236:239]	auto[0]	6	1			T196	1		T72	2		T310	1
auto[236:239]	auto[1]	6	1			T196	1		T72	2		T310	1
auto[240:243]	auto[0]	8	1			T4	2		T238	2		T241	1
auto[240:243]	auto[1]	8	1			T4	2		T238	2		T241	1
auto[244:247]	auto[0]	24	1			T74	2		T72	4		T252	4
auto[244:247]	auto[1]	24	1			T74	2		T72	4		T252	4
auto[248:251]	auto[0]	3	1			T263	1		T205	1		T194	1
auto[248:251]	auto[1]	3	1			T263	1		T205	1		T194	1
auto[252:255]	auto[0]	2	1			T43	2		-	-		-	-
auto[252:255]	auto[1]	2	1			T43	2		-	-		-	-