Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	106	1			T102	4		T103	10		T187	2
auto[ReadAddrCrossIntoMailbox]	44	1			T3	2		T76	2		T187	12
auto[ReadAddrCrossOutOfMailbox]	40	1			T187	4		T180	4		T323	2
auto[ReadAddrCrossAllMailbox]	48	1			T187	6		T129	2		T176	2
auto[ReadAddrOutsideMailbox]	686	1			T4	4		T8	2		T9	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

462

1

T3

1

T4

2

T8

1

auto[1]

462

1

T3

1

T4

2

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	126	1			T4	2		T8	2		T68	2
read_ops[0x0b]	162	1			T3	2		T9	4		T96	4
read_ops[0x3b]	184	1			T4	2		T10	2		T68	8
read_ops[0x6b]	148	1			T68	2		T96	2		T43	2
read_ops[0xbb]	160	1			T10	2		T103	2		T74	4
read_ops[0xeb]	144	1			T9	2		T43	4		T102	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T197	1		T56	1		T232	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T197	1		T56	1		T232	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T76	1		T187	1		T85	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T76	1		T187	1		T85	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T239	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T239	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T272	3		T178	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T272	3		T178	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	48	1			T4	1		T8	1		T68	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	48	1			T4	1		T8	1		T68	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T103	1		T322	4		T217	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T103	1		T322	4		T217	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T3	1		T323	1		T199	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T3	1		T323	1		T199	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T323	1		T217	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T323	1		T217	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T279	1		T311	1		T217	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T279	1		T311	1		T217	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	64	1			T9	2		T96	2		T71	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	64	1			T9	2		T96	2		T71	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T102	1		T103	2		T180	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T102	1		T103	2		T180	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T187	1		T199	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T187	1		T199	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T180	1		T272	3		T217	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T180	1		T272	3		T217	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T176	1		T199	1		T272	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T176	1		T199	1		T272	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	64	1			T4	1		T10	1		T68	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	64	1			T4	1		T10	1		T68	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T199	1		T253	1		T86	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T199	1		T253	1		T86	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T187	2		T323	1		T279	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T187	2		T323	1		T279	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	6	1			T187	2		T180	1		T279	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	6	1			T187	2		T180	1		T279	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T187	1		T199	1		T217	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T187	1		T199	1		T217	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	52	1			T68	1		T96	1		T43	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	52	1			T68	1		T96	1		T43	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T103	1		T199	2		T214	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T103	1		T199	2		T214	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T187	1		T279	2		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T187	1		T279	2		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T204	2		T199	1		T239	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T204	2		T199	1		T239	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T187	1		T204	1		T56	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T187	1		T204	1		T56	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	61	1			T10	1		T74	2		T97	6
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	61	1			T10	1		T74	2		T97	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T102	1		T103	1		T187	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T102	1		T103	1		T187	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T187	1		T323	1		T204	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T187	1		T323	1		T204	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T272	1		T56	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T272	1		T56	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T187	1		T129	1		T56	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T187	1		T129	1		T56	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	54	1			T9	1		T43	2		T196	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	54	1			T9	1		T43	2		T196	1