Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	265397	1			T3	1		T4	1		T12	1
all_pins[1]	265397	1			T3	1		T4	1		T12	1
all_pins[2]	265397	1			T3	1		T4	1		T12	1
all_pins[3]	265397	1			T3	1		T4	1		T12	1
all_pins[4]	265397	1			T3	1		T4	1		T12	1
all_pins[5]	265397	1			T3	1		T4	1		T12	1
all_pins[6]	265397	1			T3	1		T4	1		T12	1
all_pins[7]	265397	1			T3	1		T4	1		T12	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2122113	1			T3	8		T4	8		T12	8
values[0x1]	1063	1			T13	55		T32	45		T40	12
transitions[0x0=>0x1]	787	1			T13	47		T32	34		T40	10
transitions[0x1=>0x0]	798	1			T13	48		T32	34		T40	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	265273	1			T3	1		T4	1		T12	1
all_pins[0]	values[0x1]	124	1			T13	6		T32	3		T39	3
all_pins[0]	transitions[0x0=>0x1]	85	1			T13	3		T32	3		T39	2
all_pins[0]	transitions[0x1=>0x0]	96	1			T13	3		T32	5		T40	3
all_pins[1]	values[0x0]	265262	1			T3	1		T4	1		T12	1
all_pins[1]	values[0x1]	135	1			T13	6		T32	5		T40	3
all_pins[1]	transitions[0x0=>0x1]	97	1			T13	4		T32	3		T40	3
all_pins[1]	transitions[0x1=>0x0]	103	1			T13	8		T32	5		T39	4
all_pins[2]	values[0x0]	265256	1			T3	1		T4	1		T12	1
all_pins[2]	values[0x1]	141	1			T13	10		T32	7		T39	4
all_pins[2]	transitions[0x0=>0x1]	107	1			T13	10		T32	5		T39	4
all_pins[2]	transitions[0x1=>0x0]	88	1			T13	5		T32	8		T40	4
all_pins[3]	values[0x0]	265275	1			T3	1		T4	1		T12	1
all_pins[3]	values[0x1]	122	1			T13	5		T32	10		T40	4
all_pins[3]	transitions[0x0=>0x1]	89	1			T13	5		T32	8		T40	2
all_pins[3]	transitions[0x1=>0x0]	117	1			T13	8		T32	4		T39	5
all_pins[4]	values[0x0]	265247	1			T3	1		T4	1		T12	1
all_pins[4]	values[0x1]	150	1			T13	8		T32	6		T40	2
all_pins[4]	transitions[0x0=>0x1]	113	1			T13	7		T32	3		T40	2
all_pins[4]	transitions[0x1=>0x0]	88	1			T13	6		T32	2		T39	3
all_pins[5]	values[0x0]	265272	1			T3	1		T4	1		T12	1
all_pins[5]	values[0x1]	125	1			T13	7		T32	5		T39	4
all_pins[5]	transitions[0x0=>0x1]	100	1			T13	7		T32	4		T39	3
all_pins[5]	transitions[0x1=>0x0]	103	1			T13	5		T39	10		T360	3
all_pins[6]	values[0x0]	265269	1			T3	1		T4	1		T12	1
all_pins[6]	values[0x1]	128	1			T13	5		T32	1		T39	11
all_pins[6]	transitions[0x0=>0x1]	99	1			T13	5		T32	1		T39	8
all_pins[6]	transitions[0x1=>0x0]	109	1			T13	8		T32	8		T40	3
all_pins[7]	values[0x0]	265259	1			T3	1		T4	1		T12	1
all_pins[7]	values[0x1]	138	1			T13	8		T32	8		T40	3
all_pins[7]	transitions[0x0=>0x1]	97	1			T13	6		T32	7		T40	3
all_pins[7]	transitions[0x1=>0x0]	94	1			T13	5		T32	2		T39	2