Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
63.70	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	53	75	58.59

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	53	75	58.59	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	450	1			T3	4		T68	30		T96	26
values[1]	490	1			T71	22		T44	10		T97	36
values[2]	362	1			T4	28		T10	14		T42	8
values[3]	390	1			T102	10		T90	2		T172	8
values[4]	332	1			T8	12		T173	18		T74	20
values[5]	420	1			T9	14		T174	26		T175	18
values[6]	358	1			T11	12		T27	6		T76	2
values[7]	304	1			T129	4		T176	2		T29	32

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	250	1			T4	28		T91	2		T98	6
values[1]	386	1			T68	30		T173	18		T74	20
values[2]	440	1			T8	12		T172	8		T129	4
values[3]	324	1			T102	10		T174	26		T44	10
values[4]	486	1			T10	14		T43	28		T71	22
values[5]	310	1			T9	14		T96	26		T77	4
values[6]	506	1			T3	4		T97	36		T90	2
values[7]	404	1			T11	12		T27	6		T42	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3060

1

T3

4

T4

22

T8

12

auto[1]

46

1

T4

6

T72

4

T73

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	53	75	58.59	53

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	8
[auto[1]]	[values[3]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[4]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[1]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[2]]	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	6
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[4]]	[values[4]]	0	1	1
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	7
[auto[1]]	[values[6]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[6]]	[values[3] , values[4] , values[5] , values[6]]	--	--	4
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[7]]	[values[5]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	42	1			T177	2		T178	6		T179	34
auto[0]	values[0]	values[1]	30	1			T68	30		-	-		-	-
auto[0]	values[0]	values[2]	22	1			T180	8		T181	10		T182	2
auto[0]	values[0]	values[3]	26	1			T183	18		T184	8		-	-
auto[0]	values[0]	values[4]	102	1			T95	16		T185	4		T186	16
auto[0]	values[0]	values[5]	26	1			T96	26		-	-		-	-
auto[0]	values[0]	values[6]	132	1			T3	4		T187	28		T188	6
auto[0]	values[0]	values[7]	70	1			T189	14		T190	20		T92	4
auto[0]	values[1]	values[0]	12	1			T191	8		T192	4		-	-
auto[0]	values[1]	values[1]	60	1			T193	26		T194	34		-	-
auto[0]	values[1]	values[2]	74	1			T94	18		T195	10		T55	18
auto[0]	values[1]	values[3]	80	1			T44	10		T196	18		T197	2
auto[0]	values[1]	values[4]	52	1			T71	22		T198	14		T56	12
auto[0]	values[1]	values[5]	62	1			T199	26		T200	20		T201	16
auto[0]	values[1]	values[6]	104	1			T97	36		T202	26		T203	30
auto[0]	values[1]	values[7]	40	1			T204	12		T205	10		T206	18
auto[0]	values[2]	values[0]	36	1			T4	22		T207	2		T208	6
auto[0]	values[2]	values[1]	40	1			T209	16		T210	24		-	-
auto[0]	values[2]	values[2]	52	1			T211	2		T212	12		T213	14
auto[0]	values[2]	values[3]	10	1			T109	4		T214	6		-	-
auto[0]	values[2]	values[4]	104	1			T10	14		T43	28		T215	24
auto[0]	values[2]	values[5]	40	1			T77	4		T216	2		T100	8
auto[0]	values[2]	values[6]	28	1			T217	28		-	-		-	-
auto[0]	values[2]	values[7]	44	1			T42	8		T103	22		T73	2
auto[0]	values[3]	values[0]	30	1			T218	30		-	-		-	-
auto[0]	values[3]	values[1]	60	1			T219	2		T123	22		T220	36
auto[0]	values[3]	values[2]	80	1			T172	8		T221	10		T222	16
auto[0]	values[3]	values[3]	18	1			T102	10		T223	6		T224	2
auto[0]	values[3]	values[4]	52	1			T225	4		T226	12		T227	36
auto[0]	values[3]	values[5]	28	1			T228	28		-	-		-	-
auto[0]	values[3]	values[6]	70	1			T90	2		T229	6		T117	8
auto[0]	values[3]	values[7]	52	1			T75	34		T230	18		-	-
auto[0]	values[4]	values[1]	92	1			T173	18		T74	20		T231	22
auto[0]	values[4]	values[2]	20	1			T8	12		T232	8		-	-
auto[0]	values[4]	values[3]	52	1			T79	22		T233	6		T234	18
auto[0]	values[4]	values[4]	10	1			T235	10		-	-		-	-
auto[0]	values[4]	values[5]	58	1			T72	32		T86	26		-	-
auto[0]	values[4]	values[6]	64	1			T236	4		T53	26		T237	10
auto[0]	values[4]	values[7]	28	1			T238	24		T239	4		-	-
auto[0]	values[5]	values[0]	70	1			T28	38		T78	20		T240	2
auto[0]	values[5]	values[1]	22	1			T241	16		T242	4		T243	2
auto[0]	values[5]	values[2]	50	1			T45	16		T244	24		T245	4
auto[0]	values[5]	values[3]	68	1			T174	26		T175	18		T246	2
auto[0]	values[5]	values[4]	50	1			T247	16		T248	10		T249	16
auto[0]	values[5]	values[5]	58	1			T9	14		T250	22		T251	4
auto[0]	values[5]	values[6]	68	1			T252	32		T253	24		T254	6
auto[0]	values[5]	values[7]	24	1			T255	6		T256	12		T257	4
auto[0]	values[6]	values[0]	30	1			T91	2		T98	6		T258	6
auto[0]	values[6]	values[1]	74	1			T259	12		T260	30		T261	32
auto[0]	values[6]	values[2]	64	1			T80	16		T262	20		T121	16
auto[0]	values[6]	values[3]	20	1			T263	10		T99	10		-	-
auto[0]	values[6]	values[4]	38	1			T264	18		T265	20		-	-
auto[0]	values[6]	values[5]	2	1			T266	2		-	-		-	-
auto[0]	values[6]	values[6]	4	1			T267	4		-	-		-	-
auto[0]	values[6]	values[7]	120	1			T11	12		T27	6		T76	2
auto[0]	values[7]	values[0]	14	1			T268	4		T269	4		T270	4
auto[0]	values[7]	values[1]	8	1			T271	8		-	-		-	-
auto[0]	values[7]	values[2]	76	1			T129	4		T29	32		T272	22
auto[0]	values[7]	values[3]	42	1			T273	14		T274	28		-	-
auto[0]	values[7]	values[4]	76	1			T275	2		T276	10		T277	6
auto[0]	values[7]	values[5]	32	1			T176	2		T278	30		-	-
auto[0]	values[7]	values[6]	30	1			T81	10		T279	12		T280	6
auto[0]	values[7]	values[7]	18	1			T82	16		T281	2		-	-
auto[1]	values[1]	values[3]	6	1			T83	6		-	-		-	-
auto[1]	values[2]	values[0]	6	1			T4	6		-	-		-	-
auto[1]	values[2]	values[7]	2	1			T73	2		-	-		-	-
auto[1]	values[4]	values[3]	2	1			T79	2		-	-		-	-
auto[1]	values[4]	values[5]	4	1			T72	4		-	-		-	-
auto[1]	values[4]	values[6]	2	1			T84	2		-	-		-	-
auto[1]	values[5]	values[0]	10	1			T78	10		-	-		-	-
auto[1]	values[6]	values[2]	2	1			T80	2		-	-		-	-
auto[1]	values[6]	values[7]	4	1			T282	4		-	-		-	-
auto[1]	values[7]	values[4]	2	1			T283	2		-	-		-	-
auto[1]	values[7]	values[6]	4	1			T81	4		-	-		-	-
auto[1]	values[7]	values[7]	2	1			T82	2		-	-		-	-