Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1438

1

T12

3

T15

2

T19

30

auto[1]

1431

1

T12

3

T19

23

T21

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

674

1

T15

2

T16

3

T17

20

auto[1]

2195

1

T12

6

T19

53

T21

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2601

1

T12

6

T19

53

T21

9

auto[1]

268

1

T15

2

T16

2

T17

11

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	552	1			T12	1		T15	1		T19	12
valid[1]	594	1			T15	1		T19	13		T21	2
valid[2]	596	1			T12	3		T19	10		T21	2
valid[3]	561	1			T19	9		T16	1		T22	6
valid[4]	566	1			T12	2		T19	9		T21	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	34	1			T111	1		T114	1		T115	3
auto[0]	auto[0]	valid[0]	auto[1]	200	1			T12	1		T19	7		T23	3
auto[0]	auto[0]	valid[1]	auto[0]	49	1			T17	2		T60	1		T113	1
auto[0]	auto[0]	valid[1]	auto[1]	229	1			T19	6		T21	1		T22	3
auto[0]	auto[0]	valid[2]	auto[0]	47	1			T16	1		T17	1		T65	1
auto[0]	auto[0]	valid[2]	auto[1]	235	1			T12	1		T19	5		T21	1
auto[0]	auto[0]	valid[3]	auto[0]	30	1			T60	1		T64	1		T113	1
auto[0]	auto[0]	valid[3]	auto[1]	208	1			T19	7		T22	4		T23	1
auto[0]	auto[0]	valid[4]	auto[0]	37	1			T377	1		T111	2		T115	2
auto[0]	auto[0]	valid[4]	auto[1]	228	1			T12	1		T19	5		T21	1
auto[0]	auto[1]	valid[0]	auto[0]	36	1			T65	1		T113	1		T111	1
auto[0]	auto[1]	valid[0]	auto[1]	218	1			T19	5		T21	1		T22	1
auto[0]	auto[1]	valid[1]	auto[0]	53	1			T17	2		T65	1		T111	3
auto[0]	auto[1]	valid[1]	auto[1]	219	1			T19	7		T21	1		T22	2
auto[0]	auto[1]	valid[2]	auto[0]	43	1			T17	1		T60	1		T377	1
auto[0]	auto[1]	valid[2]	auto[1]	214	1			T12	2		T19	5		T21	1
auto[0]	auto[1]	valid[3]	auto[0]	40	1			T63	1		T377	1		T111	3
auto[0]	auto[1]	valid[3]	auto[1]	234	1			T19	2		T22	2		T23	2
auto[0]	auto[1]	valid[4]	auto[0]	37	1			T17	3		T65	1		T113	2
auto[0]	auto[1]	valid[4]	auto[1]	210	1			T12	1		T19	4		T21	3
auto[1]	auto[0]	valid[0]	auto[0]	39	1			T15	1		T113	2		T114	1
auto[1]	auto[0]	valid[1]	auto[0]	23	1			T15	1		T16	1		T17	1
auto[1]	auto[0]	valid[2]	auto[0]	31	1			T113	1		T375	1		T115	1
auto[1]	auto[0]	valid[3]	auto[0]	22	1			T16	1		T17	2		T114	2
auto[1]	auto[0]	valid[4]	auto[0]	26	1			T64	1		T113	1		T115	3
auto[1]	auto[1]	valid[0]	auto[0]	25	1			T17	1		T377	1		T111	1
auto[1]	auto[1]	valid[1]	auto[0]	21	1			T17	1		T65	2		T377	1
auto[1]	auto[1]	valid[2]	auto[0]	26	1			T17	1		T65	1		T113	1
auto[1]	auto[1]	valid[3]	auto[0]	27	1			T17	2		T63	1		T377	1
auto[1]	auto[1]	valid[4]	auto[0]	28	1			T17	3		T377	1		T375	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal