Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17469

1

T15

20

T16

19

T17

396

auto[1]

20646

1

T12

6

T19

664

T21

89

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31835

1

T12

6

T15

10

T19

664

auto[1]

6280

1

T15

10

T16

8

T17

142

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19906	1			T12	6		T15	11		T19	334
others[1]	3208	1			T15	3		T19	61		T21	7
others[2]	3134	1			T15	1		T19	48		T21	8
others[3]	3626	1			T15	4		T19	58		T21	10
interest[1]	2095	1			T19	42		T21	3		T16	1
interest[4]	13289	1			T12	6		T15	7		T19	228
interest[64]	6146	1			T15	1		T19	121		T21	14

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5769	1			T15	4		T16	7		T17	133
auto[0]	auto[0]	others[1]	931	1			T15	2		T17	21		T60	1
auto[0]	auto[0]	others[2]	969	1			T16	1		T17	18		T60	9
auto[0]	auto[0]	others[3]	1078	1			T15	3		T16	1		T17	24
auto[0]	auto[0]	interest[1]	659	1			T16	1		T17	11		T60	6
auto[0]	auto[0]	interest[4]	3844	1			T15	2		T16	5		T17	80
auto[0]	auto[0]	interest[64]	1783	1			T15	1		T16	1		T17	47
auto[0]	auto[1]	others[0]	10922	1			T12	6		T19	334		T21	47
auto[0]	auto[1]	others[1]	1724	1			T19	61		T21	7		T112	37
auto[0]	auto[1]	others[2]	1630	1			T19	48		T21	8		T112	45
auto[0]	auto[1]	others[3]	1952	1			T19	58		T21	10		T112	50
auto[0]	auto[1]	interest[1]	1073	1			T19	42		T21	3		T112	25
auto[0]	auto[1]	interest[4]	7306	1			T12	6		T19	228		T21	38
auto[0]	auto[1]	interest[64]	3345	1			T19	121		T21	14		T112	114
auto[1]	auto[0]	others[0]	3215	1			T15	7		T16	4		T17	52
auto[1]	auto[0]	others[1]	553	1			T15	1		T16	1		T17	16
auto[1]	auto[0]	others[2]	535	1			T15	1		T17	15		T60	2
auto[1]	auto[0]	others[3]	596	1			T15	1		T16	1		T17	13
auto[1]	auto[0]	interest[1]	363	1			T17	15		T60	4		T61	1
auto[1]	auto[0]	interest[4]	2139	1			T15	5		T16	1		T17	34
auto[1]	auto[0]	interest[64]	1018	1			T16	2		T17	31		T61	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal