Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	555	1			T13	31		T32	24		T40	4
all_values[1]	555	1			T13	31		T32	24		T40	4
all_values[2]	555	1			T13	31		T32	24		T40	4
all_values[3]	555	1			T13	31		T32	24		T40	4
all_values[4]	555	1			T13	31		T32	24		T40	4
all_values[5]	555	1			T13	31		T32	24		T40	4
all_values[6]	555	1			T13	31		T32	24		T40	4
all_values[7]	555	1			T13	31		T32	24		T40	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2404

1

T13

131

T32

101

T40

15

auto[1]

2036

1

T13

117

T32

91

T40

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1691

1

T13

79

T32

73

T40

12

auto[1]

2749

1

T13

169

T32

119

T40

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2471

1

T13

122

T32

114

T40

19

auto[1]

1969

1

T13

126

T32

78

T40

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	113	1			T13	2		T32	5		T40	2
all_values[0]	auto[0]	auto[0]	auto[1]	67	1			T13	3		T32	5		T40	1
all_values[0]	auto[0]	auto[1]	auto[0]	76	1			T13	5		T32	5		T39	1
all_values[0]	auto[0]	auto[1]	auto[1]	54	1			T13	2		T32	1		T360	1
all_values[0]	auto[1]	auto[0]	auto[1]	143	1			T13	11		T32	5		T40	1
all_values[0]	auto[1]	auto[1]	auto[1]	102	1			T13	8		T32	3		T39	4
all_values[1]	auto[0]	auto[0]	auto[0]	107	1			T13	6		T32	4		T39	3
all_values[1]	auto[0]	auto[0]	auto[1]	58	1			T13	1		T32	6		T39	5
all_values[1]	auto[0]	auto[1]	auto[0]	90	1			T13	8		T32	4		T39	1
all_values[1]	auto[0]	auto[1]	auto[1]	64	1			T13	5		T32	3		T40	2
all_values[1]	auto[1]	auto[0]	auto[1]	136	1			T13	8		T32	5		T40	1
all_values[1]	auto[1]	auto[1]	auto[1]	100	1			T13	3		T32	2		T40	1
all_values[2]	auto[0]	auto[0]	auto[0]	102	1			T13	5		T32	4		T39	5
all_values[2]	auto[0]	auto[0]	auto[1]	51	1			T13	3		T32	3		T40	1
all_values[2]	auto[0]	auto[1]	auto[0]	85	1			T13	1		T32	5		T40	2
all_values[2]	auto[0]	auto[1]	auto[1]	60	1			T13	4		T32	3		T360	2
all_values[2]	auto[1]	auto[0]	auto[1]	133	1			T13	8		T32	6		T39	5
all_values[2]	auto[1]	auto[1]	auto[1]	124	1			T13	10		T32	3		T40	1
all_values[3]	auto[0]	auto[0]	auto[0]	114	1			T13	4		T32	3		T39	6
all_values[3]	auto[0]	auto[0]	auto[1]	56	1			T13	4		T32	3		T39	2
all_values[3]	auto[0]	auto[1]	auto[0]	111	1			T13	6		T32	1		T39	6
all_values[3]	auto[0]	auto[1]	auto[1]	45	1			T13	2		T32	3		T40	1
all_values[3]	auto[1]	auto[0]	auto[1]	126	1			T13	10		T32	5		T39	3
all_values[3]	auto[1]	auto[1]	auto[1]	103	1			T13	5		T32	9		T40	3
all_values[4]	auto[0]	auto[0]	auto[0]	109	1			T13	3		T32	5		T40	1
all_values[4]	auto[0]	auto[0]	auto[1]	57	1			T13	4		T39	2		T361	3
all_values[4]	auto[0]	auto[1]	auto[0]	74	1			T13	5		T32	8		T39	3
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T13	5		T32	3		T40	1
all_values[4]	auto[1]	auto[0]	auto[1]	133	1			T13	9		T32	4		T40	2
all_values[4]	auto[1]	auto[1]	auto[1]	116	1			T13	5		T32	4		T39	4
all_values[5]	auto[0]	auto[0]	auto[0]	163	1			T13	7		T32	6		T40	3
all_values[5]	auto[0]	auto[1]	auto[0]	140	1			T13	8		T32	8		T39	6
all_values[5]	auto[1]	auto[0]	auto[1]	135	1			T13	7		T32	7		T40	1
all_values[5]	auto[1]	auto[1]	auto[1]	117	1			T13	9		T32	3		T39	3
all_values[6]	auto[0]	auto[0]	auto[0]	103	1			T13	8		T32	4		T40	1
all_values[6]	auto[0]	auto[0]	auto[1]	53	1			T13	2		T32	4		T39	1
all_values[6]	auto[0]	auto[1]	auto[0]	97	1			T13	5		T32	5		T40	3
all_values[6]	auto[0]	auto[1]	auto[1]	45	1			T13	3		T32	1		T39	5
all_values[6]	auto[1]	auto[0]	auto[1]	144	1			T13	7		T32	9		T39	5
all_values[6]	auto[1]	auto[1]	auto[1]	113	1			T13	6		T32	1		T39	7
all_values[7]	auto[0]	auto[0]	auto[0]	128	1			T13	4		T32	3		T39	8
all_values[7]	auto[0]	auto[0]	auto[1]	46	1			T13	4		T32	2		T361	2
all_values[7]	auto[0]	auto[1]	auto[0]	79	1			T13	2		T32	3		T39	5
all_values[7]	auto[0]	auto[1]	auto[1]	58	1			T13	1		T32	4		T40	1
all_values[7]	auto[1]	auto[0]	auto[1]	127	1			T13	11		T32	3		T40	1
all_values[7]	auto[1]	auto[1]	auto[1]	117	1			T13	9		T32	9		T40	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal