Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2766740	1			T1	1		T2	1035		T3	28714
all_values[1]	2766740	1			T1	1		T2	1035		T3	28714
all_values[2]	2766740	1			T1	1		T2	1035		T3	28714
all_values[3]	2766740	1			T1	1		T2	1035		T3	28714
all_values[4]	2766740	1			T1	1		T2	1035		T3	28714
all_values[5]	2766740	1			T1	1		T2	1035		T3	28714
all_values[6]	2766740	1			T1	1		T2	1035		T3	28714
all_values[7]	2766740	1			T1	1		T2	1035		T3	28714

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21672091

1

T1

8

T2

8280

T3

229712

auto[1]

461829

1

T9

44

T13

39673

T36

51

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22110432

1

T1

8

T2

8280

T3

229567

auto[1]

23488

1

T3

145

T4

218

T9

74

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2737067	1			T1	1		T2	1035		T3	28610
all_values[0]	auto[0]	auto[1]	11812	1			T3	104		T4	150		T9	19
all_values[0]	auto[1]	auto[0]	17405	1			T9	2		T13	1		T36	6
all_values[0]	auto[1]	auto[1]	456	1			T9	7		T13	2		T36	1
all_values[1]	auto[0]	auto[0]	2715622	1			T1	1		T2	1035		T3	28673
all_values[1]	auto[0]	auto[1]	5979	1			T3	41		T4	44		T9	20
all_values[1]	auto[1]	auto[0]	44671	1			T9	5		T13	7		T36	8
all_values[1]	auto[1]	auto[1]	468	1			T9	1		T13	2		T36	1
all_values[2]	auto[0]	auto[0]	2686938	1			T1	1		T2	1035		T3	28714
all_values[2]	auto[0]	auto[1]	2284	1			T4	24		T9	7		T13	30
all_values[2]	auto[1]	auto[0]	77257	1			T9	3		T13	2		T36	2
all_values[2]	auto[1]	auto[1]	261	1			T13	2		T36	1		T60	5
all_values[3]	auto[0]	auto[0]	2713233	1			T1	1		T2	1035		T3	28714
all_values[3]	auto[0]	auto[1]	234	1			T9	4		T13	3		T36	1
all_values[3]	auto[1]	auto[0]	53087	1			T9	4		T13	1		T36	5
all_values[3]	auto[1]	auto[1]	186	1			T9	1		T13	3		T36	1
all_values[4]	auto[0]	auto[0]	2747672	1			T1	1		T2	1035		T3	28714
all_values[4]	auto[0]	auto[1]	193	1			T9	1		T13	1		T141	1
all_values[4]	auto[1]	auto[0]	18637	1			T9	2		T13	4		T36	7
all_values[4]	auto[1]	auto[1]	238	1			T9	4		T13	3		T60	4
all_values[5]	auto[0]	auto[0]	2724374	1			T1	1		T2	1035		T3	28714
all_values[5]	auto[0]	auto[1]	316	1			T9	1		T10	4		T13	1
all_values[5]	auto[1]	auto[0]	41865	1			T9	4		T13	2		T36	5
all_values[5]	auto[1]	auto[1]	185	1			T9	2		T13	2		T36	1
all_values[6]	auto[0]	auto[0]	2663556	1			T1	1		T2	1035		T3	28714
all_values[6]	auto[0]	auto[1]	220	1			T9	2		T13	3		T36	1
all_values[6]	auto[1]	auto[0]	102761	1			T9	2		T13	2		T36	3
all_values[6]	auto[1]	auto[1]	203	1			T9	3		T13	4		T36	4
all_values[7]	auto[0]	auto[0]	2662367	1			T1	1		T2	1035		T3	28714
all_values[7]	auto[0]	auto[1]	224	1			T36	3		T60	2		T74	4
all_values[7]	auto[1]	auto[0]	103920	1			T9	2		T13	39636		T36	3
all_values[7]	auto[1]	auto[1]	229	1			T9	2		T36	3		T60	4