Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	25906	1			T3	99		T4	125		T6	2
auto[SpiFlashAddrCfg]	5927	1			T3	33		T4	41		T9	5
auto[SpiFlashAddr3b]	6958	1			T3	51		T4	37		T6	4
auto[SpiFlashAddr4b]	5881	1			T1	6		T3	56		T4	40

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25730

1

T3

137

T4

130

T6

8

auto[1]

18942

1

T1

6

T3

102

T4

113

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24052

1

T1

6

T3

121

T4

135

auto[1]

20620

1

T3

118

T4

108

T6

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	29466	1			T1	4		T3	117		T4	154
values[1]	849	1			T3	11		T4	4		T9	1
values[2]	1151	1			T3	13		T4	8		T9	2
values[3]	1078	1			T3	10		T4	12		T11	2
values[4]	1091	1			T3	7		T4	6		T6	2
values[5]	1098	1			T3	12		T4	14		T11	3
values[6]	1238	1			T3	7		T4	2		T11	6
values[7]	1140	1			T3	9		T4	5		T9	1
values[8]	7561	1			T1	2		T3	53		T4	38

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21014

1

T1

6

T3

239

T6

8

auto[1]

23658

1

T4

243

T9

43

T11

258

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

43007

1

T1

2

T3

234

T4

229

write

1665

1

T1

4

T3

5

T4

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15449

1

T1

2

T3

114

T4

105

valids[0x1]

29223

1

T1

4

T3

125

T4

138

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1268	1			T3	15		T4	17		T9	1
internal_process_ops[0x5a]	1184	1			T3	8		T4	9		T6	2
internal_process_ops[0x05]	15023	1			T3	23		T4	35		T9	4
internal_process_ops[0x35]	1219	1			T3	8		T4	6		T6	2
internal_process_ops[0x15]	1210	1			T3	5		T4	11		T9	3
internal_process_ops[0x03]	815	1			T3	7		T4	5		T11	2
internal_process_ops[0x0b]	839	1			T3	5		T4	2		T9	1
internal_process_ops[0x3b]	856	1			T3	8		T4	4		T6	2
internal_process_ops[0x6b]	800	1			T3	9		T4	3		T9	2
internal_process_ops[0xbb]	827	1			T3	4		T4	5		T11	1
internal_process_ops[0xeb]	843	1			T3	7		T4	6		T11	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43819

1

T1

2

T3

236

T4

242

auto[1]

853

1

T1

4

T3

3

T4

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43061

1

T1

6

T3

231

T4

230

auto[1]

1611

1

T3

8

T4

13

T9

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

6677

1

T3

70

T6

2

T12

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4065

1

T3

28

T13

48

T22

43

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1687

1

T3

16

T13

32

T21

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1382

1

T3

14

T13

40

T22

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1906

1

T3

32

T6

4

T13

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1567

1

T3

19

T13

32

T22

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1596

1

T3

17

T6

2

T13

26

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1374

1

T1

2

T3

38

T13

24

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

37

1

T13

2

T23

2

T209

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

36

1

T22

1

T26

1

T185

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

50

1

T3

1

T22

2

T29

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

50

1

T26

5

T76

1

T31

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

57

1

T22

2

T23

1

T209

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

54

1

T3

1

T13

2

T26

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

34

1

T26

1

T76

3

T30

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

57

1

T3

2

T13

3

T23

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

53

1

T13

1

T21

2

T76

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

33

1

T22

2

T23

3

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

38

1

T22

1

T23

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

57

1

T22

3

T25

2

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

60

1

T3

1

T23

3

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

52

1

T165

2

T30

2

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

49

1

T13

2

T22

2

T23

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

43

1

T1

4

T25

2

T26

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8912

1

T4

72

T9

11

T11

90

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5851

1

T4

46

T9

6

T11

109

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1286

1

T4

22

T11

17

T16

22

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1130

1

T4

16

T9

3

T11

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1513

1

T4

14

T9

3

T11

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1555

1

T4

19

T9

8

T11

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1283

1

T4

17

T9

1

T11

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1223

1

T4

23

T9

6

T11

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

60

1

T4

2

T11

1

T16

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

54

1

T4

1

T32

1

T37

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

59

1

T4

4

T9

2

T16

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

55

1

T9

1

T16

1

T35

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

66

1

T4

2

T9

2

T11

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

65

1

T84

1

T255

1

T256

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

46

1

T4

1

T32

1

T74

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

63

1

T16

2

T84

2

T32

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

64

1

T35

1

T84

4

T32

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

75

1

T11

3

T35

1

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

52

1

T4

4

T84

2

T60

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

45

1

T16

4

T256

2

T257

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

41

1

T32

1

T74

1

T258

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

63

1

T11

2

T16

3

T32

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

46

1

T16

1

T32

1

T74

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

51

1

T36

4

T75

2

T256

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3112	1			T3	40		T13	49		T24	4
auto[0]	values[0]	valids[0x1]	9666	1			T1	4		T3	77		T6	2
auto[0]	values[1]	valids[0x1]	428	1			T3	11		T13	10		T22	7
auto[0]	values[2]	valids[0x0]	409	1			T3	10		T13	13		T22	6
auto[0]	values[2]	valids[0x1]	183	1			T3	3		T13	5		T22	4
auto[0]	values[3]	valids[0x0]	365	1			T3	9		T13	12		T22	9
auto[0]	values[3]	valids[0x1]	222	1			T3	1		T13	1		T22	6
auto[0]	values[4]	valids[0x0]	414	1			T3	5		T6	2		T13	6
auto[0]	values[4]	valids[0x1]	223	1			T3	2		T13	9		T22	4
auto[0]	values[5]	valids[0x0]	392	1			T3	6		T13	7		T22	5
auto[0]	values[5]	valids[0x1]	194	1			T3	6		T13	3		T22	5
auto[0]	values[6]	valids[0x0]	419	1			T3	5		T13	9		T22	11
auto[0]	values[6]	valids[0x1]	272	1			T3	2		T13	7		T22	5
auto[0]	values[7]	valids[0x0]	400	1			T3	5		T13	3		T22	14
auto[0]	values[7]	valids[0x1]	216	1			T3	4		T13	1		T22	5
auto[0]	values[8]	valids[0x0]	2597	1			T1	2		T3	34		T6	2
auto[0]	values[8]	valids[0x1]	1502	1			T3	19		T6	2		T13	33
auto[1]	values[0]	valids[0x0]	3417	1			T4	56		T9	5		T11	23
auto[1]	values[0]	valids[0x1]	13271	1			T4	98		T9	21		T11	201
auto[1]	values[1]	valids[0x1]	421	1			T4	4		T9	1		T11	1
auto[1]	values[2]	valids[0x0]	327	1			T4	2		T9	2		T16	12
auto[1]	values[2]	valids[0x1]	232	1			T4	6		T16	5		T35	1
auto[1]	values[3]	valids[0x0]	307	1			T4	4		T11	2		T16	2
auto[1]	values[3]	valids[0x1]	184	1			T4	8		T16	3		T35	4
auto[1]	values[4]	valids[0x0]	293	1			T4	6		T9	2		T16	4
auto[1]	values[4]	valids[0x1]	161	1			T16	4		T259	3		T32	7
auto[1]	values[5]	valids[0x0]	312	1			T4	10		T11	3		T16	2
auto[1]	values[5]	valids[0x1]	200	1			T4	4		T16	8		T84	6
auto[1]	values[6]	valids[0x0]	288	1			T4	1		T11	4		T16	4
auto[1]	values[6]	valids[0x1]	259	1			T4	1		T11	2		T16	7
auto[1]	values[7]	valids[0x0]	342	1			T4	5		T9	1		T11	1
auto[1]	values[7]	valids[0x1]	182	1			T11	2		T16	4		T35	1
auto[1]	values[8]	valids[0x0]	2055	1			T4	21		T9	8		T11	7
auto[1]	values[8]	valids[0x1]	1407	1			T4	17		T9	3		T11	12