Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2687382

1

T1

1

T3

10633

T4

10741

auto[1]

13801

1

T3

19

T4

23

T9

3

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

925084

1

T1

1

T3

55

T4

65

auto[1]

1776099

1

T3

10597

T4

10699

T6

1024

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	425929	1			T1	1		T3	3237		T4	538
auto[524288:1048575]	332899	1			T3	217		T4	2776		T11	447
auto[1048576:1572863]	345954	1			T3	1045		T4	180		T9	131
auto[1572864:2097151]	326687	1			T3	3105		T4	523		T9	706
auto[2097152:2621439]	317165	1			T3	328		T4	1908		T11	514
auto[2621440:3145727]	310866	1			T3	1726		T4	2243		T9	1
auto[3145728:3670015]	312527	1			T3	134		T4	11		T11	86
auto[3670016:4194303]	329156	1			T3	860		T4	2585		T9	257

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1794980

1

T1

1

T3

10651

T4

10763

auto[1]

906203

1

T3

1

T4

1

T11

6

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2319288

1

T1

1

T3

9876

T4

7876

auto[1]

381895

1

T3

776

T4

2888

T9

142

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	156752	1			T1	1		T3	3		T4	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	218826	1			T3	3229		T4	535		T6	1024
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	88683	1			T3	3		T4	7		T11	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	185874	1			T3	212		T4	2766		T11	387
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	110766	1			T3	5		T4	5		T9	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	185310	1			T3	770		T4	169		T9	128
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	137318	1			T3	6		T4	3		T9	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	146884	1			T3	3097		T4	519		T9	561
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	107538	1			T3	13		T4	5		T11	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	164388	1			T3	308		T4	1128		T11	512
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	106007	1			T3	2		T4	8		T9	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	144932	1			T3	1354		T4	386		T11	260
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	103294	1			T4	5		T11	9		T12	212
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	163745	1			T4	1		T11	20		T13	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	100370	1			T3	3		T4	5		T9	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	187645	1			T3	857		T4	2309		T9	256
auto[0]	auto[1]	auto[0:524287]	auto[0]	2346	1			T3	1		T11	1		T13	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	45875	1			T3	1		T13	1		T32	44
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	277	1			T3	2		T13	2		T16	6
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	55918	1			T11	5		T13	512		T16	1546
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2108	1			T3	4		T4	1		T9	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	46422	1			T3	257		T16	133		T22	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	484	1			T9	7		T11	1		T13	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	40815	1			T9	132		T11	2		T13	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	790	1			T3	2		T4	2		T13	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	42544	1			T4	772		T13	512		T16	257
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2593	1			T3	1		T4	4		T13	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	55666	1			T3	369		T4	1842		T13	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	334	1			T3	2		T4	2		T16	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	43104	1			T3	132		T16	256		T35	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	3811	1			T4	2		T22	1		T23	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	35963	1			T4	262		T13	256		T22	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	242	1			T3	1		T21	6		T35	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	1625	1			T3	1		T21	39		T35	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	156	1			T4	2		T11	2		T16	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1541	1			T4	1		T11	47		T16	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	153	1			T3	2		T4	2		T13	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	950	1			T3	3		T4	3		T13	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	99	1			T3	1		T4	1		T9	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	721	1			T3	1		T9	1		T22	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	182	1			T3	2		T4	1		T16	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1463	1			T3	3		T16	1		T22	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	139	1			T4	2		T11	1		T16	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1064	1			T4	1		T11	31		T16	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	153	1			T4	1		T11	4		T13	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1389	1			T4	2		T11	53		T13	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	151	1			T4	3		T11	1		T16	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	928	1			T4	3		T11	5		T22	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	41	1			T3	1		T13	1		T32	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	222	1			T13	1		T32	20		T74	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	54	1			T16	4		T23	1		T32	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	396	1			T16	1		T23	1		T32	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	26	1			T3	1		T75	2		T31	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	219	1			T3	3		T75	25		T31	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	46	1			T9	1		T11	1		T13	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	320	1			T11	13		T13	1		T36	18
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	43	1			T16	1		T32	1		T26	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	217	1			T16	1		T32	6		T26	29
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	40	1			T13	1		T23	1		T32	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	425	1			T13	2		T32	17		T74	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	45	1			T35	2		T32	2		T74	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	463	1			T35	10		T32	17		T74	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	43	1			T4	1		T23	2		T74	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	245	1			T23	3		T75	4		T77	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1412750	1			T1	1		T3	9862		T4	7854
auto[0]	auto[0]	auto[1]	895582	1			T11	4		T12	7839		T86	20525
auto[0]	auto[1]	auto[0]	368736	1			T3	771		T4	2887		T9	141
auto[0]	auto[1]	auto[1]	10314	1			T35	2		T32	2		T26	1
auto[1]	auto[0]	auto[0]	10707	1			T3	13		T4	21		T9	2
auto[1]	auto[0]	auto[1]	249	1			T3	1		T4	1		T11	2
auto[1]	auto[1]	auto[0]	2787	1			T3	5		T4	1		T9	1
auto[1]	auto[1]	auto[1]	58	1			T23	1		T32	1		T26	1