Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12248

1

T3

137

T6

8

T12

4

auto[1]

8766

1

T1

6

T3

102

T13

149

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2626	1			T3	20		T13	44		T22	22
values[1]	2818	1			T3	40		T13	40		T21	59
values[2]	2578	1			T1	6		T3	72		T13	23
values[3]	2869	1			T3	43		T13	20		T22	89
values[4]	2595	1			T13	40		T24	4		T93	12
values[5]	2265	1			T3	40		T13	40		T22	22
values[6]	2756	1			T3	24		T12	4		T13	40
values[7]	2507	1			T6	8		T13	52		T22	46

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2559	1			T1	6		T13	20		T22	40
values[1]	2751	1			T3	69		T6	8		T12	4
values[2]	2948	1			T3	40		T13	44		T22	48
values[3]	2653	1			T3	20		T13	40		T22	22
values[4]	2598	1			T3	23		T13	20		T21	59
values[5]	2382	1			T13	43		T22	26		T93	12
values[6]	2893	1			T3	40		T13	40		T23	68
values[7]	2230	1			T3	47		T13	20		T22	83

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	208	1			T205	12		T76	28		T30	10
auto[0]	values[0]	values[1]	202	1			T23	24		T74	11		T215	20
auto[0]	values[0]	values[2]	219	1			T3	15		T13	16		T209	18
auto[0]	values[0]	values[3]	133	1			T295	4		T296	2		T44	13
auto[0]	values[0]	values[4]	153	1			T29	13		T225	8		T245	89
auto[0]	values[0]	values[5]	286	1			T23	25		T32	16		T217	32
auto[0]	values[0]	values[6]	138	1			T74	10		T76	14		T30	11
auto[0]	values[0]	values[7]	76	1			T22	12		T44	12		T45	22
auto[0]	values[1]	values[0]	154	1			T29	15		T30	8		T297	10
auto[0]	values[1]	values[1]	190	1			T182	6		T31	23		T82	13
auto[0]	values[1]	values[2]	137	1			T3	10		T31	14		T298	10
auto[0]	values[1]	values[3]	209	1			T13	12		T30	22		T164	15
auto[0]	values[1]	values[4]	192	1			T21	59		T23	12		T165	10
auto[0]	values[1]	values[5]	198	1			T22	13		T185	5		T214	24
auto[0]	values[1]	values[6]	258	1			T3	11		T23	25		T32	6
auto[0]	values[1]	values[7]	268	1			T13	11		T22	22		T23	11
auto[0]	values[2]	values[0]	301	1			T32	56		T31	10		T181	12
auto[0]	values[2]	values[1]	206	1			T3	17		T30	10		T82	16
auto[0]	values[2]	values[2]	192	1			T211	16		T82	13		T224	13
auto[0]	values[2]	values[3]	224	1			T82	97		T39	20		T169	60
auto[0]	values[2]	values[4]	166	1			T22	7		T23	13		T30	10
auto[0]	values[2]	values[5]	131	1			T13	9		T26	14		T212	16
auto[0]	values[2]	values[6]	174	1			T3	8		T76	30		T30	25
auto[0]	values[2]	values[7]	187	1			T3	16		T30	12		T183	8
auto[0]	values[3]	values[0]	140	1			T13	8		T22	13		T46	2
auto[0]	values[3]	values[1]	255	1			T22	10		T23	14		T165	15
auto[0]	values[3]	values[2]	216	1			T22	17		T23	10		T76	17
auto[0]	values[3]	values[3]	206	1			T31	18		T185	46		T193	9
auto[0]	values[3]	values[4]	139	1			T3	15		T162	2		T185	11
auto[0]	values[3]	values[5]	196	1			T167	6		T74	8		T208	6
auto[0]	values[3]	values[6]	214	1			T29	16		T299	10		T181	13
auto[0]	values[3]	values[7]	335	1			T3	10		T22	14		T32	14
auto[0]	values[4]	values[0]	316	1			T193	15		T187	14		T163	11
auto[0]	values[4]	values[1]	235	1			T13	11		T24	4		T206	14
auto[0]	values[4]	values[2]	246	1			T76	14		T165	11		T278	14
auto[0]	values[4]	values[3]	219	1			T70	4		T76	10		T288	12
auto[0]	values[4]	values[4]	204	1			T32	15		T272	10		T196	8
auto[0]	values[4]	values[5]	150	1			T93	12		T179	9		T300	14
auto[0]	values[4]	values[6]	202	1			T13	13		T30	11		T224	20
auto[0]	values[4]	values[7]	89	1			T176	24		T233	10		T225	11
auto[0]	values[5]	values[0]	100	1			T76	14		T173	2		T82	15
auto[0]	values[5]	values[1]	159	1			T3	10		T13	11		T23	13
auto[0]	values[5]	values[2]	212	1			T275	4		T26	37		T199	22
auto[0]	values[5]	values[3]	145	1			T3	10		T22	15		T82	17
auto[0]	values[5]	values[4]	299	1			T13	9		T26	12		T30	47
auto[0]	values[5]	values[5]	178	1			T219	12		T178	10		T30	8
auto[0]	values[5]	values[6]	122	1			T23	13		T31	15		T301	22
auto[0]	values[5]	values[7]	134	1			T32	8		T76	10		T201	18
auto[0]	values[6]	values[0]	150	1			T22	6		T31	18		T89	8
auto[0]	values[6]	values[1]	195	1			T3	15		T12	4		T22	13
auto[0]	values[6]	values[2]	376	1			T100	14		T32	13		T185	90
auto[0]	values[6]	values[3]	157	1			T13	12		T32	11		T82	10
auto[0]	values[6]	values[4]	171	1			T200	2		T32	19		T30	11
auto[0]	values[6]	values[5]	196	1			T23	11		T31	12		T302	6
auto[0]	values[6]	values[6]	316	1			T13	19		T74	15		T177	6
auto[0]	values[6]	values[7]	74	1			T172	2		T32	13		T29	11
auto[0]	values[7]	values[0]	137	1			T76	12		T240	9		T291	8
auto[0]	values[7]	values[1]	257	1			T6	8		T13	9		T218	12
auto[0]	values[7]	values[2]	77	1			T22	12		T30	12		T193	9
auto[0]	values[7]	values[3]	136	1			T26	13		T39	14		T269	14
auto[0]	values[7]	values[4]	164	1			T22	20		T30	20		T303	20
auto[0]	values[7]	values[5]	175	1			T13	10		T304	10		T164	8
auto[0]	values[7]	values[6]	136	1			T26	13		T31	14		T305	14
auto[0]	values[7]	values[7]	218	1			T195	2		T26	52		T165	17
auto[1]	values[0]	values[0]	229	1			T76	10		T30	53		T39	9
auto[1]	values[0]	values[1]	117	1			T23	18		T74	11		T76	23
auto[1]	values[0]	values[2]	199	1			T3	5		T13	28		T76	15
auto[1]	values[0]	values[3]	106	1			T44	7		T229	4		T230	9
auto[1]	values[0]	values[4]	75	1			T29	7		T170	18		T306	20
auto[1]	values[0]	values[5]	139	1			T23	15		T32	11		T30	7
auto[1]	values[0]	values[6]	232	1			T74	10		T76	49		T30	23
auto[1]	values[0]	values[7]	114	1			T22	10		T180	2		T44	8
auto[1]	values[1]	values[0]	154	1			T29	33		T30	12		T187	7
auto[1]	values[1]	values[1]	87	1			T31	5		T82	10		T163	15
auto[1]	values[1]	values[2]	246	1			T3	10		T31	32		T193	49
auto[1]	values[1]	values[3]	227	1			T13	8		T30	6		T164	5
auto[1]	values[1]	values[4]	91	1			T23	8		T165	10		T31	13
auto[1]	values[1]	values[5]	144	1			T22	13		T160	16		T185	15
auto[1]	values[1]	values[6]	140	1			T3	9		T23	23		T32	14
auto[1]	values[1]	values[7]	123	1			T13	9		T22	19		T23	9
auto[1]	values[2]	values[0]	92	1			T1	6		T32	9		T31	11
auto[1]	values[2]	values[1]	92	1			T3	8		T30	25		T82	4
auto[1]	values[2]	values[2]	160	1			T82	7		T224	7		T248	12
auto[1]	values[2]	values[3]	118	1			T82	3		T39	5		T169	5
auto[1]	values[2]	values[4]	161	1			T22	13		T23	10		T161	6
auto[1]	values[2]	values[5]	126	1			T13	14		T26	37		T240	8
auto[1]	values[2]	values[6]	112	1			T3	12		T76	23		T30	32
auto[1]	values[2]	values[7]	136	1			T3	11		T27	20		T30	12
auto[1]	values[3]	values[0]	119	1			T13	12		T22	7		T29	5
auto[1]	values[3]	values[1]	202	1			T22	11		T23	34		T165	5
auto[1]	values[3]	values[2]	188	1			T22	11		T23	13		T76	3
auto[1]	values[3]	values[3]	150	1			T31	7		T185	5		T193	11
auto[1]	values[3]	values[4]	119	1			T3	8		T185	9		T164	20
auto[1]	values[3]	values[5]	66	1			T74	14		T82	12		T193	12
auto[1]	values[3]	values[6]	192	1			T25	12		T29	4		T181	63
auto[1]	values[3]	values[7]	132	1			T3	10		T22	6		T32	6
auto[1]	values[4]	values[0]	102	1			T193	5		T187	10		T163	9
auto[1]	values[4]	values[1]	108	1			T13	9		T69	6		T31	12
auto[1]	values[4]	values[2]	93	1			T76	6		T165	9		T181	2
auto[1]	values[4]	values[3]	213	1			T76	18		T210	41		T169	19
auto[1]	values[4]	values[4]	86	1			T32	11		T18	7		T248	11
auto[1]	values[4]	values[5]	47	1			T179	11		T42	6		T252	14
auto[1]	values[4]	values[6]	246	1			T13	7		T30	73		T224	7
auto[1]	values[4]	values[7]	39	1			T233	12		T225	9		T238	7
auto[1]	values[5]	values[0]	47	1			T76	6		T82	6		T155	10
auto[1]	values[5]	values[1]	94	1			T3	10		T13	9		T23	7
auto[1]	values[5]	values[2]	84	1			T26	13		T239	26		T307	10
auto[1]	values[5]	values[3]	126	1			T3	10		T22	7		T82	8
auto[1]	values[5]	values[4]	286	1			T13	11		T26	84		T52	22
auto[1]	values[5]	values[5]	132	1			T30	12		T82	11		T181	19
auto[1]	values[5]	values[6]	86	1			T23	7		T31	9		T45	15
auto[1]	values[5]	values[7]	61	1			T32	12		T76	10		T185	5
auto[1]	values[6]	values[0]	214	1			T22	14		T31	6		T193	9
auto[1]	values[6]	values[1]	105	1			T3	9		T22	7		T76	8
auto[1]	values[6]	values[2]	221	1			T32	9		T185	2		T39	11
auto[1]	values[6]	values[3]	127	1			T13	8		T32	9		T82	10
auto[1]	values[6]	values[4]	104	1			T66	12		T32	1		T28	20
auto[1]	values[6]	values[5]	119	1			T23	37		T31	8		T236	4
auto[1]	values[6]	values[6]	159	1			T13	1		T74	5		T82	9
auto[1]	values[6]	values[7]	72	1			T32	19		T29	34		T164	4
auto[1]	values[7]	values[0]	96	1			T76	8		T240	11		T228	28
auto[1]	values[7]	values[1]	247	1			T13	23		T281	18		T39	10
auto[1]	values[7]	values[2]	82	1			T22	8		T30	8		T193	49
auto[1]	values[7]	values[3]	157	1			T26	26		T39	11		T236	10
auto[1]	values[7]	values[4]	188	1			T22	6		T30	6		T155	11
auto[1]	values[7]	values[5]	99	1			T13	10		T164	13		T181	15
auto[1]	values[7]	values[6]	166	1			T26	7		T31	6		T193	18
auto[1]	values[7]	values[7]	172	1			T26	28		T165	3		T31	14