Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	284	1			T3	2		T13	3		T22	4
auto[ReadAddrCrossIntoMailbox]	262	1			T3	2		T13	7		T22	13
auto[ReadAddrCrossOutOfMailbox]	250	1			T3	1		T13	4		T22	4
auto[ReadAddrCrossAllMailbox]	162	1			T3	3		T13	4		T22	5
auto[ReadAddrOutsideMailbox]	2691	1			T3	32		T6	2		T13	52

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1808

1

T3

19

T6

1

T13

30

auto[1]

1841

1

T3

21

T6

1

T13

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	603	1			T3	7		T13	11		T22	13
read_ops[0x0b]	613	1			T3	5		T13	12		T21	2
read_ops[0x3b]	628	1			T3	8		T6	2		T13	15
read_ops[0x6b]	584	1			T3	9		T13	10		T22	9
read_ops[0xbb]	618	1			T3	4		T13	11		T22	15
read_ops[0xeb]	603	1			T3	7		T13	11		T21	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T13	1		T74	1		T30	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T23	1		T30	1		T82	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T76	2		T82	1		T163	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T22	2		T23	1		T74	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T30	1		T163	2		T236	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T3	1		T22	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T22	1		T185	1		T177	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T3	1		T13	2		T31	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	210	1			T3	2		T13	5		T22	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	246	1			T3	3		T13	3		T22	6
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T218	1		T195	1		T176	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T3	1		T22	1		T218	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T22	1		T176	2		T26	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T3	1		T13	2		T22	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T13	1		T22	1		T23	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T23	3		T176	1		T76	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T23	1		T31	3		T187	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T3	1		T165	1		T309	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	220	1			T13	1		T21	1		T22	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	205	1			T3	2		T13	8		T21	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T22	1		T218	1		T23	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T3	1		T218	1		T23	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T13	1		T22	1		T205	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T3	1		T205	2		T176	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T13	1		T22	1		T176	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T23	1		T176	2		T74	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T23	1		T176	1		T39	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T176	1		T30	1		T229	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	227	1			T3	4		T6	1		T13	8
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	243	1			T3	2		T6	1		T13	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T22	1		T218	1		T199	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T22	1		T218	1		T76	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T13	1		T29	2		T30	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T22	3		T30	1		T163	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T13	1		T76	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T23	1		T74	1		T76	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T13	1		T22	1		T165	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T22	1		T23	1		T30	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	222	1			T3	7		T13	1		T23	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	203	1			T3	2		T13	6		T22	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T167	1		T76	1		T185	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	20	1			T23	1		T167	1		T76	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T13	1		T22	3		T205	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T22	1		T205	1		T179	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T74	2		T288	1		T29	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T13	1		T26	1		T288	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T76	1		T288	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T22	1		T288	1		T39	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	211	1			T3	1		T13	3		T22	8
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	242	1			T3	3		T13	6		T22	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T288	1		T199	2		T39	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T13	2		T76	1		T288	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T22	1		T32	1		T288	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T13	2		T74	1		T76	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T76	1		T165	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T22	1		T23	2		T30	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T13	1		T22	1		T205	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T3	1		T205	2		T288	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	216	1			T3	5		T13	3		T21	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	246	1			T3	1		T13	3		T21	1