Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2766740	1			T1	1		T2	1035		T3	28714
all_pins[1]	2766740	1			T1	1		T2	1035		T3	28714
all_pins[2]	2766740	1			T1	1		T2	1035		T3	28714
all_pins[3]	2766740	1			T1	1		T2	1035		T3	28714
all_pins[4]	2766740	1			T1	1		T2	1035		T3	28714
all_pins[5]	2766740	1			T1	1		T2	1035		T3	28714
all_pins[6]	2766740	1			T1	1		T2	1035		T3	28714
all_pins[7]	2766740	1			T1	1		T2	1035		T3	28714

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22028131	1			T1	8		T2	8280		T3	229712
values[0x1]	105789	1			T9	20		T13	18		T36	12
transitions[0x0=>0x1]	104038	1			T9	16		T13	17		T36	6
transitions[0x1=>0x0]	104048	1			T9	16		T13	17		T36	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2766274	1			T1	1		T2	1035		T3	28714
all_pins[0]	values[0x1]	466	1			T9	7		T13	2		T36	1
all_pins[0]	transitions[0x0=>0x1]	316	1			T9	6		T13	2		T36	1
all_pins[0]	transitions[0x1=>0x0]	332	1			T13	2		T36	1		T60	2
all_pins[1]	values[0x0]	2766258	1			T1	1		T2	1035		T3	28714
all_pins[1]	values[0x1]	482	1			T9	1		T13	2		T36	1
all_pins[1]	transitions[0x0=>0x1]	370	1			T9	1		T13	2		T36	1
all_pins[1]	transitions[0x1=>0x0]	156	1			T13	2		T36	1		T60	4
all_pins[2]	values[0x0]	2766472	1			T1	1		T2	1035		T3	28714
all_pins[2]	values[0x1]	268	1			T13	2		T36	1		T60	5
all_pins[2]	transitions[0x0=>0x1]	229	1			T13	2		T60	3		T74	2
all_pins[2]	transitions[0x1=>0x0]	147	1			T9	1		T13	3		T60	3
all_pins[3]	values[0x0]	2766554	1			T1	1		T2	1035		T3	28714
all_pins[3]	values[0x1]	186	1			T9	1		T13	3		T36	1
all_pins[3]	transitions[0x0=>0x1]	133	1			T9	1		T13	3		T36	1
all_pins[3]	transitions[0x1=>0x0]	185	1			T9	4		T13	3		T60	3
all_pins[4]	values[0x0]	2766502	1			T1	1		T2	1035		T3	28714
all_pins[4]	values[0x1]	238	1			T9	4		T13	3		T60	4
all_pins[4]	transitions[0x0=>0x1]	196	1			T9	4		T13	2		T60	3
all_pins[4]	transitions[0x1=>0x0]	1516	1			T9	2		T13	1		T36	1
all_pins[5]	values[0x0]	2765182	1			T1	1		T2	1035		T3	28714
all_pins[5]	values[0x1]	1558	1			T9	2		T13	2		T36	1
all_pins[5]	transitions[0x0=>0x1]	324	1			T13	2		T60	4		T74	12
all_pins[5]	transitions[0x1=>0x0]	101128	1			T9	1		T13	4		T36	3
all_pins[6]	values[0x0]	2664378	1			T1	1		T2	1035		T3	28714
all_pins[6]	values[0x1]	102362	1			T9	3		T13	4		T36	4
all_pins[6]	transitions[0x0=>0x1]	102300	1			T9	3		T13	4		T36	1
all_pins[6]	transitions[0x1=>0x0]	167	1			T9	2		T60	4		T74	2
all_pins[7]	values[0x0]	2766511	1			T1	1		T2	1035		T3	28714
all_pins[7]	values[0x1]	229	1			T9	2		T36	3		T60	4
all_pins[7]	transitions[0x0=>0x1]	170	1			T9	1		T36	2		T60	2
all_pins[7]	transitions[0x1=>0x0]	417	1			T9	6		T13	2		T60	4