Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	3	125	97.66

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	3	125	97.66	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2599	1			T3	23		T12	4		T13	20
values[1]	2515	1			T3	60		T13	72		T22	92
values[2]	2508	1			T13	20		T93	12		T160	16
values[3]	3077	1			T3	71		T13	24		T21	59
values[4]	2739	1			T22	20		T23	42		T161	6
values[5]	2565	1			T3	45		T13	40		T24	4
values[6]	2315	1			T1	6		T3	20		T13	20
values[7]	2696	1			T3	20		T6	8		T13	103

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2870	1			T3	20		T13	20		T22	22
values[1]	2489	1			T3	20		T21	59		T22	21
values[2]	2339	1			T3	20		T13	64		T22	26
values[3]	3112	1			T3	47		T13	40		T22	110
values[4]	2051	1			T3	40		T12	4		T13	43
values[5]	3264	1			T3	49		T13	20		T22	21
values[6]	2317	1			T1	6		T3	43		T6	8
values[7]	2572	1			T13	92		T24	4		T22	40

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20632

1

T1

2

T3

236

T6

8

auto[1]

382

1

T1

4

T3

3

T13

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	3	125	97.66	3

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1]]	[values[2]]	0	1	1
[auto[1]]	[values[2]]	[values[4]]	0	1	1
[auto[1]]	[values[7]]	[values[4]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	326	1			T32	26		T29	45		T30	40
auto[0]	values[0]	values[1]	509	1			T32	85		T76	33		T162	2
auto[0]	values[0]	values[2]	225	1			T39	20		T163	21		T164	20
auto[0]	values[0]	values[3]	284	1			T87	14		T165	20		T31	20
auto[0]	values[0]	values[4]	312	1			T12	4		T23	20		T82	41
auto[0]	values[0]	values[5]	324	1			T166	6		T31	47		T163	25
auto[0]	values[0]	values[6]	358	1			T3	23		T167	6		T26	48
auto[0]	values[0]	values[7]	225	1			T13	18		T22	20		T168	25
auto[0]	values[1]	values[0]	289	1			T39	20		T163	20		T169	20
auto[0]	values[1]	values[1]	197	1			T3	20		T170	18		T171	6
auto[0]	values[1]	values[2]	280	1			T3	20		T22	26		T70	4
auto[0]	values[1]	values[3]	331	1			T3	20		T172	2		T74	22
auto[0]	values[1]	values[4]	307	1			T13	20		T22	46		T26	49
auto[0]	values[1]	values[5]	337	1			T26	20		T173	2		T82	21
auto[0]	values[1]	values[6]	497	1			T74	20		T31	29		T174	4
auto[0]	values[1]	values[7]	243	1			T13	51		T22	20		T175	24
auto[0]	values[2]	values[0]	369	1			T23	23		T176	24		T76	63
auto[0]	values[2]	values[1]	240	1			T26	39		T177	6		T82	22
auto[0]	values[2]	values[2]	236	1			T13	20		T52	22		T178	10
auto[0]	values[2]	values[3]	178	1			T30	55		T179	19		T164	22
auto[0]	values[2]	values[4]	408	1			T180	2		T164	20		T181	36
auto[0]	values[2]	values[5]	436	1			T182	6		T76	27		T183	8
auto[0]	values[2]	values[6]	195	1			T93	12		T49	20		T30	34
auto[0]	values[2]	values[7]	408	1			T160	16		T164	20		T184	20
auto[0]	values[3]	values[0]	468	1			T23	20		T30	23		T185	84
auto[0]	values[3]	values[1]	424	1			T21	59		T186	4		T39	45
auto[0]	values[3]	values[2]	319	1			T13	23		T32	32		T187	30
auto[0]	values[3]	values[3]	565	1			T3	24		T22	21		T23	23
auto[0]	values[3]	values[4]	166	1			T188	2		T189	20		T190	29
auto[0]	values[3]	values[5]	597	1			T3	24		T23	17		T76	20
auto[0]	values[3]	values[6]	215	1			T3	20		T185	43		T191	6
auto[0]	values[3]	values[7]	246	1			T165	38		T192	22		T193	38
auto[0]	values[4]	values[0]	460	1			T23	20		T76	20		T165	20
auto[0]	values[4]	values[1]	246	1			T30	20		T31	22		T194	12
auto[0]	values[4]	values[2]	306	1			T195	2		T26	48		T28	16
auto[0]	values[4]	values[3]	466	1			T22	20		T26	96		T31	23
auto[0]	values[4]	values[4]	159	1			T196	8		T197	21		T198	20
auto[0]	values[4]	values[5]	298	1			T23	22		T161	6		T74	22
auto[0]	values[4]	values[6]	335	1			T27	18		T76	20		T199	22
auto[0]	values[4]	values[7]	400	1			T46	2		T76	38		T31	22
auto[0]	values[5]	values[0]	262	1			T3	20		T22	21		T32	27
auto[0]	values[5]	values[1]	249	1			T200	2		T74	20		T201	18
auto[0]	values[5]	values[2]	171	1			T32	20		T30	22		T202	6
auto[0]	values[5]	values[3]	590	1			T13	39		T22	19		T23	43
auto[0]	values[5]	values[4]	163	1			T203	12		T45	20		T204	6
auto[0]	values[5]	values[5]	345	1			T3	25		T22	21		T23	20
auto[0]	values[5]	values[6]	330	1			T32	20		T76	20		T29	20
auto[0]	values[5]	values[7]	428	1			T24	4		T205	12		T206	14
auto[0]	values[6]	values[0]	336	1			T207	6		T208	6		T30	62
auto[0]	values[6]	values[1]	292	1			T22	20		T23	73		T209	18
auto[0]	values[6]	values[2]	261	1			T13	20		T210	49		T82	20
auto[0]	values[6]	values[3]	305	1			T22	26		T26	25		T76	20
auto[0]	values[6]	values[4]	258	1			T3	20		T211	16		T30	43
auto[0]	values[6]	values[5]	389	1			T66	12		T76	26		T164	22
auto[0]	values[6]	values[6]	146	1			T1	2		T22	20		T100	14
auto[0]	values[6]	values[7]	280	1			T212	16		T213	8		T214	29
auto[0]	values[7]	values[0]	314	1			T13	20		T23	20		T165	20
auto[0]	values[7]	values[1]	301	1			T215	20		T76	20		T216	10
auto[0]	values[7]	values[2]	500	1			T32	21		T39	25		T164	28
auto[0]	values[7]	values[3]	324	1			T22	20		T23	47		T32	20
auto[0]	values[7]	values[4]	251	1			T3	20		T13	23		T217	32
auto[0]	values[7]	values[5]	469	1			T13	20		T218	12		T29	39
auto[0]	values[7]	values[6]	190	1			T6	8		T13	20		T32	20
auto[0]	values[7]	values[7]	294	1			T13	20		T219	12		T220	10
auto[1]	values[0]	values[0]	3	1			T221	2		T222	1		-	-
auto[1]	values[0]	values[1]	1	1			T223	1		-	-		-	-
auto[1]	values[0]	values[2]	2	1			T224	2		-	-		-	-
auto[1]	values[0]	values[3]	5	1			T39	1		T225	3		T226	1
auto[1]	values[0]	values[4]	1	1			T227	1		-	-		-	-
auto[1]	values[0]	values[5]	8	1			T31	2		T228	1		T198	1
auto[1]	values[0]	values[6]	8	1			T26	2		T229	1		T230	1
auto[1]	values[0]	values[7]	8	1			T13	2		T231	2		T232	4
auto[1]	values[1]	values[0]	7	1			T233	2		T234	1		T235	2
auto[1]	values[1]	values[1]	2	1			T168	2		-	-		-	-
auto[1]	values[1]	values[3]	10	1			T76	1		T236	3		T237	1
auto[1]	values[1]	values[4]	5	1			T26	2		T39	1		T154	1
auto[1]	values[1]	values[5]	2	1			T214	1		T238	1		-	-
auto[1]	values[1]	values[6]	7	1			T31	2		T224	2		T239	1
auto[1]	values[1]	values[7]	1	1			T13	1		-	-		-	-
auto[1]	values[2]	values[0]	6	1			T31	3		T155	1		T239	2
auto[1]	values[2]	values[1]	2	1			T82	1		T238	1		-	-
auto[1]	values[2]	values[2]	2	1			T226	2		-	-		-	-
auto[1]	values[2]	values[3]	5	1			T30	1		T179	1		T164	3
auto[1]	values[2]	values[5]	11	1			T240	1		T189	1		T221	1
auto[1]	values[2]	values[6]	4	1			T163	1		T240	1		T241	2
auto[1]	values[2]	values[7]	8	1			T155	2		T44	1		T45	2
auto[1]	values[3]	values[0]	8	1			T30	1		T185	1		T193	2
auto[1]	values[3]	values[1]	10	1			T242	8		T222	1		T243	1
auto[1]	values[3]	values[2]	5	1			T13	1		T239	2		T214	1
auto[1]	values[3]	values[3]	22	1			T3	3		T22	1		T185	2
auto[1]	values[3]	values[4]	5	1			T190	1		T244	2		T245	1
auto[1]	values[3]	values[5]	12	1			T23	3		T82	1		T164	1
auto[1]	values[3]	values[6]	4	1			T19	4		-	-		-	-
auto[1]	values[3]	values[7]	11	1			T165	2		T193	2		T246	4
auto[1]	values[4]	values[0]	9	1			T236	1		T224	1		T228	1
auto[1]	values[4]	values[1]	2	1			T190	2		-	-		-	-
auto[1]	values[4]	values[2]	9	1			T26	3		T28	4		T82	1
auto[1]	values[4]	values[3]	6	1			T31	2		T154	1		T235	3
auto[1]	values[4]	values[4]	8	1			T197	1		T198	1		T221	1
auto[1]	values[4]	values[5]	14	1			T247	8		T45	1		T244	1
auto[1]	values[4]	values[6]	12	1			T27	2		T185	1		T82	2
auto[1]	values[4]	values[7]	9	1			T31	2		T248	4		T230	1
auto[1]	values[5]	values[0]	4	1			T22	1		T39	2		T181	1
auto[1]	values[5]	values[1]	2	1			T214	2		-	-		-	-
auto[1]	values[5]	values[2]	2	1			T189	1		T233	1		-	-
auto[1]	values[5]	values[3]	5	1			T13	1		T22	1		T224	1
auto[1]	values[5]	values[4]	2	1			T45	1		T226	1		-	-
auto[1]	values[5]	values[5]	6	1			T25	6		-	-		-	-
auto[1]	values[5]	values[6]	2	1			T45	1		T245	1		-	-
auto[1]	values[5]	values[7]	4	1			T30	1		T39	1		T193	1
auto[1]	values[6]	values[0]	7	1			T30	1		T233	1		T249	3
auto[1]	values[6]	values[1]	6	1			T22	1		T164	2		T223	1
auto[1]	values[6]	values[2]	2	1			T237	1		T250	1		-	-
auto[1]	values[6]	values[3]	9	1			T22	2		T26	4		T155	1
auto[1]	values[6]	values[4]	6	1			T228	4		T45	1		T251	1
auto[1]	values[6]	values[5]	7	1			T164	1		T18	1		T229	1
auto[1]	values[6]	values[6]	5	1			T1	4		T198	1		-	-
auto[1]	values[6]	values[7]	6	1			T252	2		T250	1		T253	2
auto[1]	values[7]	values[0]	2	1			T185	1		T250	1		-	-
auto[1]	values[7]	values[1]	6	1			T163	3		T189	1		T225	2
auto[1]	values[7]	values[2]	19	1			T32	1		T164	1		T239	4
auto[1]	values[7]	values[3]	7	1			T23	1		T223	2		T235	4
auto[1]	values[7]	values[5]	9	1			T29	1		T187	1		T169	1
auto[1]	values[7]	values[6]	9	1			T30	1		T82	1		T18	1
auto[1]	values[7]	values[7]	1	1			T254	1		-	-		-	-