Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1799

1

T2

7

T3

9

T4

10

auto[1]

1785

1

T2

3

T3

8

T4

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1952

1

T2

10

T3

17

T4

19

auto[1]

1632

1

T9

6

T17

1

T16

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2852

1

T2

4

T3

10

T4

13

auto[1]

732

1

T2

6

T3

7

T4

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	695	1			T2	1		T3	2		T4	5
valid[1]	734	1			T2	1		T3	4		T4	1
valid[2]	674	1			T2	2		T3	4		T4	5
valid[3]	727	1			T2	2		T3	2		T4	3
valid[4]	754	1			T2	4		T3	5		T4	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	115	1			T2	1		T4	1		T9	4
auto[0]	auto[0]	valid[0]	auto[1]	169	1			T9	1		T16	1		T83	3
auto[0]	auto[0]	valid[1]	auto[0]	123	1			T2	1		T3	3		T9	2
auto[0]	auto[0]	valid[1]	auto[1]	168	1			T83	2		T326	2		T32	2
auto[0]	auto[0]	valid[2]	auto[0]	138	1			T2	1		T3	1		T4	3
auto[0]	auto[0]	valid[2]	auto[1]	137	1			T83	3		T84	2		T85	1
auto[0]	auto[0]	valid[3]	auto[0]	133	1			T4	1		T9	2		T13	3
auto[0]	auto[0]	valid[3]	auto[1]	158	1			T83	5		T326	5		T327	2
auto[0]	auto[0]	valid[4]	auto[0]	127	1			T3	2		T4	2		T9	3
auto[0]	auto[0]	valid[4]	auto[1]	175	1			T36	1		T83	3		T85	1
auto[0]	auto[1]	valid[0]	auto[0]	107	1			T3	1		T4	1		T9	1
auto[0]	auto[1]	valid[0]	auto[1]	159	1			T9	1		T72	1		T83	5
auto[0]	auto[1]	valid[1]	auto[0]	117	1			T4	1		T13	1		T16	1
auto[0]	auto[1]	valid[1]	auto[1]	191	1			T9	1		T22	1		T36	1
auto[0]	auto[1]	valid[2]	auto[0]	115	1			T2	1		T3	2		T4	1
auto[0]	auto[1]	valid[2]	auto[1]	143	1			T22	2		T23	1		T83	3
auto[0]	auto[1]	valid[3]	auto[0]	114	1			T4	2		T9	2		T13	1
auto[0]	auto[1]	valid[3]	auto[1]	167	1			T9	1		T36	1		T23	1
auto[0]	auto[1]	valid[4]	auto[0]	131	1			T3	1		T4	1		T9	3
auto[0]	auto[1]	valid[4]	auto[1]	165	1			T9	2		T17	1		T72	1
auto[1]	auto[0]	valid[0]	auto[0]	70	1			T3	1		T4	2		T9	1
auto[1]	auto[0]	valid[1]	auto[0]	54	1			T9	1		T16	1		T22	1
auto[1]	auto[0]	valid[2]	auto[0]	68	1			T20	1		T22	1		T36	1
auto[1]	auto[0]	valid[3]	auto[0]	96	1			T2	2		T3	1		T9	3
auto[1]	auto[0]	valid[4]	auto[0]	68	1			T2	2		T3	1		T4	1
auto[1]	auto[1]	valid[0]	auto[0]	75	1			T4	1		T9	2		T13	1
auto[1]	auto[1]	valid[1]	auto[0]	81	1			T3	1		T13	2		T84	1
auto[1]	auto[1]	valid[2]	auto[0]	73	1			T3	1		T4	1		T9	1
auto[1]	auto[1]	valid[3]	auto[0]	59	1			T3	1		T9	2		T13	1
auto[1]	auto[1]	valid[4]	auto[0]	88	1			T2	2		T3	1		T4	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal