Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49109

1

T2

324

T3

318

T4

344

auto[1]

16806

1

T9

46

T17

1

T16

43

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48021

1

T2

203

T3

208

T4

238

auto[1]

17894

1

T2

121

T3

110

T4

106

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33808	1			T2	164		T3	164		T4	167
others[1]	5589	1			T2	25		T3	25		T4	31
others[2]	5659	1			T2	25		T3	26		T4	37
others[3]	6390	1			T2	30		T3	42		T4	27
interest[1]	3602	1			T2	19		T3	11		T4	12
interest[4]	22254	1			T2	91		T3	104		T4	108
interest[64]	10867	1			T2	61		T3	50		T4	70

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15864	1			T2	98		T3	110		T4	109
auto[0]	auto[0]	others[1]	2773	1			T2	18		T3	16		T4	22
auto[0]	auto[0]	others[2]	2669	1			T2	16		T3	18		T4	27
auto[0]	auto[0]	others[3]	2990	1			T2	21		T3	24		T4	23
auto[0]	auto[0]	interest[1]	1699	1			T2	10		T3	5		T4	10
auto[0]	auto[0]	interest[4]	10340	1			T2	53		T3	71		T4	64
auto[0]	auto[0]	interest[64]	5220	1			T2	40		T3	35		T4	47
auto[0]	auto[1]	others[0]	8718	1			T9	32		T17	1		T16	20
auto[0]	auto[1]	others[1]	1339	1			T9	2		T16	3		T22	6
auto[0]	auto[1]	others[2]	1463	1			T9	2		T16	11		T22	9
auto[0]	auto[1]	others[3]	1682	1			T9	3		T16	5		T22	8
auto[0]	auto[1]	interest[1]	939	1			T9	5		T16	1		T22	4
auto[0]	auto[1]	interest[4]	5799	1			T9	18		T17	1		T16	14
auto[0]	auto[1]	interest[64]	2665	1			T9	2		T16	3		T22	10
auto[1]	auto[0]	others[0]	9226	1			T2	66		T3	54		T4	58
auto[1]	auto[0]	others[1]	1477	1			T2	7		T3	9		T4	9
auto[1]	auto[0]	others[2]	1527	1			T2	9		T3	8		T4	10
auto[1]	auto[0]	others[3]	1718	1			T2	9		T3	18		T4	4
auto[1]	auto[0]	interest[1]	964	1			T2	9		T3	6		T4	2
auto[1]	auto[0]	interest[4]	6115	1			T2	38		T3	33		T4	44
auto[1]	auto[0]	interest[64]	2982	1			T2	21		T3	15		T4	23

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal