Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	888	1			T9	10		T13	11		T36	7
all_values[1]	888	1			T9	10		T13	11		T36	7
all_values[2]	888	1			T9	10		T13	11		T36	7
all_values[3]	888	1			T9	10		T13	11		T36	7
all_values[4]	888	1			T9	10		T13	11		T36	7
all_values[5]	888	1			T9	10		T13	11		T36	7
all_values[6]	888	1			T9	10		T13	11		T36	7
all_values[7]	888	1			T9	10		T13	11		T36	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3833

1

T9

36

T13

49

T36

21

auto[1]

3271

1

T9

44

T13

39

T36

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2814

1

T9

40

T13

41

T36

26

auto[1]

4290

1

T9

40

T13

47

T36

30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4070

1

T9

49

T13

56

T36

35

auto[1]

3034

1

T9

31

T13

32

T36

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	180	1			T13	3		T36	1		T60	4
all_values[0]	auto[0]	auto[0]	auto[1]	89	1			T9	1		T13	2		T36	1
all_values[0]	auto[0]	auto[1]	auto[0]	163	1			T13	1		T36	3		T60	1
all_values[0]	auto[0]	auto[1]	auto[1]	94	1			T9	2		T60	3		T157	3
all_values[0]	auto[1]	auto[0]	auto[1]	179	1			T9	1		T13	2		T36	1
all_values[0]	auto[1]	auto[1]	auto[1]	183	1			T9	6		T13	3		T36	1
all_values[1]	auto[0]	auto[0]	auto[0]	170	1			T9	2		T13	2		T60	3
all_values[1]	auto[0]	auto[0]	auto[1]	76	1			T9	1		T13	1		T60	1
all_values[1]	auto[0]	auto[1]	auto[0]	134	1			T9	5		T13	3		T36	5
all_values[1]	auto[0]	auto[1]	auto[1]	98	1			T13	1		T60	1		T158	1
all_values[1]	auto[1]	auto[0]	auto[1]	230	1			T9	1		T13	1		T60	3
all_values[1]	auto[1]	auto[1]	auto[1]	180	1			T9	1		T13	3		T36	2
all_values[2]	auto[0]	auto[0]	auto[0]	186	1			T9	4		T13	2		T36	1
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T13	2		T36	2		T74	1
all_values[2]	auto[0]	auto[1]	auto[0]	163	1			T9	3		T13	1		T36	1
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T60	1		T74	1		T158	2
all_values[2]	auto[1]	auto[0]	auto[1]	212	1			T9	2		T13	3		T36	1
all_values[2]	auto[1]	auto[1]	auto[1]	161	1			T9	1		T13	3		T36	2
all_values[3]	auto[0]	auto[0]	auto[0]	182	1			T9	2		T13	2		T36	1
all_values[3]	auto[0]	auto[0]	auto[1]	96	1			T9	2		T13	1		T60	3
all_values[3]	auto[0]	auto[1]	auto[0]	146	1			T9	3		T13	2		T36	2
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T13	1		T36	1		T60	1
all_values[3]	auto[1]	auto[0]	auto[1]	231	1			T9	1		T13	4		T36	2
all_values[3]	auto[1]	auto[1]	auto[1]	147	1			T9	2		T13	1		T36	1
all_values[4]	auto[0]	auto[0]	auto[0]	176	1			T9	2		T13	1		T36	1
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T74	3		T158	1		T159	1
all_values[4]	auto[0]	auto[1]	auto[0]	151	1			T9	2		T13	2		T36	6
all_values[4]	auto[0]	auto[1]	auto[1]	91	1			T9	2		T13	3		T60	1
all_values[4]	auto[1]	auto[0]	auto[1]	203	1			T9	2		T13	3		T60	2
all_values[4]	auto[1]	auto[1]	auto[1]	186	1			T9	2		T13	2		T60	4
all_values[5]	auto[0]	auto[0]	auto[0]	297	1			T9	3		T13	7		T36	2
all_values[5]	auto[0]	auto[1]	auto[0]	229	1			T9	4		T13	1		T36	2
all_values[5]	auto[1]	auto[0]	auto[1]	193	1			T9	1		T36	2		T60	2
all_values[5]	auto[1]	auto[1]	auto[1]	169	1			T9	2		T13	3		T36	1
all_values[6]	auto[0]	auto[0]	auto[0]	185	1			T9	3		T13	4		T36	1
all_values[6]	auto[0]	auto[0]	auto[1]	96	1			T9	1		T13	1		T36	1
all_values[6]	auto[0]	auto[1]	auto[0]	154	1			T9	1		T60	5		T74	4
all_values[6]	auto[0]	auto[1]	auto[1]	92	1			T13	3		T36	1		T159	1
all_values[6]	auto[1]	auto[0]	auto[1]	215	1			T9	2		T13	2		T36	1
all_values[6]	auto[1]	auto[1]	auto[1]	146	1			T9	3		T13	1		T36	3
all_values[7]	auto[0]	auto[0]	auto[0]	168	1			T9	3		T13	6		T60	3
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T36	1		T74	3		T157	2
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T9	3		T13	4		T60	3
all_values[7]	auto[0]	auto[1]	auto[1]	102	1			T36	2		T60	3		T158	4
all_values[7]	auto[1]	auto[0]	auto[1]	216	1			T9	2		T36	2		T60	2
all_values[7]	auto[1]	auto[1]	auto[1]	183	1			T9	2		T13	1		T36	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal