Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2697396	1			T1	5		T3	1		T4	1
all_values[1]	2697396	1			T1	5		T3	1		T4	1
all_values[2]	2697396	1			T1	5		T3	1		T4	1
all_values[3]	2697396	1			T1	5		T3	1		T4	1
all_values[4]	2697396	1			T1	5		T3	1		T4	1
all_values[5]	2697396	1			T1	5		T3	1		T4	1
all_values[6]	2697396	1			T1	5		T3	1		T4	1
all_values[7]	2697396	1			T1	5		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20468218

1

T1

40

T3

8

T4

8

auto[1]

1110950

1

T20

47

T38

18142

T64

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555986

1

T1

40

T3

8

T4

8

auto[1]

23182

1

T5

37

T8

76

T16

273

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2589287	1			T1	5		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	11405	1			T5	37		T8	47		T16	117
all_values[0]	auto[1]	auto[0]	96078	1			T20	6		T38	3474		T64	1
all_values[0]	auto[1]	auto[1]	626	1			T20	1		T38	150		T63	2
all_values[1]	auto[0]	auto[0]	2508993	1			T1	5		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	5628	1			T8	16		T16	102		T20	2
all_values[1]	auto[1]	auto[0]	182286	1			T20	1		T38	3596		T64	1
all_values[1]	auto[1]	auto[1]	489	1			T20	3		T38	29		T63	1
all_values[2]	auto[0]	auto[0]	2568901	1			T1	5		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	2662	1			T8	13		T16	54		T20	1
all_values[2]	auto[1]	auto[0]	125540	1			T20	6		T38	3610		T64	1
all_values[2]	auto[1]	auto[1]	293	1			T20	2		T38	13		T34	34
all_values[3]	auto[0]	auto[0]	2552766	1			T1	5		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	187	1			T20	2		T38	3		T63	1
all_values[3]	auto[1]	auto[0]	144233	1			T20	1		T38	3		T64	2
all_values[3]	auto[1]	auto[1]	210	1			T20	3		T38	6		T64	2
all_values[4]	auto[0]	auto[0]	2630850	1			T1	5		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	188	1			T20	4		T38	7		T63	2
all_values[4]	auto[1]	auto[0]	66158	1			T20	2		T38	3619		T64	2
all_values[4]	auto[1]	auto[1]	200	1			T20	1		T38	2		T64	3
all_values[5]	auto[0]	auto[0]	2521453	1			T1	5		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	288	1			T19	9		T20	4		T38	4
all_values[5]	auto[1]	auto[0]	175483	1			T20	1		T38	4		T64	5
all_values[5]	auto[1]	auto[1]	172	1			T20	1		T38	2		T64	1
all_values[6]	auto[0]	auto[0]	2527648	1			T1	5		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	217	1			T38	7		T64	2		T63	2
all_values[6]	auto[1]	auto[0]	169337	1			T20	7		T38	4		T64	1
all_values[6]	auto[1]	auto[1]	194	1			T20	5		T38	3		T63	1
all_values[7]	auto[0]	auto[0]	2547547	1			T1	5		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	198	1			T20	4		T38	4		T64	3
all_values[7]	auto[1]	auto[0]	149426	1			T20	5		T38	3619		T63	1326
all_values[7]	auto[1]	auto[1]	225	1			T20	2		T38	8		T64	1