Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31264	1			T5	34		T8	70		T9	222
auto[SpiFlashAddrCfg]	6438	1			T1	2		T4	6		T5	5
auto[SpiFlashAddr3b]	7810	1			T1	3		T4	2		T5	17
auto[SpiFlashAddr4b]	6386	1			T3	4		T4	4		T5	12

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28793

1

T1

5

T4

12

T5

44

auto[1]

23105

1

T3

4

T5

24

T8

78

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27906

1

T3

2

T4

10

T5

31

auto[1]

23992

1

T1

5

T3

2

T4

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35323	1			T1	2		T4	2		T5	41
values[1]	911	1			T5	5		T8	4		T9	2
values[2]	1263	1			T5	4		T8	14		T9	8
values[3]	1295	1			T4	2		T5	3		T8	3
values[4]	1231	1			T5	1		T8	8		T9	12
values[5]	1161	1			T8	6		T9	12		T11	6
values[6]	1177	1			T1	3		T3	2		T8	1
values[7]	1233	1			T4	6		T8	12		T9	9
values[8]	8304	1			T3	2		T4	2		T5	14

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26278

1

T3

4

T4

12

T8

194

auto[1]

25620

1

T1

5

T5

68

T16

139

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

49986

1

T1

5

T3

4

T4

12

write

1912

1

T5

2

T8

7

T9

11

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16805

1

T1

3

T3

4

T4

8

valids[0x1]

35093

1

T1

2

T4

4

T5

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1338	1			T5	2		T8	6		T9	9
internal_process_ops[0x5a]	1357	1			T4	2		T5	3		T8	7
internal_process_ops[0x05]	19415	1			T5	10		T8	25		T9	155
internal_process_ops[0x35]	1357	1			T5	1		T8	2		T9	12
internal_process_ops[0x15]	1326	1			T5	3		T8	4		T9	5
internal_process_ops[0x03]	853	1			T5	2		T8	4		T9	4
internal_process_ops[0x0b]	961	1			T1	2		T4	2		T8	11
internal_process_ops[0x3b]	904	1			T1	3		T3	2		T4	2
internal_process_ops[0x6b]	872	1			T4	2		T5	2		T8	4
internal_process_ops[0xbb]	877	1			T4	4		T8	6		T9	4
internal_process_ops[0xeb]	918	1			T3	2		T5	1		T8	11

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50982

1

T1

5

T3

4

T4

12

auto[1]

916

1

T8

2

T9

4

T11

16

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50072

1

T1

5

T3

4

T4

12

auto[1]

1826

1

T5

3

T8

6

T9

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8674

1

T8

48

T9

163

T11

146

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5662

1

T8

22

T9

56

T11

24

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1857

1

T4

6

T8

26

T9

18

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1642

1

T8

21

T9

21

T11

21

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2269

1

T4

2

T8

20

T9

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1891

1

T8

23

T9

24

T11

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1778

1

T4

4

T8

16

T9

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1563

1

T3

4

T8

11

T9

13

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

87

1

T9

2

T14

4

T29

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

45

1

T11

4

T29

1

T32

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

60

1

T9

1

T11

4

T32

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

69

1

T11

1

T35

2

T36

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

62

1

T8

2

T32

1

T27

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

65

1

T8

1

T11

3

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

44

1

T9

1

T33

1

T24

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

55

1

T12

2

T27

1

T34

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

55

1

T9

1

T29

2

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

53

1

T9

1

T11

4

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

50

1

T9

1

T11

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

55

1

T9

1

T11

2

T29

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

74

1

T8

3

T34

4

T36

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

58

1

T9

1

T32

3

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

55

1

T9

1

T26

2

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

55

1

T8

1

T9

1

T11

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9071

1

T5

22

T16

57

T28

157

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7364

1

T5

12

T16

18

T28

308

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1267

1

T1

2

T5

4

T16

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1197

1

T5

1

T16

12

T28

23

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1629

1

T1

3

T5

7

T16

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1560

1

T5

10

T16

15

T28

27

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1266

1

T5

9

T16

5

T28

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1296

1

T5

1

T16

6

T28

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

66

1

T16

2

T146

5

T23

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

50

1

T16

2

T28

3

T38

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

46

1

T28

1

T38

2

T71

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

70

1

T28

3

T38

2

T71

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

76

1

T38

6

T71

3

T39

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

47

1

T28

1

T71

2

T39

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

64

1

T28

5

T43

1

T71

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

62

1

T16

4

T28

1

T38

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

82

1

T39

2

T146

2

T23

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

51

1

T28

2

T38

2

T23

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

53

1

T39

1

T146

1

T161

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

62

1

T71

1

T146

1

T52

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

60

1

T5

2

T28

3

T43

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

51

1

T38

2

T71

1

T39

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

62

1

T38

3

T71

1

T154

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

68

1

T28

1

T22

2

T38

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3581	1			T8	35		T9	36		T11	36
auto[0]	values[0]	valids[0x1]	13220	1			T4	2		T8	64		T9	204
auto[0]	values[1]	valids[0x1]	480	1			T8	4		T9	2		T11	4
auto[0]	values[2]	valids[0x0]	483	1			T8	13		T9	6		T11	3
auto[0]	values[2]	valids[0x1]	295	1			T8	1		T9	2		T11	5
auto[0]	values[3]	valids[0x0]	470	1			T4	2		T8	2		T9	7
auto[0]	values[3]	valids[0x1]	268	1			T8	1		T9	3		T11	2
auto[0]	values[4]	valids[0x0]	439	1			T8	6		T9	2		T11	8
auto[0]	values[4]	valids[0x1]	223	1			T8	2		T9	10		T11	5
auto[0]	values[5]	valids[0x0]	413	1			T8	2		T9	6		T11	5
auto[0]	values[5]	valids[0x1]	242	1			T8	4		T9	6		T11	1
auto[0]	values[6]	valids[0x0]	402	1			T3	2		T8	1		T9	10
auto[0]	values[6]	valids[0x1]	280	1			T9	7		T11	4		T26	3
auto[0]	values[7]	valids[0x0]	460	1			T4	6		T8	5		T9	5
auto[0]	values[7]	valids[0x1]	265	1			T8	7		T9	4		T11	2
auto[0]	values[8]	valids[0x0]	3046	1			T3	2		T8	32		T9	23
auto[0]	values[8]	valids[0x1]	1711	1			T4	2		T8	15		T9	15
auto[1]	values[0]	valids[0x0]	3465	1			T5	20		T16	14		T28	65
auto[1]	values[0]	valids[0x1]	15057	1			T1	2		T5	21		T16	74
auto[1]	values[1]	valids[0x1]	431	1			T5	5		T16	7		T28	3
auto[1]	values[2]	valids[0x0]	290	1			T5	2		T16	2		T28	8
auto[1]	values[2]	valids[0x1]	195	1			T5	2		T16	3		T28	2
auto[1]	values[3]	valids[0x0]	348	1			T5	1		T16	3		T28	4
auto[1]	values[3]	valids[0x1]	209	1			T5	2		T16	2		T28	1
auto[1]	values[4]	valids[0x0]	346	1			T5	1		T16	2		T28	10
auto[1]	values[4]	valids[0x1]	223	1			T16	2		T28	5		T22	1
auto[1]	values[5]	valids[0x0]	339	1			T28	6		T22	5		T43	6
auto[1]	values[5]	valids[0x1]	167	1			T16	1		T28	1		T22	2
auto[1]	values[6]	valids[0x0]	320	1			T1	3		T16	2		T28	6
auto[1]	values[6]	valids[0x1]	175	1			T16	5		T28	9		T38	3
auto[1]	values[7]	valids[0x0]	268	1			T28	1		T22	1		T43	3
auto[1]	values[7]	valids[0x1]	240	1			T28	3		T22	2		T43	1
auto[1]	values[8]	valids[0x0]	2135	1			T5	9		T16	12		T28	44
auto[1]	values[8]	valids[0x1]	1412	1			T5	5		T16	10		T28	26