Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2922980

1

T1

3224

T3

1

T4

1537

auto[1]

17970

1

T5

8

T8

14

T9

148

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

820513

1

T1

3224

T3

1

T4

1537

auto[1]

2120437

1

T5

2642

T8

15279

T9

27653

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	543373	1			T1	1074		T3	1		T4	363
auto[524288:1048575]	300105	1			T5	4		T8	8		T9	3198
auto[1048576:1572863]	379897	1			T1	1095		T5	1185		T8	3024
auto[1572864:2097151]	335129	1			T1	2		T4	679		T5	204
auto[2097152:2621439]	329312	1			T1	287		T4	1		T8	3750
auto[2621440:3145727]	384338	1			T5	265		T8	5328		T9	263
auto[3145728:3670015]	355840	1			T1	541		T4	492		T8	2951
auto[3670016:4194303]	312956	1			T1	225		T4	2		T5	997

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2139669

1

T1

18

T3

1

T4

14

auto[1]

801281

1

T1

3206

T4

1523

T9

10

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2550002

1

T1

3224

T3

1

T4

1537

auto[1]

390948

1

T5

2201

T8

1341

T9

283

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	179661	1			T1	1074		T3	1		T4	363
auto[0]	auto[0]	auto[0:524287]	auto[1]	304260	1			T9	7086		T11	2891		T31	5528
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	66185	1			T8	2		T9	7		T11	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	194144	1			T9	3182		T11	9635		T37	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	101734	1			T1	1095		T8	4		T9	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	228342	1			T8	2497		T9	4327		T11	3356
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	78314	1			T1	2		T4	679		T5	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	201634	1			T5	193		T9	4		T11	3639
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	80021	1			T1	287		T4	1		T8	12
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	194711	1			T8	3738		T9	5		T11	261
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	100740	1			T5	2		T8	16		T9	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	244006	1			T5	256		T8	4769		T9	259
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	120921	1			T1	541		T4	492		T8	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	180111	1			T8	2945		T9	8381		T11	3635
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	86842	1			T1	225		T4	2		T8	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	173742	1			T8	1		T9	4013		T11	257
auto[0]	auto[1]	auto[0:524287]	auto[0]	2147	1			T5	1		T11	2		T28	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	54010	1			T16	256		T28	1		T22	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	338	1			T5	1		T8	1		T11	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	37707	1			T5	1		T8	5		T11	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	237	1			T8	4		T11	2		T16	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	47562	1			T5	1185		T8	513		T16	128
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	247	1			T5	2		T8	1		T29	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	52655	1			T5	5		T29	2131		T22	513
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	187	1			T9	1		T11	2		T28	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	52347	1			T9	1		T11	4		T32	7
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	307	1			T5	1		T8	1		T9	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	36974	1			T5	1		T8	541		T28	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	457	1			T8	1		T11	4		T29	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	52043	1			T11	2188		T29	2246		T43	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	344	1			T5	1		T8	5		T9	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	50050	1			T5	996		T8	262		T9	257
auto[1]	auto[0]	auto[0:524287]	auto[0]	277	1			T9	1		T11	1		T31	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2548	1			T9	18		T11	10		T31	44
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	144	1			T9	1		T11	3		T28	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1144	1			T9	8		T11	5		T28	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	197	1			T8	1		T11	1		T16	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1454	1			T11	2		T16	7		T28	13
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	176	1			T5	1		T9	4		T11	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1400	1			T9	65		T11	9		T16	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	172	1			T9	1		T16	3		T43	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1675	1			T9	13		T16	17		T43	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	202	1			T8	1		T11	1		T28	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1797	1			T11	18		T28	120		T22	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	170	1			T8	1		T11	2		T16	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1869	1			T11	24		T16	2		T43	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	154	1			T8	1		T9	1		T11	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1255	1			T8	3		T9	18		T11	7
auto[1]	auto[1]	auto[0:524287]	auto[0]	41	1			T28	1		T33	1		T214	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	429	1			T28	25		T33	16		T214	31
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	53	1			T5	1		T11	1		T38	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	390	1			T5	1		T11	2		T38	11
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	47	1			T8	1		T27	2		T34	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	324	1			T8	4		T27	19		T176	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	50	1			T22	1		T38	3		T39	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	653	1			T22	2		T38	49		T39	88
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	25	1			T9	1		T38	2		T35	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	174	1			T9	6		T38	18		T35	8
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	42	1			T5	1		T28	1		T39	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	270	1			T5	4		T28	20		T39	10
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	40	1			T29	3		T38	1		T71	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	229	1			T29	19		T38	2		T155	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	41	1			T8	1		T9	1		T16	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	528	1			T8	1		T9	10		T28	30

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1736904	1			T1	18		T3	1		T4	14
auto[0]	auto[0]	auto[1]	798464	1			T1	3206		T4	1523		T9	3
auto[0]	auto[1]	auto[0]	385134	1			T5	2194		T8	1334		T9	264
auto[0]	auto[1]	auto[1]	2478	1			T9	1		T28	2		T27	2
auto[1]	auto[0]	auto[0]	14353	1			T5	1		T8	7		T9	124
auto[1]	auto[0]	auto[1]	281	1			T9	6		T11	6		T28	4
auto[1]	auto[1]	auto[0]	3278	1			T5	7		T8	7		T9	18
auto[1]	auto[1]	auto[1]	58	1			T155	1		T72	6		T273	1