Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15077

1

T4

12

T8

116

T9

228

auto[1]

11201

1

T3

4

T8

78

T9

120

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2940	1			T8	25		T11	56		T106	16
values[1]	3466	1			T9	20		T29	20		T123	4
values[2]	3201	1			T9	20		T121	4		T32	20
values[3]	3653	1			T8	88		T9	20		T11	39
values[4]	3022	1			T4	12		T11	74		T162	2
values[5]	2978	1			T8	20		T9	150		T11	99
values[6]	3571	1			T8	41		T9	138		T11	20
values[7]	3447	1			T3	4		T8	20		T11	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3075	1			T4	12		T8	43		T9	167
values[1]	3349	1			T9	48		T11	79		T14	14
values[2]	3411	1			T8	20		T9	20		T11	51
values[3]	3066	1			T8	65		T32	28		T27	63
values[4]	3356	1			T9	20		T11	45		T162	2
values[5]	3277	1			T3	4		T8	21		T105	10
values[6]	3878	1			T8	45		T9	61		T11	93
values[7]	2866	1			T9	32		T11	20		T121	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	216	1			T33	16		T178	13		T126	16
auto[0]	values[0]	values[1]	175	1			T106	16		T164	14		T172	15
auto[0]	values[0]	values[2]	211	1			T11	22		T195	6		T51	10
auto[0]	values[0]	values[3]	219	1			T212	8		T264	6		T178	9
auto[0]	values[0]	values[4]	216	1			T11	14		T44	14		T182	13
auto[0]	values[0]	values[5]	220	1			T170	4		T36	22		T211	15
auto[0]	values[0]	values[6]	201	1			T8	18		T34	9		T177	8
auto[0]	values[0]	values[7]	171	1			T32	11		T33	19		T34	11
auto[0]	values[1]	values[0]	164	1			T51	8		T178	28		T165	14
auto[0]	values[1]	values[1]	153	1			T123	4		T210	10		T208	18
auto[0]	values[1]	values[2]	446	1			T180	49		T177	4		T192	12
auto[0]	values[1]	values[3]	182	1			T27	9		T24	9		T167	11
auto[0]	values[1]	values[4]	281	1			T9	16		T163	4		T44	17
auto[0]	values[1]	values[5]	294	1			T44	22		T177	12		T126	12
auto[0]	values[1]	values[6]	366	1			T29	10		T286	112		T178	13
auto[0]	values[1]	values[7]	216	1			T33	15		T34	13		T35	9
auto[0]	values[2]	values[0]	199	1			T35	13		T178	16		T183	17
auto[0]	values[2]	values[1]	260	1			T35	12		T287	16		T196	34
auto[0]	values[2]	values[2]	162	1			T32	6		T35	17		T200	14
auto[0]	values[2]	values[3]	210	1			T177	12		T288	6		T229	12
auto[0]	values[2]	values[4]	301	1			T33	14		T186	12		T51	29
auto[0]	values[2]	values[5]	152	1			T91	6		T191	11		T177	10
auto[0]	values[2]	values[6]	318	1			T9	11		T33	13		T289	18
auto[0]	values[2]	values[7]	89	1			T27	11		T172	14		T290	2
auto[0]	values[3]	values[0]	255	1			T8	17		T9	10		T291	4
auto[0]	values[3]	values[1]	391	1			T14	14		T31	64		T27	28
auto[0]	values[3]	values[2]	262	1			T27	16		T292	2		T191	47
auto[0]	values[3]	values[3]	205	1			T8	15		T32	11		T27	14
auto[0]	values[3]	values[4]	236	1			T32	16		T164	7		T293	89
auto[0]	values[3]	values[5]	195	1			T34	11		T214	9		T294	8
auto[0]	values[3]	values[6]	374	1			T8	11		T11	34		T27	64
auto[0]	values[3]	values[7]	256	1			T35	6		T24	25		T281	4
auto[0]	values[4]	values[0]	277	1			T4	12		T35	21		T188	14
auto[0]	values[4]	values[1]	193	1			T32	50		T51	10		T206	7
auto[0]	values[4]	values[2]	172	1			T178	10		T280	22		T196	29
auto[0]	values[4]	values[3]	294	1			T214	9		T35	70		T24	11
auto[0]	values[4]	values[4]	141	1			T162	2		T165	11		T192	14
auto[0]	values[4]	values[5]	326	1			T27	57		T194	4		T34	16
auto[0]	values[4]	values[6]	227	1			T11	47		T34	10		T178	12
auto[0]	values[4]	values[7]	142	1			T11	10		T180	11		T216	7
auto[0]	values[5]	values[0]	167	1			T9	45		T193	6		T167	22
auto[0]	values[5]	values[1]	317	1			T9	14		T11	53		T33	10
auto[0]	values[5]	values[2]	144	1			T9	6		T29	13		T34	16
auto[0]	values[5]	values[3]	98	1			T8	14		T203	10		T178	13
auto[0]	values[5]	values[4]	225	1			T11	13		T32	10		T36	19
auto[0]	values[5]	values[5]	84	1			T27	13		T165	11		T224	10
auto[0]	values[5]	values[6]	340	1			T34	15		T279	18		T36	13
auto[0]	values[5]	values[7]	200	1			T9	21		T80	14		T35	10
auto[0]	values[6]	values[0]	424	1			T8	17		T9	71		T11	15
auto[0]	values[6]	values[1]	364	1			T29	16		T33	12		T185	2
auto[0]	values[6]	values[2]	130	1			T29	38		T27	9		T191	11
auto[0]	values[6]	values[3]	183	1			T295	14		T187	16		T126	12
auto[0]	values[6]	values[4]	293	1			T32	10		T181	6		T50	34
auto[0]	values[6]	values[5]	373	1			T8	15		T82	20		T33	34
auto[0]	values[6]	values[6]	322	1			T9	34		T32	9		T33	43
auto[0]	values[6]	values[7]	111	1			T34	11		T49	14		T55	33
auto[0]	values[7]	values[0]	153	1			T37	4		T209	4		T182	12
auto[0]	values[7]	values[1]	207	1			T177	48		T284	10		T192	7
auto[0]	values[7]	values[2]	422	1			T8	9		T11	12		T29	37
auto[0]	values[7]	values[3]	312	1			T178	38		T172	75		T206	13
auto[0]	values[7]	values[4]	177	1			T29	11		T26	11		T32	8
auto[0]	values[7]	values[5]	210	1			T105	10		T217	11		T148	15
auto[0]	values[7]	values[6]	204	1			T32	8		T198	10		T164	10
auto[0]	values[7]	values[7]	249	1			T176	12		T226	13		T149	8
auto[1]	values[0]	values[0]	163	1			T33	4		T178	23		T126	4
auto[1]	values[0]	values[1]	152	1			T164	8		T172	18		T165	7
auto[1]	values[0]	values[2]	143	1			T11	9		T51	10		T176	10
auto[1]	values[0]	values[3]	231	1			T178	11		T182	9		T192	6
auto[1]	values[0]	values[4]	161	1			T11	11		T44	6		T182	9
auto[1]	values[0]	values[5]	114	1			T36	5		T211	6		T191	7
auto[1]	values[0]	values[6]	199	1			T8	7		T34	22		T177	18
auto[1]	values[0]	values[7]	148	1			T32	28		T33	21		T34	10
auto[1]	values[1]	values[0]	132	1			T51	12		T178	8		T165	6
auto[1]	values[1]	values[1]	110	1			T36	5		T296	9		T240	9
auto[1]	values[1]	values[2]	293	1			T180	50		T177	16		T192	8
auto[1]	values[1]	values[3]	139	1			T27	34		T24	17		T167	12
auto[1]	values[1]	values[4]	141	1			T9	4		T44	3		T175	5
auto[1]	values[1]	values[5]	136	1			T44	18		T177	11		T126	20
auto[1]	values[1]	values[6]	121	1			T29	10		T86	16		T178	7
auto[1]	values[1]	values[7]	292	1			T33	5		T34	7		T35	66
auto[1]	values[2]	values[0]	157	1			T35	7		T178	56		T183	10
auto[1]	values[2]	values[1]	195	1			T35	45		T196	7		T218	10
auto[1]	values[2]	values[2]	133	1			T32	14		T35	13		T177	5
auto[1]	values[2]	values[3]	250	1			T177	17		T229	67		T196	65
auto[1]	values[2]	values[4]	283	1			T33	6		T51	11		T24	13
auto[1]	values[2]	values[5]	153	1			T191	9		T177	11		T196	52
auto[1]	values[2]	values[6]	202	1			T9	9		T33	7		T126	15
auto[1]	values[2]	values[7]	137	1			T121	4		T27	9		T172	83
auto[1]	values[3]	values[0]	139	1			T8	6		T9	10		T35	3
auto[1]	values[3]	values[1]	215	1			T27	8		T180	10		T167	5
auto[1]	values[3]	values[2]	211	1			T27	4		T191	4		T196	10
auto[1]	values[3]	values[3]	225	1			T8	30		T32	17		T27	6
auto[1]	values[3]	values[4]	197	1			T32	4		T164	131		T237	9
auto[1]	values[3]	values[5]	139	1			T34	9		T214	11		T51	15
auto[1]	values[3]	values[6]	168	1			T8	9		T11	5		T27	9
auto[1]	values[3]	values[7]	185	1			T35	14		T24	20		T164	6
auto[1]	values[4]	values[0]	91	1			T35	8		T149	7		T221	13
auto[1]	values[4]	values[1]	99	1			T32	9		T51	11		T206	13
auto[1]	values[4]	values[2]	135	1			T178	10		T196	5		T218	18
auto[1]	values[4]	values[3]	222	1			T214	30		T35	11		T24	10
auto[1]	values[4]	values[4]	130	1			T165	23		T192	6		T236	19
auto[1]	values[4]	values[5]	228	1			T27	7		T34	5		T201	5
auto[1]	values[4]	values[6]	219	1			T11	7		T34	18		T178	35
auto[1]	values[4]	values[7]	126	1			T11	10		T180	9		T216	13
auto[1]	values[5]	values[0]	244	1			T9	5		T167	18		T164	145
auto[1]	values[5]	values[1]	244	1			T9	34		T11	26		T33	10
auto[1]	values[5]	values[2]	75	1			T9	14		T29	7		T34	4
auto[1]	values[5]	values[3]	104	1			T8	6		T178	14		T177	7
auto[1]	values[5]	values[4]	169	1			T11	7		T32	10		T36	1
auto[1]	values[5]	values[5]	288	1			T27	192		T165	55		T224	10
auto[1]	values[5]	values[6]	175	1			T34	5		T36	29		T24	4
auto[1]	values[5]	values[7]	104	1			T9	11		T35	10		T126	12
auto[1]	values[6]	values[0]	222	1			T8	3		T9	26		T11	5
auto[1]	values[6]	values[1]	133	1			T29	11		T33	8		T24	8
auto[1]	values[6]	values[2]	153	1			T29	4		T27	11		T191	9
auto[1]	values[6]	values[3]	76	1			T126	8		T183	7		T297	7
auto[1]	values[6]	values[4]	195	1			T32	10		T24	9		T180	10
auto[1]	values[6]	values[5]	280	1			T8	6		T85	4		T33	83
auto[1]	values[6]	values[6]	154	1			T9	7		T32	11		T33	2
auto[1]	values[6]	values[7]	158	1			T34	9		T235	38		T175	2
auto[1]	values[7]	values[0]	72	1			T182	8		T236	4		T221	13
auto[1]	values[7]	values[1]	141	1			T177	25		T192	40		T183	18
auto[1]	values[7]	values[2]	319	1			T8	11		T11	8		T29	5
auto[1]	values[7]	values[3]	116	1			T178	10		T172	13		T206	7
auto[1]	values[7]	values[4]	210	1			T29	9		T26	10		T32	12
auto[1]	values[7]	values[5]	85	1			T3	4		T217	13		T148	5
auto[1]	values[7]	values[6]	288	1			T32	79		T189	18		T164	10
auto[1]	values[7]	values[7]	282	1			T176	87		T226	28		T169	18