Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	307	1			T4	10		T8	1		T9	1
auto[ReadAddrCrossIntoMailbox]	272	1			T8	1		T9	1		T11	3
auto[ReadAddrCrossOutOfMailbox]	247	1			T9	1		T11	3		T162	2
auto[ReadAddrCrossAllMailbox]	183	1			T9	3		T11	1		T26	1
auto[ReadAddrOutsideMailbox]	3049	1			T3	4		T8	38		T9	35

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2036

1

T3

2

T4

5

T8

25

auto[1]

2022

1

T3

2

T4

5

T8

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	628	1			T8	4		T9	4		T11	6
read_ops[0x0b]	754	1			T4	2		T8	11		T9	11
read_ops[0x3b]	671	1			T3	2		T4	2		T8	4
read_ops[0x6b]	636	1			T4	2		T8	4		T9	9
read_ops[0xbb]	660	1			T4	4		T8	6		T9	4
read_ops[0xeb]	709	1			T3	2		T8	11		T9	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T33	1		T279	1		T24	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T32	1		T34	1		T201	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T11	1		T34	1		T24	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T32	1		T201	1		T217	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T26	1		T33	1		T34	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	14	1			T9	1		T27	1		T35	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T11	1		T298	1		T152	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T34	1		T35	1		T211	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	210	1			T8	1		T9	3		T11	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T8	3		T11	1		T12	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T4	1		T11	1		T33	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T4	1		T32	1		T34	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T8	1		T11	1		T24	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T32	1		T35	2		T178	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T11	1		T29	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T33	1		T34	1		T176	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T9	1		T33	1		T34	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T26	1		T178	1		T206	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T8	7		T9	6		T11	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T8	3		T9	4		T11	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T4	1		T29	2		T32	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T4	1		T212	2		T33	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T33	1		T34	1		T176	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T33	1		T34	2		T201	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T35	1		T172	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T32	1		T27	1		T51	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T24	1		T178	1		T192	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T9	1		T51	1		T164	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	240	1			T3	1		T8	2		T9	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	247	1			T3	1		T8	2		T9	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	18	1			T4	1		T291	2		T34	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T4	1		T27	1		T291	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T26	1		T214	1		T299	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T32	1		T34	1		T35	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T11	1		T27	1		T24	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T33	2		T51	2		T35	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T34	1		T206	1		T224	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T27	1		T126	1		T240	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	238	1			T8	1		T9	2		T11	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	240	1			T8	3		T9	7		T11	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T4	2		T27	1		T279	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T4	2		T8	1		T27	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T27	1		T164	2		T177	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T9	1		T11	1		T176	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T24	1		T178	1		T172	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T33	1		T34	1		T211	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T34	1		T35	1		T24	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T32	1		T206	1		T217	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T8	2		T9	1		T11	6
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	231	1			T8	3		T9	2		T11	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T11	1		T32	2		T27	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T9	1		T11	1		T29	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T26	1		T176	1		T126	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T33	1		T178	2		T167	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T162	1		T27	1		T33	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T11	1		T162	1		T29	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T164	1		T182	1		T236	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T9	1		T178	2		T44	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T3	1		T8	11		T9	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	250	1			T3	1		T9	4		T11	2